| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708205000 | Normalization | 27 |
| 20080215651 | Signal Separation Device, Signal Separation Method, Signal Separation Program and Recording Medium - A frequency domain transforming section | 09-04-2008 |
| 20090006511 | POLYNOMIAL-BASIS TO NORMAL-BASIS TRANSFORMATION FOR BINARY GALOIS-FIELDS GF(2m) - Basis conversion from polynomial-basis form to normal-basis form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions. | 01-01-2009 |
| 20090006512 | NORMAL-BASIS TO CANONICAL-BASIS TRANSFORMATION FOR BINARY GALOIS-FIELDS GF(2m) - Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions. | 01-01-2009 |
| 20090300087 | Computation processor, information processor, and computing method - A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit. | 12-03-2009 |
| 20100174764 | REUSE OF ROUNDER FOR FIXED CONVERSION OF LOG INSTRUCTIONS - A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number. | 07-08-2010 |
| 20100205233 | REFLECTIONLESS FILTERS - Reflectionless low-pass, high-pass, band-pass, and band-stop filters, as well as a method for designing such filters is disclosed. The filters function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications. | 08-12-2010 |
| 20100205234 | METHOD AND APPARATUS FOR DETECTING SIGNAL USING CYCLO-STATIONARY CHARACTERISITICS - A method and apparatus for detecting a signal using a cyclo-stationary characteristic value is provided. A method of detecting a signal using a cyclo-stationary characteristic value includes: calculating cyclo-stationary characteristic values with respect to a cyclic frequency domain of an input signal; multiplying the calculated cyclo-stationary characteristic values with each other; and detecting the signal from the input signal based on the result of the multiplication. | 08-12-2010 |
| 20100250635 | VECTOR MULTIPLICATION PROCESSING DEVICE, AND METHOD AND PROGRAM THEREOF - Intended is to reduce power consumption without requiring shift of an operand. A vector multiplication processing device comprising a speed-up circuit (a fixed point overflow foresight circuit | 09-30-2010 |
| 20100306290 | METHOD AND APPARATUS FOR SPATIO-TEMPORAL COMPRESSIVE SENSING - A method and apparatus for spatio-temporal compressive sensing, which allows accurate reconstruction of missing values in any digital information represented in matrix or tensor form, is disclosed. The method of embodiments comprises three main components: (i) a method for finding sparse, low-rank approximations of the data of interest that account for spatial and temporal properties of the data, (ii) a method for finding a refined approximation that better satisfies the measurement constraints while staying close to the low-rank approximations obtained by SRMF, and (iii) a method for combining global and local interpolation. The approach of embodiments also provides methods to perform common data analysis tasks, such as tomography, prediction, and anomaly detection, in a unified fashion. | 12-02-2010 |
| 20110040815 | Apparatus and method for performing fused multiply add floating point operation - A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus | 02-17-2011 |
| 20110072063 | Abstraction Apparatus for Processing Data - An abstraction apparatus for processing data is provided. The abstraction apparatus implements an abstraction layer that supports a variety of physical objects (hardware). The abstraction apparatus only manages information related to data denormalization and/or denormalization separately without embedding the information in the logical objects (software), thereby reducing overhead due to the normalization and/or denormalization. | 03-24-2011 |
| 20110153699 | 16-POINT TRANSFORM FOR MEDIA DATA CODING - In general, techniques are described for implementing a 16-point inverse discrete cosine transform (IDCT) that is capable of applying multiple IDCTs of different sizes. For example, an apparatus comprising a 16-point inverse discrete cosine transform of type II (IDCT-II) unit may implement the techniques of this disclosure. The 16-point IDCT-II unit performs these IDCTs-II of different sizes to transform data from a spatial to a frequency domain. The 16-point IDCT-II unit includes an 8-point IDCT-II unit that performs one of the IDCTs-II of size 8 and a first 4-point IDCT-II unit that performs one of the IDCTs-II of size 4. The 8-point IDCT-II unit includes the first 4-point DCT-II unit. The 16-point IDCT-II unit also comprises an inverse 8-point DCT-IV unit that includes a second 4-point IDCT-II unit and a third 4-point IDCT-II unit. Each of the second and third 4-point IDCT-II units performs one of the IDCTs-II of size 4. | 06-23-2011 |
| 20110219052 | DISCRETE FOURIER TRANSFORM IN AN INTEGRATED CIRCUIT DEVICE - Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets. | 09-08-2011 |
| 20110231460 | APPARATUS AND METHOD FOR FLOATING-POINT FUSED MULTIPLY ADD - A fused multiply add (FMA) unit includes an alignment counter configured to calculate an alignment shift count, an aligner configured to align an addend input based on the alignment shift count and output an aligned addend, a multiplier configured to multiply a first multiplicand input and a second multiplicand input and output a product, an adder configured to add the aligned addend and the product and output a sum without determining the sign of the sum or complementing the sum, a normalizer configured to receive the sum directly from the adder and normalize the sum irrespective of the sign of the sum and output a normalized sum, and a rounder configured to round and complement-adjust the normalized sum and output a final mantissa. | 09-22-2011 |
| 20110320512 | Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection - A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format. | 12-29-2011 |
| 20120011182 | DECIMAL FLOATING-POINT SQUARE-ROOT UNIT USING NEWTON-RAPHSON ITERATIONS - A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the exponent. | 01-12-2012 |
| 20120124117 | FUSED MULTIPLY-ADD APPARATUS AND METHOD - A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero. | 05-17-2012 |
| 20120173597 | LEADING SIGN DIGIT PREDICTOR FOR FLOATING POINT NEAR SUBTRACTOR - An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position. The larger of the two numbers is designated as the subtrahend and the smaller as the minuend. Wires and logic align the subtrahend relative to the minuend by the not more than one digit position and invert the aligned subtrahend. A plurality of NAND gates performs a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits. A zero value is assigned to the most significant bit of the prediction string. A string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend. | 07-05-2012 |
| 20140089361 | ARITHMETIC PROCESSING APPARATUS AND AN ARITHMETIC PROCESSING METHOD - Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision. | 03-27-2014 |
| 20140297704 | Parallel Device For Solving Linear Equation Set In Finite Field - The present invention relates to a parallel device for solving linear equations over finite fields, including a processor, an input port, an output port, a pivot finding component, a partial inversion component, a normalization component and an elimination component. The processor is connected to each of the pivot finding component, the partial inversion component, the normalization component, the elimination component, and the input port and the output port. The partial inversion component is connected to the elimination component and the normalization component. The pivot finding component is connected to the elimination component. The present invention enables parallel computing to a certain extent with fast solving speed and simple design, and thus can be widely used in various engineering fields. | 10-02-2014 |
| 20150106414 | SYSTEM AND METHOD FOR IMPROVED FRACTIONAL BINARY TO FRACTIONAL RESIDUE CONVERTER AND MULTIPLER - Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. | 04-16-2015 |
| 20150355112 | COMPUTATION APPARATUS, PROGRAM, AND X-RAY IMAGING SYSTEM - A computation apparatus includes a normalization unit configured to normalize values of two of distributions including a distribution of absorption information of a subject, a distribution of phase information of the subject, and a distribution of scattering information of the subject which are calculated by using a projection image of the subject by X-rays, and a calculation unit configured to calculate a difference or quotient of the normalized two distributions and obtain a composite distribution. | 12-10-2015 |
| 20150378679 | UNDERFLOW/OVERFLOW DETECTION PRIOR TO NORMALIZATION - Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value. | 12-31-2015 |
| 20160048374 | EMULATION OF FUSED MULTIPLY-ADD OPERATIONS - At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value. | 02-18-2016 |
| 20160092169 | STANDALONE FLOATING-POINT CONVERSION UNIT - A data processing apparatus includes floating-point adder circuitry and floating-point conversion circuitry that generates a floating-point number as an output by performing a conversion on any input having a format from a list of formats including: an integer number, a fixed-point number, and a floating-point number having a format smaller than the output floating-point number. The floating-point conversion circuitry is physically distinct from the floating-point adder circuitry. | 03-31-2016 |
| 20160161975 | Excess-Fours Processing in Direct Digital Synthesizer Implementations - Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided. Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to he responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time. | 06-09-2016 |
| 20160253152 | SPLITABLE AND SCALABLE NORMALIZER FOR VECTOR DATA | 09-01-2016 |
