| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 706027000 |
Architecture
| 87 |
| 706033000 |
Semiconductor neural network
| 25 |
| 706041000 |
Digital neural network
| 8 |
| 706038000 |
Analog neural network | 5 |
| 20080243740 | Calibrating A Tester Using ESD Protection Circuitry - An apparatus includes a circuit element that requires calibration, a calibration circuit for use in calibrating the circuit element, and a damping diode electrically connectable in a first path that includes the calibration circuit and electrically connectable in a second path that excludes the calibration circuit. The first path is for electrically connecting the calibration circuit and the circuit element, and the second path is for use in protecting the apparatus from electrostatic discharge. A switching circuit is used to switch the clamping diode between the first path and the second path. | 10-02-2008 |
| 20150379396 | PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE ARRAY LAYOUT - Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout. | 12-31-2015 |
| 20100217735 | RESISTIVE ELEMENT, NEURON ELEMENT, AND NEURAL NETWORK INFORMATION PROCESSING DEVICE - A neuron element is provided having an input part that receives a plurality of input signals and, in response to the respective input signals, creates weighted signals as the products of the input signals and connection weights corresponding to the input signals, an addition part that obtains the total sum of the plurality of weighted signals, and an output part that outputs an output signal as a function of the total sum, a functional molecular element having a current-voltage characteristic in which the current flowing through the element is represented as a function having an inflection point with respect to the applied voltage is used as an element that defines the output signal, and the output signal is defined as a function of the total sum based on the current-voltage characteristic of this element in the region including the inflection point. Thereby, a neuron element that includes an output part formed of a simple circuit and has an analogous output characteristic, and a neural network information processing device employing it are provided. | 08-26-2010 |
| 20140164300 | Analyzing Social Network - Disclosed is a method and system for analyzing a social network, the method comprising: segregating, by a processor, the social network into a plurality of groups of users, wherein each group of users has a unique identity in the social network; mining, by the processor, data from a group of users of the plurality of groups of users; identifying a plurality of social variables from the data, wherein the plurality of social variables comprises at least one of a number of users, connections of the users, interactions of the users, affinity of the users, or posts by the users; equating a social variable of the plurality of social variables with a thermodynamic variable of a plurality of thermodynamic variables; determining quantitative values of the plurality of thermodynamic variables based upon the plurality of social variables; generating a virtual thermodynamics system based upon the quantitative values for analyzing the social network. | 06-12-2014 |
| 20220138548 | ANALOG HARDWARE IMPLEMENTATION OF ACTIVATION FUNCTIONS - An analog neural network including a hardware activation function is provided. A layer of the analog neural network includes a sequence of processing elements that receives analog signals, perform MAC operations on the analog signals, and generates analog outputs. The analog outputs are provided to an analog circuitry that can apply an activation function on the analog outputs. The output of the analog circuitry are also analog signals, which can further be provided to the next layer in the network. The analog circuitry may include a differential pair of transistors to compute the tan h activation function. Alternatively, the analog circuitry may include a comparator and multiplexer to compute the ReLU activation function. Compared with digital implementation of activation functions, the analog circuitry eliminates the need of converting the analog outputs of the layer to digital signals and the need of converting the result of the activation function to analog signals. | 05-05-2022 |
| 706034000 |
Hybrid network (i.e., analog and digital) | 2 |
| 20110119215 | HARDWARE ANALOG-DIGITAL NEURAL NETWORKS - An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller. | 05-19-2011 |
| 20120150781 | INTEGRATE AND FIRE ELECTRONIC NEURONS - An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated. | 06-14-2012 |
| Entries |
| Document | Title | Date |
|---|
| 20080228682 | Generating Simulated Neural Circuits - A first array of simulated neurons having trees of output branches and a second array of simulated neurons having trees of input branches are generated. Thereafter, the output branches of one or more of the simulated neurons of the first array and the input branches of one or more of the simulated neurons of the second array are grown and connections are formed between individual output branches of the simulated neurons of the first array and individual input branches of the simulated neurons of the second array that grow to within a vicinity of each other. | 09-18-2008 |
| 20080228683 | Activity-Dependent Generation of Simulated Neural Circuits - A simulated neural circuit includes a plurality of simulated neurons. The simulated neurons have input branches that are configured to connect to a plurality of inputs and activate in response to activity in the inputs to which they are connected. In addition, the simulated neurons are configured to activate in response to activity in their input branches. Initial connections are formed between various input branches and various inputs and a set of the inputs are activated. Thereafter, the stability of connections between input branches and inputs to which they are connected is moderated based on the activated set of inputs and a pattern of activity generated in the input branches and simulated neurons in response to the activated set of inputs. | 09-18-2008 |
| 20090094180 | METHOD OF REAL-TIME CRYSTAL PEAK TRACKING FOR POSITRON EMISSION TOMOGRAPHY (PET) AVALANCHE-PHOTODIODES (APD) DETECTOR - The present invention provides a method of real-time crystal peak tracking for avalanche-photodiode (APD) detectors on positron emission tomography (PET) scanners that satisfies the need to compensate for the significant gain drifting due to thermal variations in APD detectors on PET scanners. | 04-09-2009 |
| 20090171874 | METHOD AND APPARATUS FOR CONFIGURING A COMMUNICATION CHANNEL - A method of configuring a communication channel prior to the transmission of an input signal along the communication channel, the communication channel comprising a plurality of sub-channels, the method comprising determining the strength of the input signal and in accordance with the determined signal strength, selecting a set of the plurality of sub-channels and transmitting said in put signal along the set of sub-channels in parallel, wherein each of the sub-channels has a predetermined noise characteristic such that the set of selected sub-channels exhibits a combined noise characteristic in which the standard deviation of the noise is proportional to the signal strength. | 07-02-2009 |
| 20090307165 | NERVE EQUIVALENT CIRCUIT, SYNAPSE EQUIVALENT CIRCUIT AND NERVE CELL BODY EQUIVALENT CIRCUIT - By mathematizing input/output relations of a nerve circuit, a synapse and a cell body, it is intended to provide a nerve equivalent circuit, a synapse equivalent circuit and a cell body equivalent circuit whereby electrical characteristics in accordance with the physiological functions and physical structures of nerve cells are faithfully reproduced. A nerve equivalent circuit simulating the electrical characteristics of nerve cells wherein an input signal f | 12-10-2009 |
| 20090313195 | Artificial neural network architecture - An artificial neural network apparatus comprising an array of neural units, each comprising a router, at least one neuron device and at least one synapse unit. The routers of respective neural units communicate with one another using data packets. The synapse units receive and create analogue signals, the routers converting these signals from or into packet form for communication between neural units. The use of routers in this way simplifies the required interconnectivity between neural units in the array and so facilitates the creation of large artificial neural networks. | 12-17-2009 |
| 20100042566 | ELECTRONIC BRAIN MODEL WITH NEURON TABLES - A method of emulating the human brain with its thought and rationalization processes is presented here, as well as a method of storing human-like thought. The invention provides for inclusion of psychological profiles, experience and societal position in an electronic emulation of the human brain. This permits a realistic human-like response by that emulation to the people and the interactive environment around it. | 02-18-2010 |
| 20100042567 | METHOD FOR OPERATING ELECTRONIC BRAIN MODEL WITH REINFORCEMENT MEMORY - A method of emulating the human brain with its thought and rationalization processes is presented here, as well as a method of storing human-like thought. The invention provides for inclusion of psychological profiles, experience and societal position in an electronic emulation of the human brain. This permits a realistic human-like response by that emulation to the people and the interactive environment around it. | 02-18-2010 |
| 20100161532 | DETERMINATION OF GRAPH CONNECTIVITY METRICS USING BIT-VECTORS - Determination of a connectivity-metrics for graphs representative of networks of interest. A graph that represents a network of interest is accessed. The graph includes nodes representing points in the network of interest, and edges corresponding to the nodes. Bit-vectors are generated corresponding to the nodes and/or edges, wherein individual bits in the bit-vectors respectively provide a logical indication of connectedness. The connectivity-metric is then determined by applying a logical bit operation to the plurality of bit-vectors. Examples of connectivity metrics include a connected components, shortest paths, betweenness, clustering, and tree-based determinations. | 06-24-2010 |
| 20110161268 | FRAMEWORK FOR THE EVOLUTION OF ELECTRONIC NEURAL ASSEMBLIES TOWARD DIRECTED GOALS - Methods and systems for the evolution of electronic neural assemblies toward directed goals. A compact computing architecture includes electronics that allows users of such an architecture to create autonomous agents, in a real or a virtual world and add intelligence to machines. An intelligent machine is composed of four basic modules: one or more sensors, one or more motors, a (Reward Input Output System) RIOS, and a cortex. A number of genetically evolved detectors can project both to cortex and RIOS. At first the neurons within the cortex evolve to predict the structure of the sensory data followed by the structure of proprioceptive activations of its own motor system. Finally, once the cortex has learned its sensory and motor programs, it evolves to predict the reward signals, which comes in multiple channels but is dominated by the detection of the aquisition of free-energy. | 06-30-2011 |
| 20110289034 | Neural Processing Unit - The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described. | 11-24-2011 |
| 20120254087 | ELECTRONIC BRAIN MODEL WITH NEURON TABLES - A method of emulating the human brain with its thought and rationalization processes is presented here, as well as a method of storing human-like thought. The invention provides for inclusion of psychological profiles, experience and societal position in an electronic emulation of the human brain. This permits a realistic human-like response by that emulation to the people and the interactive environment around it. | 10-04-2012 |
| 20120271783 | OPTIMAL TECHNIQUE SEARCH METHOD AND SYSTEM - Disclosed are an optimal technique search method and system that can enable a more effective search for optimal techniques for problem solutions than in the past through the use of a neural network employing genetic algorithm. Provided therein are an execution unit ( | 10-25-2012 |
| 20120330873 | Delay Generator Using a Programmable Resistor Based on a Phase-Change Material - A delay generator comprises at least one programmable resistor R | 12-27-2012 |
| 20130024410 | METHOD AND APPARATUS OF NEURONAL FIRING MODULATION VIA NOISE CONTROL - Certain aspects of the present disclosure support a technique for neuronal firing modulation via noise control. Response curve of a typical neuron with a threshold can transition from not firing to always firing with a very small change in the neuron's input, thus limiting the range of excitable input patterns for the neuron. By introducing local, region and global noise terms, the slope of the neuron's response curve can be reduced. This may enable a larger set of input spike patterns to be effective in causing the neuron to fire, i.e., the neuron can be responsive to a large range of input patterns instead of an inherently small set of patterns in a noiseless situation. | 01-24-2013 |
| 20130031039 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING SPIKE EVENT IN NEUROMORPHIC CHIP - An apparatus and a method for transmitting and receiving a spike event in a neuromorphic chip. A transmission apparatus of the neuromorphic chip outputs addresses sequentially and repeatedly to an address bus, and when a spike generated by a neuron is detected by the transmission apparatus, outputs a strobe at a first time when one of the addresses being output sequentially and repeatedly becomes identical to an address of the neuron that generated the spike. A receiving apparatus of the neuromorphic chip inputs an address through the address bus at a strobe detection time when the strobe is detected by the receiving apparatus. | 01-31-2013 |
| 20130198121 | MULTI-COMPARTMENT NEURON SUITABLE FOR IMPLEMENTATION IN A DISTRIBUTED HARDWARE MODEL BY REDUCING COMMUNICATION BANDWIDTH - Embodiments of the present invention provide a neural module comprising a multilevel hierarchical structure of neural compartments. Each neural compartment is interconnected to one or more neural compartments of a previous level and a next hierarchical level in the hierarchical structure. Each neural compartment integrates spike signals from interconnected neural compartments of a previous hierarchical level, generates a spike signal in response to the integrated spike signals reaching a threshold of said neural compartment, and delivers a generated spike signal to interconnected neural compartments of a next hierarchical level. Each neural compartment is further interconnected to one or more external spiking systems, such that said neural compartment integrates spike signals from interconnected external spiking systems, and delivers a generated spike signal to interconnected external spiking systems. The neural compartments of a neural module include one soma compartment and a plurality of dendrite compartments. Each neural compartment is excitatory or inhibitory. | 08-01-2013 |
| 20130297541 | SPIKING NEURAL NETWORK FEEDBACK APPARATUS AND METHODS - Apparatus and methods for feedback in a spiking neural network. In one approach, spiking neurons receive sensory stimulus and context signal that correspond to the same context. When the stimulus provides sufficient excitation, neurons generate response. Context connections are adjusted according to inverse spike-timing dependent plasticity. When the context signal precedes the post synaptic spike, context synaptic connections are depressed. Conversely, whenever the context signal follows the post synaptic spike, the connections are potentiated. The inverse STDP connection adjustment ensures precise control of feedback-induced firing, eliminates runaway positive feedback loops, enables self-stabilizing network operation. In another aspect of the invention, the connection adjustment methodology facilitates robust context switching when processing visual information. When a context (such an object) becomes intermittently absent, prior context connection potentiation enables firing for a period of time. If the object remains absent, the connection becomes depressed thereby preventing further firing. | 11-07-2013 |
| 20130311415 | LEARNING METHOD OF NEURAL NETWORK CIRCUIT - A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a bipolar sawtooth pulse voltage, and a first input signal has a bipolar sawtooth pulse waveform. For a period during which the first input signal is permitted to be input to a first electrode of a variable resistance element, the bipolar sawtooth pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element is input to a control electrode of the variable resistance element. The resistance value of the variable resistance element changes due to an electric potential difference between the first electrode and the control electrode, the electric potential difference being generated depending on an input timing difference between a voltage applied to the first electrode and the voltage applied to the control electrode. | 11-21-2013 |
| 20130325777 | SPIKING NEURON NETWORK APPARATUS AND METHODS - Apparatus and methods for heterosynaptic plasticity in a spiking neural network having multiple neurons configured to process sensory input. In one exemplary approach, a heterosynaptic plasticity mechanism is configured to select alternate plasticity rules when performing neuronal updates. The selection mechanism is adapted based on recent post-synaptic activity of neighboring neurons. When neighbor activity is low, a regular STDP update rule is effectuated. When neighbor activity is high, an alternate STDP update rule, configured to reduce probability of post-synaptic spike generation by the neuron associated with the update, is used. The heterosynaptic mechanism impedes that neuron to respond to (or learn) features within the sensory input that have been detected by neighboring neurons, thereby forcing the neuron to learn a different feature or feature set. The heterosynaptic methodology advantageously introduces competition among neighboring neurons, in order to increase receptive field diversity and improve feature detection capabilities of the network. | 12-05-2013 |
| 20140032464 | MULTI-COMPARTMENT NEURONS WITH NEURAL CORES - Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron. | 01-30-2014 |
| 20140114894 | Method for Finding Shortest Pathway between Neurons in A Neural Network - The present invention discloses a method for finding shortest pathways between neurons in a neural network, including: establishing a three dimensional or higher dimensional neural space database (which may be neuron image database) by a processing device in a storage space, wherein the three dimensional or higher dimensional neural space database includes a plurality of neurons distributed therein. Then, it is determined whether there is a connection between each of the plurality of neurons in the three dimensional or higher dimensional neural space database and the others of the plurality of neurons in the three dimensional or higher dimensional neural space database by the processing device, and subsequently a shortest pathway table of all of a plurality of connected neurons is calculated via an All-pairs Shortest Paths algorithm and is stored in the storage space. | 04-24-2014 |
| 20140136459 | METHOD AND SYSTEM FOR KANBAN CELL NEURON NETWORK - A system for machine cognition includes Kanban cells (KC), Kanban cell neurons (KCN), and Kanban cell neuron networks (KCNN). The KC is an asynchronous AND-OR gate without feedback that is self-timing by the input data to process until input is equal to output. Input is a four-valued logic (4 VL) based on the set {contradiction, true, false, tautology} of four-valued bit code (4 vbc) where contradiction is equivalent to null. Access to a sparsely filled look up table (LUT) is minimized in hardware with a 2-bit value per logical signal. | 05-15-2014 |
| 20140156578 | FIRING RATE INDEPENDENT SPIKE MESSAGE PASSING IN LARGE SCALE NEURAL NETWORK MODELING - A neural network portion comprising N pre-synaptic neurons capable each of firing an action potential, wherein the number N can be encoded in a word of n bits;
| 06-05-2014 |
| 20140258199 | STRUCTURAL DESCRIPTIONS FOR NEUROSYNAPTIC NETWORKS - Embodiments of the invention provide a method comprising creating a structural description for at least one neurosynaptic core circuit. Each core circuit comprises an interconnect network including plural electronic synapses for interconnecting one or more electronic neurons with one or more electronic axons. The structural description defines a desired neuronal activity for the core circuits. The desired neuronal activity is simulated by programming the core circuits with the structural description. The structural description controls routing of neuronal firing events for the core circuits. | 09-11-2014 |
| 20140330762 | ELECTRONIC BRAIN MODEL WITH NEURON TABLES - A method of emulating the human brain with its thought and rationalization processes is presented here, as well as a method of storing human-like thought. The invention provides for inclusion of psychological profiles, experience and societal position in an electronic emulation of the human brain. This permits a realistic human-like response by that emulation to the people and the interactive environment around it. | 11-06-2014 |
| 20140337262 | CONVOLUTION OPERATION CIRCUIT AND OBJECT RECOGNITION APPARATUS - In a convolution operation circuit, a first and a second shift registers provide data to a first and a second inputs of a plurality of multipliers, a first and a second storage units store data to be supplied to the first and the second shift registers, a plurality of cumulative adders accumulate output from the plurality of multipliers, a third storage unit latches output from the plurality of cumulative adders at predetermined timing, a fourth storage unit stores data to be stored in the first and the second storage units and data output from the third storage unit, and a control unit sets data stored in the first and the second storage units to the first and the second shift registers at predetermined timing, causes the first and the second shift registers to perform shift operations in synchronization with an operation of the cumulative adder. | 11-13-2014 |
| 20150112909 | CONGESTION AVOIDANCE IN NETWORKS OF SPIKING NEURONS - A method for managing a neural network includes monitoring a congestion indication in a neural network. The method further includes modifying a spike distribution based on the monitored congestion indication. | 04-23-2015 |
| 20150294217 | METHODS, SYSTEMS AND COMPUTER PROGRAM PRODUCTS FOR NEUROMORPHIC GRAPH COMPRESSION USING ASSOCIATIVE MEMORIES - Methods, systems and computer program products memorize multiple inputs into an artificial neuron that includes multiple dendrites each having multiple dendrite compartments. Operations include computing coincidence detection as distal synapse activation that flows from more proximal ones of the dendrite compartments to a soma of the artificial neuron, generating a dendritic action potential responsive to the coincidence detection from a non-zero activation value input received at a corresponding one of the dendrite compartments that includes a non-zero receptivity, and responsive to generating the dendritic action potential, decrementing the activation value and the receptivity and passing the decremented activation value to a next one of the dendrite compartments. | 10-15-2015 |
| 20150310328 | Neural Network Architecture, Production Method And Programs Corresponding Thereto - A method of producing data representing an identifier of a neuron from a cluster of L neurons belonging to a neural network having C clusters. L and C are natural integers of values greater than or equal to two. Each neuron has at least two states. The method includes, for at least one current cluster C | 10-29-2015 |
| 20150324684 | NEUROMORPHIC HARDWARE FOR NEURONAL COMPUTATION AND NON-NEURONAL COMPUTATION - Embodiments of the invention provide a neurosynaptic system comprising a delay unit for receiving and buffering axonal inputs, and a neural computation unit for generating neuronal outputs by performing a set of computations based on at least one axonal input received by the delay unit. The system further comprises a permutation unit for receiving external inputs to the system, and transmitting external outputs from the system. The permutation unit maps each external input received as either an axonal input to the delay unit or an external output from the system. The permutation unit maps each neuronal output generated by the neural computation unit as either an axonal input to the delay unit or an external output from the system. The neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the neurons with the axons. | 11-12-2015 |
| 20160004959 | MEMRISTOR APPARATUS - A memristor apparatus includes meta-stable switching elements and an AHAH (Anti-Hebbian and Hebbian) feedback mechanism that operates the meta-stable switching elements. | 01-07-2016 |
| 20160019453 | ASYMMETRICAL MEMRISTOR - Embodiments of the present invention provide a memristor having a first electrode, a second electrode and a memristive layer arranged between the first electrode and the second electrode. Thereby, the memristor is adapted to obtain an asymmetrical current density distribution in the memristive layer. | 01-21-2016 |
| 20160055408 | PERIPHERAL DEVICE INTERCONNECTIONS FOR NEUROSYNAPTIC SYSTEMS - Embodiments of the invention provide a system and circuit interconnecting peripheral devices to neurosynaptic core circuits. The neurosynaptic system includes an interconnect that includes different types of communication channels. A device connects to the neurosynaptic system via the interconnect. | 02-25-2016 |
| 20160098629 | EFFICIENT AND SCALABLE SYSTEMS FOR CALCULATING NEURAL NETWORK CONNECTIVITY IN AN EVENT-DRIVEN WAY - Systems and methods achieving scalable and efficient connectivity in neural algorithms by re-calculating network connectivity in an event-driven way are disclosed. The disclosed solution eliminates the storing of a massive amount of data relating to connectivity used in traditional methods. In one embodiment, a deterministic LFSR is used to quickly, efficiently, and cheaply re-calculate these connections on the fly. An alternative embodiment caches some or all of the LFSR seed values in memory to avoid sequencing the LFSR through all states needed to compute targets for a particular active neuron. Additionally, connections may be calculated in a way that generates neural networks with connections that are uniformly or normally (Gaussian) distributed. | 04-07-2016 |
| 20160125287 | NEUROMORPHIC SYNAPSES - A neuromorphic synapse with a resistive memory cell connected in circuitry having first and second input terminals. The input terminals respectively receive pre-neuron and post-neuron action signals, each having a read portion and a write portion, in use. The circuitry includes an output terminal for providing a synaptic output signal which is dependent on resistance of the memory cell. The circuitry is configured such that the synaptic output signal is provided at the output terminal in response to application at the first input terminal of the read portion of the pre-neuron action signal, and such that a programming signal, for programming resistance of the memory cell, is applied to the cell in response to simultaneous application of the write portions of the pre-neuron and post-neuron action signals at the first and second input terminals respectively. The synapse can be adapted for operation with identical pre-neuron and post-neuron action signals. | 05-05-2016 |
| 20160379109 | CONVOLUTIONAL NEURAL NETWORKS ON HARDWARE ACCELERATORS - A hardware acceleration component is provided for implementing a convolutional neural network. The hardware acceleration component includes an array of N rows and M columns of functional units, an array of N input data buffers configured to store input data, and an array of M weights data buffers configured to store weights data. Each of the N input data buffers is coupled to a corresponding one of the N rows of functional units. Each of the M weights data buffers is coupled to a corresponding one of the M columns of functional units. Each functional unit in a row is configured to receive a same set of input data. Each functional unit in a column is configured to receive a same set of weights data from the weights data buffer coupled to the row. Each of the functional units is configured to perform a convolution of the received input data and the received weights data, and the M columns of functional units are configured to provide M planes of output data. | 12-29-2016 |
| 20190147329 | THIN-FILM LARGE-AREA CLASSIFIER | 05-16-2019 |
| 20220138527 | PROCESS FOR PROCESSING DATA BY AN ARTIFICIAL NEURAL NETWORK WITH GROUPED EXECUTIONS OF INDIVIDUAL OPERATIONS TO AVOID SIDE-CHANNEL ATTACKS, AND CORRESPONDING SYSTEM - Process and system for processing data by an artificial neural network comprising several pooling or convolutional layers all associated with neural matrices, including for each layer of the several successive layers obtaining a reordered matrix, obtaining a division of the reordered matrix into a plurality of contiguous submatrices having given widths and heights, and grouping execution of the individual operations to be performed for each submatrix. | 05-05-2022 |
| 20220138540 | INTEGRATED CIRCUIT WITH A CONFIGURABLE NEUROMORPHIC NEURON APPARATUS FOR ARTIFICIAL NEURAL NETWORKS - The present disclosure relates to an integrated circuit comprising a first neuromorphic neuron apparatus. The first neuromorphic neuron apparatus comprises an input and an accumulation block having a state variable for performing an inference task on the basis of input data comprising a temporal sequence. The first neuromorphic neuron apparatus may be switchable in a first mode and in a second mode. The accumulation block may be configured to perform an adjustment of the state variable using a current input signal of the first neuromorphic neuron apparatus and a decay function indicative of a decay behavior of the apparatus. The state variable may be dependent on previously received one or more input signals of the first neuromorphic neuron apparatus. | 05-05-2022 |
