| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 706033000 | Semiconductor neural network | 25 |
| 20080275832 | Electronic Synapse Device - An electronic synapse device comprising a substrate formed from semiconductor material; a first input for receiving a weighting signal; a second input for receiving a signal from a pre-synaptic neuron device; an insulating layer provided between the first and second inputs and the semiconductor material; and an output, the second input being located between the first input and the output. Upon application of the weighting signal to the first input a quantity of charge accumulates in said substrate in the region said first input. Subsequently, upon application of the pre-synaptic signal to the second input, the charge is transferred to a region of the substrate that is substantially in register with the second input whereupon the charge causes an output signal to be generated at the output. | 11-06-2008 |
| 20090292661 | Compact Circuits and Adaptation Techniques for Implementing Adaptive Neurons and Synapses with Spike Timing Dependent Plasticity (STDP). - This invention pertains to compact synaptic circuits and networks comprising compact synaptic circuits that exhibit functional characteristics of biological synapses and networks of synapses including, but not limited to, spike timing dependent plasticity (“STDP”). Temporal coincidence of pre- and post-synaptic action potentials across the synapses of the present invention induces proportional Hebbian synaptic weight updates. Networks of the synapses of the present invention operated according to the methods of this invention are designed to implement biological learning functions, such as STDP. | 11-26-2009 |
| 20100042568 | ELECTRONIC BRAIN MODEL WITH NEURON REINFORCEMENT - A method of emulating the human brain with its thought and rationalization processes is presented here, as well as a method of storing human-like thought. The invention provides for inclusion of psychological profiles, experience and societal position in an electronic emulation of the human brain. This permits a realistic human-like response by that emulation to the people and the interactive environment around it. | 02-18-2010 |
| 20100223220 | ELECTRONIC SYNAPSE - An electronic synapse device is provided. One embodiment of the invention includes a metastable switching synaptic device. Changing conductance of the metastable switching synaptic device occurs by receiving opposite signed first and second voltage pulses at the metastable switching synaptic device where magnitude of the first voltage pulse and the second voltage pulse each are below a switching voltage magnitude threshold. A magnitude difference between the first voltage pulse and the second voltage pulse exceeds the switching voltage magnitude threshold by an amount, wherein the amount is a function of a relative timing between the first voltage pulse and the second voltage pulse. | 09-02-2010 |
| 20100299297 | SYSTEM FOR ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING PHASE CHANGE MEMORY - A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse. | 11-25-2010 |
| 20110106742 | Neuromorphic computer - A neuromorphic computing device utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. The invention provides advantages over software-based neuromorphic computing methods. | 05-05-2011 |
| 20110119214 | AREA EFFICIENT NEUROMORPHIC CIRCUITS - A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit. | 05-19-2011 |
| 20110137843 | Circuits and Methods Representative of Spike Timing Dependent Plasticity of Neurons - A neuromorphic circuit performs functions representative of spiking timing dependent plasticity of a synapse. | 06-09-2011 |
| 20110302120 | ADDRESSING SCHEME FOR NEURAL MODELING AND BRAIN-BASED DEVICES USING SPECIAL PURPOSE PROCESSOR - A special purpose processor (SPP) can use a Field Programmable Gate Array (FPGA) to model a large number of neural elements. The FPGAs or similar programmable device can have multiple cores doing presynaptic, postsynaptic, and plasticity calculations in parallel. Each core can implement multiple neural elements of the neural model. | 12-08-2011 |
| 20120011090 | METHODS AND SYSTEMS FOR THREE-MEMRISTOR SYNAPSE WITH STDP AND DOPAMINE SIGNALING - The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling. | 01-12-2012 |
| 20120011091 | METHODS AND SYSTEMS FOR CMOS IMPLEMENTATION OF NEURON SYNAPSE - Certain embodiments of the present disclosure support techniques for power efficient implementation of neuron synapses with positive and/or negative synaptic weights. | 01-12-2012 |
| 20120011092 | METHODS AND SYSTEMS FOR MEMRISTOR-BASED NEURON CIRCUITS - Certain embodiments of the present disclosure support techniques for designing neuron circuits based on memristors. Bulky capacitors as electrical current integrators can be eliminated and nanometer scale memristors can be utilized instead. Using the nanometer feature-sized memristors, the neuron hardware area can be substantially reduced. | 01-12-2012 |
| 20120011093 | METHODS AND SYSTEMS FOR DIGITAL NEURAL PROCESSING WITH DISCRETE-LEVEL SYNAPES AND PROBABILISTIC STDP - Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training. | 01-12-2012 |
| 20120150780 | PHYSICAL NEURAL NETWORK - A physical neural network includes at least one neuron-like node that sums at least one input signal and generates at least one output signal based on a threshold associated with the at least one input signal, at least one connection network associated with the at least one neuron-like node wherein the at least one connection network comprises a plurality of interconnected connections, such that each connection of the plurality of interconnected connections is strengthened or weakened according to an application of an electric field. In some cases, the threshold can include a threshold below which the at least one output signal is not generated and above which the at least one output signal is generated. | 06-14-2012 |
| 20120303567 | METHOD AND APPARATUS OF PRIMARY VISUAL CORTEX SIMPLE CELL TRAINING AND OPERATION - Certain aspects of the present disclosure present a technique for primary visual cortex (V1) cell training and operation. The present disclosure proposes a model structure of V1 cells and retinal ganglion cells (RGCs), and an efficient method of training connectivity between these two layers of cells such that the proposed method leads to an autonomous formation of feature detectors within the V1 layer. The proposed approach enables a hardware-efficient and biological-plausible implementation of image recognition and motion detection systems. | 11-29-2012 |
| 20120310871 | HIGH-ORDER TIME ENCODER BASED NEURON CIRCUIT - A spike domain circuit responsive to analog and/or spike domain input signals. The spike domain circuit has a hysteresis quantizer for generating a spike domain output signal z(t); a one bit DAC having an input which is coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and having an output which is coupled to a current summing node; and a second order filter stage having two inputs, one of said two inputs being coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and the other of the two inputs being coupled to receive current summed at said current summing node. The second order filter stage has an output coupled to an input of the hysteresis quantizer. The current summing node also receives signals related to the analog and/or spike domain input signals to which the circuit is responsive. The circuit may serve as a neural node and many such circuits may be utilized together to model neurons with complex biological dynamics. | 12-06-2012 |
| 20130073501 | METHOD AND APPARATUS FOR STRUCTURAL DELAY PLASTICITY IN SPIKING NEURAL NETWORKS - Certain aspects of the present disclosure relate to a technique for adaptive structural delay plasticity applied in spiking neural networks. With the proposed method of structural delay plasticity, the requirement of modeling multiple synapses with different delays can be avoided. In this case, far fewer potential synapses should be modeled for learning. | 03-21-2013 |
| 20130173516 | ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES - According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state. | 07-04-2013 |
| 20130185237 | DEVICE AND METHOD FOR DATA PROCESSING - A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analogue pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted. | 07-18-2013 |
| 20140067743 | SYNAPTIC SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons. | 03-06-2014 |
| 20140172763 | Neural Processing Unit - The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described. | 06-19-2014 |
| 20150100532 | GROUP INFORMATION STORING AND RECOGNIZING APPARATUS - A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses. | 04-09-2015 |
| 20150106316 | METHOD AND APPARATUS FOR PROVIDING REAL-TIME MONITORING OF AN ARTIFICAL NEURAL NETWORK - A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register. | 04-16-2015 |
| 20160132766 | Synaptic Neural Network Core Based Sensor System - A sensor system comprises: an energy storage device; an intermittent energy release device electrically coupled to the energy storage device, wherein the intermittent energy release device causes the energy storage device to release stored energy intermittently; a sensor electrically coupled to the energy storage device; a register electrically coupled to the sensor, wherein the register stores readings from the sensor; a synaptic neural network core electrically coupled to the sensor, wherein the synaptic neural network core converts the readings from the sensor into a synthetic context-based object that is derived from the readings and a context object; a transponder electrically coupled to the synaptic neural network core; and a storage buffer within the transponder, wherein the storage buffer stores the synthetic context-based object for transmission by the transponder to a monitoring system. | 05-12-2016 |
| 20160379110 | NEUROMORPHIC PROCESSING DEVICES - A neuromorphic processing device has a device input, for receiving an input data signal, and an assemblage of neuron circuits. Each neuron circuit comprises a resistive memory cell which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals for programming cell resistance to vary the neuron state, and a neuron output circuit for supplying a neuron output signal in response to cell resistance traversing a threshold. The device includes an input signal generator, connected to the device input and the assemblage of neuron circuits, for generating neuron input signals for the assemblage in dependence on the input data signal. The device further includes a device output circuit, connected to neuron output circuits of the assemblage, for producing a device output signal dependent on neuron output signals of the assemblage, whereby the processing device exploits stochasticity of resistive memory cells of the assemblage. | 12-29-2016 |
