Class / Patent application number | Description | Number of patent applications / Date published |
505190000 | Josephson junction, per se (e.g., point contact, bridge, barrier junction, SIS, SNS, SSS, etc.) or Josephson junction with only terminals or connect | 13 |
20080274898 | SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS - A coupling system to couple a first and a second qubit in response to a state of the coupling system that may be set by two input signals. | 11-06-2008 |
20090082209 | SYSTEMS, METHODS AND APPARATUS FOR DIGITAL-TO-ANALOG CONVERSION OF SUPERCONDUCTING MAGNETIC FLUX SIGNALS - A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits. | 03-26-2009 |
20090197770 | BISMUTH BASED OXIDE SUPERCONDUCTOR THIN FILMS AND METHOD OF MANUFACTURING THE SAME - A Bi-based oxide superconductor thin film whose c-axis is oriented parallel to the substrate and whose a-axis (or b-axis) is oriented perpendicular to the substrate, is manufactured in order to obtain a high performance layered Josephson junction using a Bi-based oxide superconductor. The method of manufacturing an a-axis oriented Bi-based oxide superconductor thin film, involves an epitaxial growth process using an LaSrAlO | 08-06-2009 |
20090247410 | JOSEPHSON JUNCTION DEVICE FOR SUPERCONDUCTIVE ELECTRONICS WITH A MAGNESIUM DIBORIDE - A Josephson junction (JJ) device includes a buffered substrate comprising a first buffer layer formed on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer includes a hexagonal compound structure. A trilayer structure is formed on the buffered substrate comprising at least two layers of a superconducting material. A thin tunnel barrier layer is positioned between the at least two layers. The buffered substrate is used to minimize lattice mismatch and interdiffusion in the trilayer structure so as to allow the JJ device to operate above 20 K. 12 | 10-01-2009 |
20100041559 | TUNABLE, SUPERCONDUCTING, SURFACE-EMITTING TERAHERZ SOURCE - A compact, solid-state THz source based on the driven Josephson vortex lattice in a highly anisotropic superconductor such as Bi | 02-18-2010 |
20120157321 | Injection Locked Long Josephson Junction Pulse Source - A superconducting circuit, and a method, are disclosed for generating pulses with stable frequency. The circuit includes an annular Long Josephson Junction (LJJ) capable of producing electrical pulses of a desired frequency due to a steady bias current applied to the LJJ. The circuit further includes an electrical interface for injecting an RF signal of a first frequency into the annular LJJ, resulting in the desired frequency locking onto the first frequency. Typically the first frequency substantially equals the desired frequency. The injection of the RF signal further results in the decrease of the frequency jitter of the desired frequency. The pulses generated in the loop section of the LJJ are outputted through a tail section of the LJJ, and through transmission lines which couple to the tail section. | 06-21-2012 |
20120302446 | JOSEPHSON MAGNETIC SWITCH - New type of Josephson switch based on Josephson superconductor/insulator/ferromagnet/superconductor (SIFS) junction is disclosed. This Josephson SIFS junction has a ferromagnetic (F-) barrier whose magnetization can be controlled by magnetic field pulses. The critical current of such SIFS junction can be controlled using the remanent magnetization of the junction ferromagnetic (F-) barrier. The proposed switch exploits a weakly ferromagnetic (F-) thin-film inner layer with in-plane magnetic anisotropy and small coercive field (for example, Pd | 11-29-2012 |
20130040818 | SUPERCONDUCTING LATCH SYSTEM - A reciprocal quantum logic (RQL) latch system is provided. The latch system comprises an output portion that retains a state of the latch system, and a bi-stable loop that comprises a set input, a reset input and an output coupled to the output portion. A positive single flux quantum (SFQ) pulse on the set input when the latch system is in a reset state results in providing a SFQ current in the output portion representative of the latch system being in a set state. | 02-14-2013 |
20130079230 | IONICALLY CONTROLLED THREE-GATE COMPONENT - A three-port component comprises a source electrode, a drain electrode, and a channel, which is corrected between the source electrode and the drain electrode and which is made of a material haying an electronic conductivity that can be varied by supplying and/or removing ions. The three-port component comprises an ion reservoir, which is in contact with a gate electrode, and which is connected to the channel so that the reservoir is able to exchange ions with the channel when a potential is applied to the gate electrode. Information can be stored on the three-port component by distributing the total number of ions, which are present in the ion reservoir and the channel, between the ion reservoir and the channel. The distribution of ions in the channel and the ion reservoir changes when, and only when, a corresponding driving potential is applied to the gate electrode. Thus, in contrast to RRAMS, there is no time-voltage dilemma. | 03-28-2013 |
20140302995 | METHOD OF FORMING REWORKABLE, THERMALLY CONDUCTIVE AND ELECTRICALLY RESISTIVE BONDING STRUCTURE IN SUPERCONDUCTOR MULTI-CHIP MODULE USING REWORKABLE EPOXY BONDING COMPOSITES AND APPLICATION OF THE SAME - In one aspect, the present invention relates to a method of forming a reworkable, thermally conductive and electrically resistive material as a bonding structure in a module and application of the same. In certain embodiments, a homogeneous solution is prepared with an anisotropic structure, such as single-wall carbon nanotubes (SWCNTs), and an epoxy resin. The homogeneous solution is applied between a carrier and a chip of the module, and cured at a curing temperature for a curing time period to form a reworkable epoxy bonding layer, which has an anisotropic structure loading factor of about 0.1%-1.0% such that the reworkable epoxy bonding layer is thermally conductive and electrically resistive. When the chip is identified as a faulty chip, the module may be heated at a debonding temperature for a debonding time period such that the reworkable epoxy bonding layer debonds, and the chip becomes detachable from the carrier. | 10-09-2014 |
20150080223 | SEMICONDUCTOR DEVICE, SUPERCONDUCTING DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance. | 03-19-2015 |
20150119253 | METHOD FOR INCREASING THE INTEGRATION LEVEL OF SUPERCONDUCTING ELECTRONICS CIRCUITS, AND A RESULTING CIRCUIT - A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers. | 04-30-2015 |
20160149111 | MAGNETIC FLUX-TO-VOLTAGE TRANSDUCER BASED ON JOSEPHSON JUNCTION ARRAYS - A device and method for converting magnetic flux to voltage uses a Fraunhofer pattern of a 1D array of long Josephson junctions. The 1D array of Josephson junctions may include from 1 to 10 | 05-26-2016 |