| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438735000 | Differential etching of semiconductor substrate | 61 |
| 20080214012 | Apparatus and method for fabricating semiconductor devices and substrates - An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads. | 09-04-2008 |
| 20080220615 | METHOD FOR PRODUCING SELF-ALIGNED MASK, ARTICLES PRODUCED BY SAME AND COMPOSITION FOR SAME - A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferential develop in a fashion that is replicates the existing pattern of the substrate. The existing pattern may be comprised of a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. Structures made in accordance with the method. | 09-11-2008 |
| 20080233758 | METHOD FOR FORMING TRENCH AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for forming a trench includes providing a substrate, and forming the trench in the substrate using a gas containing chlorine (Cl | 09-25-2008 |
| 20080268649 | METHOD OF FORMING A MICRO PATTERN IN SEMICONDUCTOR DEVICE - A method of forming a micro pattern in a semiconductor device includes forming an etching object layer and a hard mask layer on a semiconductor substrate. Cross-shaped first auxiliary patterns are formed on the hard mask layer. An insulating layer is formed on the hard mask layer including the first auxiliary pattern. A second auxiliary pattern is formed on the insulating layer between the first auxiliary patterns. An etching process is performed such that the insulating layer remains only on a lower portion of the second auxiliary pattern. The hard mask is etched through an etching process using the first and second auxiliary patterns as an etching mask to form a hard mask pattern. The etching object layer is etched using the hard mask pattern as an etching mask. | 10-30-2008 |
| 20090004874 | Inductively coupled dual zone processing chamber with single planar antenna - A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the processing chamber. One or more gas sources in fluid communication with one or more gas distribution members supply process gas to a first zone adjacent to the first substrate support and a second zone adjacent to the second substrate support. A radio-frequency (RF) antenna adapted to inductively couple RF energy into the interior of the processing chamber and energize the process gas into a plasma state in the first and second zones. The antenna is located between the first substrate support and the second substrate support. | 01-01-2009 |
| 20090004875 | METHODS OF TRIMMING AMORPHOUS CARBON FILM FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE - Methods for forming an ultra thin structure using a method that includes trimming a mask layer during an etching process are provided. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on an underlying layer, trimming the photoresist layer to a first predetermined critical dimension, etching the hardmask layer through openings defined by the trimmed photoresist layer, trimming the hardmask layer to a second predetermined critical dimension, and etching the underlying layer through openings defined by the trimmed hardmask layer. | 01-01-2009 |
| 20090029559 | PHOTO MASK OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING PATTERN USING THE SAME - There is provided a photo mask for forming a specific pattern and a specific pattern formed using the photo mask. Unlike in a related method of forming a specific pattern using a photo mask including cell lines and pad lines, the photo mask is manufactured with cell lines and pad lines, the pad lines each including at least one space line. The photoresist layer is exposed and developed using the photomask to form the photoresist pattern. The etched layer is etched in accordance with the photoresist pattern to form the specific pattern. Therefore, it is possible to improve the pattern uniformity of the semiconductor device and thus to improve yield. | 01-29-2009 |
| 20090042399 | Method for Dry Develop of Trilayer Photoresist Patterns - A method of forming a feature on a multi-layer semiconductor is disclosed. A pattern feature is formed in an uppermost layer of the multi-layer semiconductor. The multilayer semiconductor is etched with a SO | 02-12-2009 |
| 20090081879 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device including processing a substrate to be processed by using an amorphous carbon hard mask that includes processing an amorphous carbon film formed on the substrate to be processed to provide a hard mask, and forming a protective film comprising a silicon oxide film on a sidewall of the amorphous carbon film exposed during or after processing the amorphous carbon film; and the protective film preferably formed by sputtering an intermediate mask comprising at least a silicon oxide on the amorphous carbon film. | 03-26-2009 |
| 20090093125 | CHEMISTRY AND COMPOSITIONS FOR MANUFACTURING INTEGRATED CIRCUITS - In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines. | 04-09-2009 |
| 20090117748 | METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE CAPABLE OF IMPROVING THERMAL EFFICIENCY OF PHASE CHANGE MATERIAL - A method for manufacturing a phase change memory device, capable of improving reset current characteristics of a phase change layer by preventing thermal loss of the phase change layer. An interlayer dielectric layer having a lower electrode contact is formed on a semiconductor substrate. A phase change layer and an upper electrode layer are sequentially formed on the interlayer dielectric layer. Then, an upper electrode and a phase change pattern are formed by etching predetermined portions of the upper electrode layer and the phase change layer using an etching gas having chlorine gas. | 05-07-2009 |
| 20090176376 | Method of fine patterning semiconductor device - For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography. | 07-09-2009 |
| 20090246966 | Method of fine patterning semiconductor device - For integrated circuit fabrication, at least one spacer support structure is formed in a first area over a semiconductor substrate, and a mask material is deposited on exposed surfaces of the spacer support structure and on a second area over the semiconductor substrate. A masking structure is formed on a portion of the mask material in the second area, and the mask material is patterned to form spacers on sidewalls of the spacer support structure and to form a mask pattern under the masking structure. The spacer support structure and the masking structure are comprised of respective high carbon content materials that have been spin-coated and have substantially a same etch selectivity. | 10-01-2009 |
| 20090275208 | Compositions of Matter, and Methods of Removing Silicon Dioxide - Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX | 11-05-2009 |
| 20100009543 | Method For Manufacturing Semiconductor Device - Disclosed is a method for manufacturing a semiconductor device. The method includes sequentially depositing a polishing stop film and a mask oxide film on a semiconductor substrate, forming a photosensitive film pattern on the mask oxide film to expose a device isolation region, sequentially etching the mask oxide film and the polishing stop film under first and second etching process conditions using the photosensitive film pattern as a mask to form a hard mask pattern, and etching the semiconductor substrate under third etching process conditions using the hard mask pattern to form a trench for a device-isolation film. Advantageously, the method simplifies an overall process without using a spacer and secures a desired margin in the subsequent processes, e.g., gap-filling an insulating material in the trench and chemical mechanical polishing of the insulating material. | 01-14-2010 |
| 20100093180 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a first opening pattern and a second opening pattern larger in size than the first opening pattern in a first film formed above a semiconductor substrate and in a second film on the first film, the second film comprising a material different from the first film; forming a blocking film on the second film, the blocking film substantially blocking only the first opening pattern between the first and second opening patterns of the second film; and selectively applying isotropic etching to an inner side face of the second opening pattern of the first film after forming the blocking film, thereby enlarging only the size of the second opening pattern between the size of the first opening pattern and the size of the second opening pattern of the first film. | 04-15-2010 |
| 20100159709 | MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern. | 06-24-2010 |
| 20100173499 | LOW K DIELECTRIC SURFACE DAMAGE CONTROL - A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma. | 07-08-2010 |
| 20100203739 | METHOD FOR ETCHING A LAYER ON A SILICON SEMICONDUCTOR SUBSTRATE - A method for selective etching of an SiGe mixed semiconductor layer on a silicon semiconductor substrate by dry chemical etching of the SiGe mixed semiconductor layer with the aid of an etching gas selected from the group including ClF | 08-12-2010 |
| 20100227478 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR - Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device which can prevent a sealing member from being deteriorated due to a thermal radiation from a heater. The substrate processing apparatus includes a processing container, a substrate stage installed in the processing container, on which a substrate is placed, a heater installed in the substrate stage and configured to heat the substrate, a thermal radiation attenuator adjacent to the processing container, and a gas supply pipe connected to a gas inlet part with a sealing member interposed therebetween and configured to supply a processing gas to an inside of the processing container, wherein the thermal radiation attenuator is installed on a line connecting the heater and the sealing member. | 09-09-2010 |
| 20100297851 | COMPOSITIONS AND METHODS FOR MULTIPLE EXPOSURE PHOTOLITHOGRAPHY - Compositions for use in multiple exposure photolithography and methods of forming electronic devices using a multiple exposure lithographic process are provided. The compositions find particular applicability in semiconductor device manufacture for making high-density lithographic patterns. | 11-25-2010 |
| 20110065280 | MASK PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The method includes a film-forming process which forms a carbon film, to isotropically coat a surface of a silicon film pattern in which a first line portion formed of a silicon film that is formed on a target etching film on a substrate is arranged, an etchback process which etches back the carbon film such that the carbon film is removed from an upper portion of the first line portion and remains as a side wall portion of the first line portion, and a silicon film removing process which forms a mask pattern in which the side wall portion is arranged, by removing the first line portion. | 03-17-2011 |
| 20110117749 | METHOD FOR REDUCING LINE WIDTH ROUGHNESS WITH PLASMA PRE-ETCH TREATMENT ON PHOTORESIST - A method for reducing line width roughness (LWR) of a feature in an etch layer below a patterned photoresist mask having mask features is provided. The method includes (a) non-etching plasma pre-etch treatment of the photoresist mask, and (b) etching of a feature in the etch layer through the pre-treated photoresist mask using an etching gas. The non-etching plasma pre-etch treatment includes (a1) providing a treatment gas containing H | 05-19-2011 |
| 20110124198 | METHOD OF MANUFACTURING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device comprises forming sacrificial film patterns of a line type in a cell region of a semiconductor substrate and, at the same time, forming pad patterns in a peripheral region of the semiconductor substrate, forming a spacer on sidewalls of each of the sacrificial film patterns and the pad patterns, forming a gap-fill layer on sidewalls of the spacers to thereby form line and space patterns, including the sacrificial film patterns and the gap-fill layers, in the cell region, and separating the line and space patterns of the cell region at regular intervals and, at the same time, etching the pad patterns of the peripheral region to thereby form specific patterns in the peripheral region. | 05-26-2011 |
| 20110130008 | METHOD TO CONTROL CRITICAL DIMENSION - A method to control a critical dimension is disclosed. First, a material layer and a composite patterned layer covering the material layer are provided. The composite patterned layer has a pattern defining a first critical dimension. Later, an etching gas is used to perform an etching step to etch the composite patterned layer and a pattern-transferring step is carried out so that thereby the underlying material layer has a transferred pattern with a second critical dimension which is substantially smaller than the first critical dimension. | 06-02-2011 |
| 20130309873 | METHOD OF SELECTIVELY ETCHING A THREE-DIMENSIONAL STRUCTURE - A method of selectively etching a three-dimensional (3-D) structure includes generating a plasma in contact with the 3-D structure, and illuminating a designated portion of the 3-D structure with a laser beam while the plasma is being generated. Nonilluminated portions of the 3-D structure are etched at a first etch rate, and the designated portion of the 3-D structure is etched at a second etch rate, where the second etch rate is different from the first etch rate. | 11-21-2013 |
| 20140017901 | VAPOUR ETCH OF SILICON DIOXIDE WITH IMPROVED SELECTIVITY - The etching of a sacrificial silicon dioxide (SiO | 01-16-2014 |
| 20160020115 | Etching Method and Storage Medium - An etching method includes disposing a target substrate within a chamber. The target substrate has a first silicon oxide film formed on a surface of the target substrate by a chemical vapor deposition method or an atomic layer deposition method, a second silicon oxide film that includes a thermally-oxidized film and a silicon nitride film. The second silicon oxide film and the silicon nitride are formed adjacent to the first silicon oxide film. The etching method further includes supplying an HF gas and an alcohol gas or water vapor into the chamber to selectively etch the first silicon oxide film with respect to the second silicon oxide film and the silicon nitride film. | 01-21-2016 |
| 20160379835 | GAS PHASE ETCHING SYSTEM AND METHOD - A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer. | 12-29-2016 |
| 438736000 | Utilizing multilayered mask | 16 |
| 20080220616 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A process for manufacturing a semiconductor device, comprising: preparing a substrate in which a silicon-containing resist pattern is formed on a processed-material layer, dry-etching the processed-material layer using the silicon-containing resist pattern as a mask to form a processed-material layer pattern, ashing the silicon-containing resist pattern to leave a silicon-containing residual resist, immersing the substrate on which the silicon-containing residual resist remains into pure water to swell and deform the silicon-containing residual resist, and immersing the substrate on which the swelled and deformed silicon-containing residual resist remains into diluted hydrofluoric acid to remove the silicon-containing residual resist. | 09-11-2008 |
| 20080242100 | SEMICONDUCTOR DEVICE AND FABRICATIONS THEREOF - A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask. | 10-02-2008 |
| 20080248653 | Etchant gas and a method for removing material from a late transition metal structure - An etchant gas and a method for removing at least a portion of a late transition metal structure are disclosed. The etchant gas includes PF | 10-09-2008 |
| 20080248654 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surface of the first photoresist pattern. A second photoresist layer is formed over the BARC layer and the organic layer. An etch process is performed so that the second photoresist layer remains on the BARC layer between the first photoresist patterns and becomes a second photoresist pattern. The organic layer on the first photoresist pattern and between the first and second photoresist patterns is removed. The BARC layer formed below the organic layer is removed. The hard mask layer is etched using the first and second photoresist patterns as an etch mask. The etch target layer is etched using a hard mask pattern as an etch mask. | 10-09-2008 |
| 20080268650 | TRIPLE POLY-SI REPLACEMENT SCHEME FOR MEMORY DEVICES - A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions. | 10-30-2008 |
| 20090142932 | METHOD OF FORMING A HARD MASK PATTERN IN A SEMICONDUCTOR DEVICE - In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus. | 06-04-2009 |
| 20090156014 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device of the present invention includes: forming a first film, a second film and a third film in sequence on a silicon substrate; patterning a resist film formed on the third film by conducting an exposure and developing process for the resist film employing an exposure mask including a phase shifter; selectively dry-etching the third film through a mask of the resist film employing the second film as an etch stop to process the third film into a first pattern; further dry-etching the third film employing the second film as an etch stop to partially remove the third film, thereby processing the third film into a second pattern; patterning the second film employing the third film having the second pattern as a mask; and patterning the first film employing the patterned second film as a mask. | 06-18-2009 |
| 20090163035 | ETCH WITH HIGH ETCH RATE RESIST MASK - A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed. | 06-25-2009 |
| 20090209109 | PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - Provided is a pattern forming method for forming a pattern serving as a mask, which includes: a process for forming a first pattern 105 made of a photoresist; a process for forming a boundary layer 106 at sidewall portions and top portions of the first pattern 105; a process for forming a second mask material layer 107 to cover a surface of the boundary layer 106; a process for removing a part of the second mask material layer 107 to expose top portions of the boundary layer 106; a process for forming a second pattern made of the second mask material layer 107 by etching and removing the boundary layer 106; and a trimming process for reducing a width of the first pattern 105 and a width of the second pattern to predetermined widths. | 08-20-2009 |
| 20100203740 | Process for Increasing Feature Density During the Manufacture of a Semiconductor Device - Methods used during the manufacture of a semiconductor device, such as one that includes forming a plurality of vertically oriented first support features. Each feature comprises first and second sidewalls and the first support features are formed to have a first pitch. A plurality of first mask spacers are formed, wherein one first mask spacer is formed on each first support feature sidewall, and each first mask spacer comprises an exposed, vertically oriented sidewall. A plurality of vertically oriented second support features are formed, wherein one second support feature is formed on the exposed, vertically oriented sidewall of each first mask spacer, and each second support feature is separated from an adjacent second support feature by a gap. A plurality of second mask features are formed, wherein one second mask feature is formed within each gap. The first and second support features are removed, and the first and second mask spacers are left to provide an etch pattern, wherein the first and second mask features have a second pitch. The first pitch is about three times the second pitch. | 08-12-2010 |
| 20100248492 | Method of forming patterns of semiconductor device - A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask. | 09-30-2010 |
| 20100317196 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: forming a first resist on a workpiece; patterning the first resist by performing selective exposure, baking, and development on the first resist; forming a second resist on the workpiece after the patterning the first resist; patterning the second resist by performing selective exposure, baking, and development on the second resist to selectively remove a part of the second resist and remove the first resist left on the workpiece; and processing the workpiece by using the patterned second resist as a mask. | 12-16-2010 |
| 20120252221 | FORMING CURVED FEATURES USING A SHADOW MASK - Processes for making a profile-transferring substrate surface and membranes having curved features are disclosed. A profile-transferring substrate surface having a curved feature is created by isotropic plasma etching through a shadow mask. The shadow mask has a through hole which has a lower portion adjacent to the bottom surface of the shadow mask and an upper portion that is above and narrower than the lower portion. The isotropic plasma etching through the shadow mask can create a curved dent in a planar substrate in a central portion of an area enclosed by the bottom opening. After the shadow mask is removed. A uniform layer of material deposited over the exposed surface of the substrate will include a curved feature at the location of the curved dent in the substrate surface. | 10-04-2012 |
| 20120282780 | ETCH WITH HIGH ETCH RATE RESIST MASK - A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed. | 11-08-2012 |
| 20130260568 | MANUFACTURING METHOD FOR THIN FILM TRANSISTOR ARRAY PANEL - A manufacturing method for a thin film transistor array panel includes: providing a gate line including a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer; etching the data wire material layer by using the first photosensitive film pattern as a mask; providing a second photosensitive film pattern by etching back the first photosensitive film pattern; etching the semiconductor material layer by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask to form a source electrode and a drain electrode. The etching the semiconductor material layer uses a first non-sulfur fluorinated gas. | 10-03-2013 |
| 20150380246 | DIMENSION-CONTROLLED VIA FORMATION PROCESSING - Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench. | 12-31-2015 |
| 438737000 | Substrate possessing multiple layers | 16 |
| 20090124088 | METHOD FOR ETCHING A SACRIFICIAL LAYER FOR A MICRO-MACHINED STRUCTURE - A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species. | 05-14-2009 |
| 20100029085 | CLEANING COMPOSITION AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - A cleaning composition of a semiconductor device for laminating an organosiloxane-based thin film and a photoresist layer in this order on a substrate having a low dielectric interlayer insulation film and a copper wiring or a copper alloy wiring, then applying selective exposure and development treatments to the subject photoresist layer to form a photoresist pattern, subsequently applying a dry etching treatment to the organosiloxane-based thin film and the low dielectric interlayer insulation film while using this resist pattern as a mask and then removing the organosiloxane-based thin film, a residue generated by the dry etching treatment, a modified photoresist having been modified by the dry etching treatment and an unmodified photoresist layer located in a lower layer than the modified photoresist, the cleaning composition containing from 15 to 20% by mass of hydrogen peroxide, from 0.0001 to 0.003% by mass of an amino polymethylene phosphonic acid, from 0.02 to 0.5% by mass of potassium hydroxide and water and having a pH of from 7.5 to 8.5, is provided. Also, a method for manufacturing a semiconductor device using the subject cleaning composition is provided. | 02-04-2010 |
| 20100029086 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND STORAGE MEDIUM - A semiconductor device having high reliability is provided by reducing fluorine remaining in a metal forming the semiconductor device. Specifically disclosed is a method for manufacturing a semiconductor device including a fluoride removal step for removing a metal fluoride produced on a metal forming an electrode or wiring of a semiconductor device which is formed on a substrate to be processed. This method for manufacturing a semiconductor device is characterized in that the metal fluoride is removed by supplying formic acid in a gaseous state to the substrate to be processed in the fluoride removal step. | 02-04-2010 |
| 20100216314 | SUBSTRATE PROCESSING METHOD - A substrate processing method that processes a substrate including a processing target layer, an intermediate layer, and a mask layer as stacked in that order. The intermediate layer includes an Si-ARC (Si-containing Anti-Reflection Coating) film and the mask layer has an opening exposing a part of the Si-ARC. The substrate processing method includes a shrink etching step during which an opening width reduction process and an etching process are performed concurrently. In the opening width reduction process, deposits are formed on a sidewall surface of the opening of the mask layer by a plasma generated from a gaseous mixture of an anisotropic etching gas and one of a depositive gas and H | 08-26-2010 |
| 20100330811 | Method for forming via holes - An improved method of forming a via hole is provided. This method makes it possible to form a via hole having a highly accurate processed shape in an insulating body. The insulating body has a multi-layer structure made of different kinds of insulating layers. The insulating body has, for example, a first insulating layer and a second insulating layer on the first insulating layer. The first insulating layer is provided on a lower wiring layer. The method includes a step of forming a first through hole in the second insulating layer by dry etching. The first through hole reaches the first insulating layer. The side wall of the first through hole defines an exposed portion of the second insulating layer. The bottom of the first through hole defines an exposed portion of the first insulating layer. The method also includes a step of assimilating the exposed portion of the second insulating layer and the exposed portion of the first insulating layer so that the exposed portions of the first and second insulating layers have the same composition. The method also includes a step of forming a second through hole extending from the first through hole to the lower wiring layer by dry etching. The first and second through holes defines a via hole. The via hole is made by removing the exposed portion of the first insulating layer. | 12-30-2010 |
| 438738000 | Selectively etching substrate possessing multiple layers of differing etch characteristics | 6 |
| 20140199852 | PATTERN FORMING METHOD - A pattern forming method is provided for forming a pattern of a multilayer film including insulative films and electrically conductive films stacked together and having a hole formed therein on a substrate with the electrically conductive film being selectively accurately indented from an inner peripheral surface of the hole. The pattern forming method includes the steps of: alternately stacking at least two insulative films and at least two polysilicon films on a substrate to form a multilayer film including the at least two insulative films and the at least two polysilicon films; forming a hole extending through the at least two insulative films and the at least two polysilicon films in the multilayer film; and selectively etching the polysilicon films from a side wall of the hole through isotropic etching by feeding into the hole an etching gas prepared by diluting fluorine-containing halogen gas with an inert gas. | 07-17-2014 |
| 20160155630 | SUBSTRATE PROCESSING APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM | 06-02-2016 |
| 438739000 | Lateral etching of intermediate layer (i.e., undercutting) | 2 |
| 20080207004 | Method of Forming a Semiconductor Structure - A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium. | 08-28-2008 |
| 20150140829 | METHOD FOR SEMICONDUCTOR MANUFACTURING - A method includes followings operations. A semiconductor substrate is provided. A photoresist is formed on the semiconductor substrate. Dopants are inserted into the photoresist to carbonize a portion of the photoresist. An etch steam is sprayed on the semiconductor substrate and the photoresist. A hole is formed at a surface of the photoresist by the etch steam. The etch steam is flowed into the hole so as to remove a portion of the photoresist at an interface between the semiconductor substrate and the photoresist. The photoresist is decorticated from the semiconductor substrate. | 05-21-2015 |
| 438740000 | Utilizing etch stop layer | 2 |
| 20090061641 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming micro patterns, an etch target layer, a hard mask layer, a silicon-containing bottom anti-reflective coating (BARC) layer, and first auxiliary patterns are formed over a semiconductor substrate. The silicon-containing BARC layer is etched to form silicon-containing BARC patterns. Insulating layers are formed on a surface of the silicon-containing BARC patterns and the first auxiliary patterns. A second auxiliary layer is formed on the hard mask layer and the insulating layers. An etch process is performed such that the second auxiliary layer remains on the hard mask layer between the silicon-containing BARC patterns thereby forming second auxiliary patterns. The insulating layers on the first auxiliary patterns and between the silicon-containing BARC patterns and the second auxiliary patterns are removed. The hard mask layer is etched thereby forming hard mask patterns. The etch target layer is etched using the hard mask patterns as an etch mask. | 03-05-2009 |
| 20090124089 | Device and Method for Stopping an Etching Process - A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being different from the second etchant. | 05-14-2009 |
| 438742000 | Electrically conductive material (e.g., metal, conductive oxide, etc.) | 3 |
| 20090098737 | METHOD OF PATTERNING MULTILAYER METAL GATE STRUCTURES FOR CMOS DEVICES - A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer. | 04-16-2009 |
| 20090149029 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - An inventive semiconductor device production method is a method for producing a semiconductor device having a metal interconnection by etching a metal film including a lower layer of a first metal material and an upper layer of a second metal material different from the first metal material. In the production method, the upper layer is selectively etched under conditions such that an etching rate for the upper layer is higher than an etching rate for the lower layer. The etching is terminated when the lower layer is exposed. Thereafter, the upper layer is over-etched under conditions such that the etching rate for the upper layer is substantially equal to the etching rate for the lower layer. Then, the lower layer is selectively etched. | 06-11-2009 |
| 20100248493 | PHOTOMASK BLANK, PROCESSING METHOD, AND ETCHING METHOD - A photomask blank is provided comprising a transparent substrate, a single or multi-layer film including an outermost layer composed of chromium base material, and an etching mask film. The etching mask film is a silicon oxide base material film formed of a composition comprising a hydrolytic condensate of a hydrolyzable silane, a crosslink promoter, and an organic solvent and having a thickness of 1-10 nm. The etching mask film has high resistance to chlorine dry etching, ensuring high-accuracy processing of the photomask blank. | 09-30-2010 |
| 438743000 | Silicon oxide or glass | 2 |
| 20120178263 | SUBSTRATE PROCESSING APPARATUS - [Problem] To provide a substrate processing apparatus capable of preventing adherence of hydrogen fluoride to an inner surface the like of a chamber. | 07-12-2012 |
| 20140273496 | METHOD OF REMOVING A METAL HARDMASK - Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiF | 09-18-2014 |
