| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438704000 | Having liquid and vapor etching steps | 34 |
| 20080220614 | METHOD FOR MANUFACTURING IMAGE SENSOR DEVICE - The invention is directed to a method for manufacturing an image sensor device. The method comprises steps of forming a photodiode and a transistor on a substrate. A salicide block is formed over a photo-sensing region of the photodiode. An interconnects processes is performed several times to forming a plurality of dielectric layers over the substrate and interconnects between the dielectric layers. A photolithography and etching process is performed to remove the dielectric layers over the photo-sensing region to expose the salicide block over the photo-sensing region. | 09-11-2008 |
| 20080242099 | Method for forming contact hole using dry and wet etching processes in semiconductor device - A method for forming a contact hole in a semiconductor device includes forming an insulation layer over a substrate, forming a hard mask pattern over the insulation layer, forming a first contact hole by partially etching the insulation layer, forming a spacer on sidewalls of the first contact hole, forming a second contact hole to expose the substrate by etching the remaining insulation layer within the first contact hole, forming a third contact hole by horizontally etching the second contact hole, wherein a line width of the third contact hole is wider than that of the first contact hole, and removing the hard mask pattern and the spacer. | 10-02-2008 |
| 20080261403 | METHOD FOR OBTAINING HIGH-QUALITY BOUNDARY FOR SEMICONDUCTOR DEVICES FABRICATED ON A PARTITIONED SUBSTRATE - One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of trenches. The process then forms a multilayer structure, which comprises a first doped layer, an active layer, and a second doped layer, on one of the deposition platforms. Next, the process removes sidewalls of the multilayer structure. | 10-23-2008 |
| 20080280450 | Method of two-step backside etching - The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate. | 11-13-2008 |
| 20090087994 | METHOD OF FORMING FINE PATTERNS AND MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME - A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including the first fine pattern is wet-etched to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained in the wet-etching the semiconductor crystal has a bottom surface and a sidewall that have unique crystal planes, respectively. The present fine-pattern forming process can be advantageously applied to a semiconductor light emitting device, particularly, to a phonic crystal structure required to have fine patterns or a structure using a surface plasmon resonance principle. | 04-02-2009 |
| 20090233447 | CONTROL WAFER RECLAMATION PROCESS - A method of recycling a control wafer having a dielectric layer deposited thereon involves removing most of the dielectric layer by plasma etching leaving a residual film of the dielectric and then removing the residual dielectric film by a wet etching process. The combination of the dry and wet etching provides effective removal of the dielectric material without damaging the wafer substrate and any residual wet etching byproduct particulate remaining on the wafer substrate is then removed by APM cleaning and scrubbing. | 09-17-2009 |
| 20100041236 | NOVEL METHOD TO INTEGRATE GATE ETCHING AS ALL-IN-ONE PROCESS FOR HIGH K METAL GATE - The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate; applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and applying a wet etching process to the semiconductor substrate to remove polymeric residue. | 02-18-2010 |
| 20100041237 | METHOD FOR FORMING A FINE PATTERN USING ISOTROPIC ETCHING - A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer. | 02-18-2010 |
| 20100055915 | Processing apparatus, processing method, and plasma source - [Problems] A processing apparatus and a processing method that shorten a lead time and are more reliable than before in respect of the processing performance are provided. | 03-04-2010 |
| 20100055916 | METHOD FOR DECAPSULATING PACKAGE - A method for decapsulating a package is provided. The method comprises steps of providing a package having a chip therein, wherein the chip has an active surface and a rear surface. Further, the package further comprises a heat sink, a plurality of solder bumps, a substrate, an underfill and a plurality of solder balls. The method further comprises removing the heat sink and removing the substrate together with the solder balls. A dry etching process is performed to remove a portion of the underfill. A wet etching process is performed to remove the rest portion of the underfill. A thermal process solder bump removal process is performed to melt the solder bumps and then a solder bump removal process is performed to remove the melted solder bumps from the active surface of the chip. | 03-04-2010 |
| 20100093177 | METHOD OF CLEANING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER - A silicon wafer surface other than a defect is oxidized by ozone to form a silicon oxide film. A hydrofluoric acid is sprayed and subsequently a cleaning gas is sprayed onto the surface of the silicon wafer. | 04-15-2010 |
| 20100105211 | NANO-CRYSTAL ETCH PROCESS - A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant. | 04-29-2010 |
| 20100120255 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a mask material onto the foundation film so as to cover the core pattern, the mask material being crosslinkable upon supply acid from the core pattern; etching back the mask material to expose an upper surface of the core pattern and remove a portion of the mask material formed on the end portion of the core pattern, thereby leaving a mask material side wall portion formed on a side wall of the core pattern; and removing the core pattern and processing the foundation film by using the mask material sidewall portion left on the foundation film as a mask. | 05-13-2010 |
| 20100120256 | METHOD FOR REMOVING ETCHING RESIDUES FROM SEMICONDUCTOR COMPONENTS - A method for cleaning structured surfaces of semiconductor components to remove photoresist and etching residues after the etching of the surface, comprising: a) removal of the photoresist, b) treatment of the surface with an acidic aqueous solution comprising one or more acids and one or more oxidizing agents, c) treatment of the surface with an alkaline aqueous solution and d) washing of the surface with demineralized water, the steps a), b) and c) being effected before step d). | 05-13-2010 |
| 20100144156 | METHOD TO INTEGRATE MICRO ELECTRO MECHANICAL SYSTEM AND CMOS IMAGE SENSOR - A method to integrate a micro electro mechanical system and a CMOS image sensor is disclosed. First a substrate is provided. The substrate includes a micro electro mechanical system (MEMS) region and a CMOS image sensor (CIS) region. The micro electro mechanical system region includes a micro electro mechanical system component and the CMOS image sensor region includes a CMOS image sensor element. Second, an etching procedure is performed on the substrate to form a micro electro mechanical system trench and a CMOS image sensor trench. The etching procedure includes at least a dry etching and at least a wet etching. | 06-10-2010 |
| 20100173498 | TRIM PROCESS FOR CRITICAL DIMENSION CONTROL FOR INTEGRATED CIRCUITS - Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive. | 07-08-2010 |
| 20100233882 | SINGLE SILICON-ON-INSULATOR (SOI) WAFER ACCELEROMETER FABRICATION - Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant selectively removes the oxide to expose the SOI wafer substrate. A portion of the SOI substrate under at least one MEMS structure is removed, thereby releasing the MEMS structure to be used in the formation of an accelerometer. | 09-16-2010 |
| 20100248485 | METHOD FOR DIELECTRIC MATERIAL REMOVAL BETWEEN CONDUCTIVE LINES - A method of removing carbon doped silicon oxide between metal contacts is provided. A layer of the carbon doped silicon oxide is converted to a layer of silicon oxide by removing the carbon dopant. The converted layer of silicon oxide is selectively wet etched with respect to the carbon doped silicon oxide and the metal contacts, which forms recess between the metal contacts. | 09-30-2010 |
| 20110111600 | PROCESSING METHOD FOR SOI SUBSTRATE - A method of processing a SOI substrate to form a groove in the SOI substrate in which a silicon layer is stacked on both sides of an oxide layer is disclosed. In accordance with an embodiment of the present invention, the method includes dividing a portion of the silicon layer, in which the groove is to be processed, into a plurality of unit portions, performing dry etching on certain portions of the plurality of divided unit portions such that the oxide layer is exposed and removing remaining portions of the plurality of divided unit portions by removing the oxide layer. | 05-12-2011 |
| 20110177692 | Barrier Layer Removal Method and Apparatus - This invention relates to a method and apparatus by integrating semiconductor manufacturing processes of stress free electrochemical copper polishing (SFP), removal of the Tantalum oxide or Titanium oxide formed during SFP process and XeF | 07-21-2011 |
| 20110183522 | METHOD AND APPARATUS FOR PATTERN COLLAPSE FREE WET PROCESSING OF SEMICONDUCTOR DEVICES - A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern collapse. | 07-28-2011 |
| 20120003835 | METHOD OF ETCHING SACRIFICIAL LAYER - An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process. | 01-05-2012 |
| 20120088370 | Substrate Processing System with Multiple Processing Devices Deployed in Shared Ambient Environment and Associated Methods - A plurality of substrate processing devices are disposed in a separated manner within a shared ambient environment. A conveyance device is disposed within the shared ambient environment and is defined to move a substrate through and between each of the substrate processing devices in a continuous manner. Some substrate processing devices are defined to perform dry substrate processing operations in which an energized reactive environment is created in exposure to the substrate in an absence of liquid material. Some substrate processing devices are defined to perform wet substrate processing operations in which at least one material in a liquid state is applied to the substrate. In one embodiment, a complementary pair of dry and wet substrate processing devices are disposed in the shared ambient environment in a sequential manner relative to movement of the substrate by the conveyance device. | 04-12-2012 |
| 20120100721 | METHOD FOR TREATING A SEMICONDUCTOR WAFER - A method for treating semiconductor wafer includes: providing a stack including a high-k layer including a first oxide material, wherein the first oxide material contains hafnium and/or zirconium, and a cap-layer including a second oxide material, wherein the cap-layer has been deposited on top of the high-k layer, wherein the second oxide material contains lanthanum, a lanthanide and/or aluminium; supplying liquid A to the surface of the semiconductor wafer, liquid A being an aqueous solution containing an oxidizing agent; supplying liquid B to the surface of the semiconductor wafer, liquid B being a liquid with a pH-value lower than 6; and conducting a step SC wherein a liquid C is supplied to the surface of the semiconductor wafer, wherein step SC is carried out after step SB, wherein liquid C is an aqueous acidic solution with a fluorine concentration of at least 10 ppm. | 04-26-2012 |
| 20120122316 | METHOD FOR SURFACE TREATMENT OF A WAFER - An object of the present invention is to provided a wafer exhibiting excellent surface properties, in which variation in reaction, which has been concerned in surface treatment with a diffusion controlled process such as conventional wet treatment, is effectively suppressed in a method for surface treatment of a wafer involving a chemical treatment. | 05-17-2012 |
| 20120289052 | Methods for Manufacturing High Dielectric Constant Films - Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface. | 11-15-2012 |
| 20130034966 | CHEMICAL DISPERSION METHOD AND DEVICE - A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided. | 02-07-2013 |
| 20140273481 | PROCESSING SYSTEMS AND METHODS FOR HALIDE SCAVENGING - Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools. | 09-18-2014 |
| 20140322918 | MICRO-POSTS HAVING IMPROVED UNIFORMITY AND A METHOD OF MANUFACTURE THEREOF - As discussed herein, there is presented an apparatus comprising micro-posts. The apparatus includes a substrate having a planar surface, a plurality of micro-posts located on the planar surface, wherein each micro-post has a base portion on the planar surface and a post portion located on a top surface of the corresponding base portion, and wherein side surfaces of the base portions intersect the planar surface at oblique angles. | 10-30-2014 |
| 20150079795 | Substrate Processing System with Multiple Processing Devices Deployed in Shared Ambient Environment and Associated Methods - A plurality of substrate processing devices are disposed in a separated manner within a shared ambient environment. A conveyance device is disposed within the shared ambient environment and is defined to move a substrate through and between each of the substrate processing devices in a continuous manner. Some substrate processing devices are defined to perform dry substrate processing operations in which an energized reactive environment is created in exposure to the substrate in an absence of liquid material. Some substrate processing devices are defined to perform wet substrate processing operations in which at least one material in a liquid state is applied to the substrate. In one embodiment, a complementary pair of dry and wet substrate processing devices are disposed in the shared ambient environment in a sequential manner relative to movement of the substrate by the conveyance device. | 03-19-2015 |
| 20150087156 | ETCHING METHOD, AND METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE PRODUCT AND SEMICONDUCTOR DEVICE USING THE SAME, AS WELL AS KIT FOR PREPARATION OF ETCHING LIQUID - A method of etching a semiconductor substrate, having the steps of: preparing an etching liquid by mixing a first liquid with a second liquid to be in the range of pH from 8.5 to 14, the first liquid containing a basic compound, the second liquid containing an oxidizing agent; and then applying the etching liquid to a semiconductor substrate on a timely basis for etching a Ti-containing layer in or on the semiconductor substrate. | 03-26-2015 |
| 20150099363 | Method of Fabricating III-Nitride Based Semiconductor on Partial Isolated Silicon Substrate - A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened. | 04-09-2015 |
| 20150140827 | METHODS FOR BARRIER LAYER REMOVAL - Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas. | 05-21-2015 |
| 20180025927 | SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD, AND STORAGE MEDIUM | 01-25-2018 |
