Entries |
Document | Title | Date |
20080206989 | Method for Producing Vertical Electrical Contact Connections in Semiconductor Wafers - The invention relates to a method for producing vertical electrical connections (micro-vias) in semiconductor wafers for the fabrication of semiconductor components. The method is characterized by the following steps: —application of a protective resist to the wafer front side—patterning of the protective resist on the wafer front side such that the contacts to be connected to the wafer rear side become free—laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side—cleaning of the wafer (debris removal)—application of a plating base to the wafer rear side and into the laser-drilled passage holes—application of gold by electrodeposition onto the metallized wafer rear side and the passage holes—resist stripping of the protective resist—application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side. | 08-28-2008 |
20080206990 | Methods For Fabricating Semiconductor Components With Conductive Interconnects - A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components. | 08-28-2008 |
20080233740 | Method for Producing Electrically Conductive Bushings Through Non-Conductive or Semiconductive Substrates - The present invention relates to a method for producing electrical bushings through non-conductive or semiconductive substrates, which are particularly suitable for electrical applications. The method is characterized in that a semiconductor substrate or a non-conductive substrate ( | 09-25-2008 |
20080254618 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method. | 10-16-2008 |
20080261396 | SUBSTRATE HAVING HIGH ELECTRICAL CONNECTION RELIABILITY OF A PENETRATING VIA CONNECTED TO WIRINGS AND A METHOD FOR MANUFACTURING THE SAME - A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole. | 10-23-2008 |
20080268638 | Substrate with Feedthrough and Method for Producing the Same - A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel. | 10-30-2008 |
20080280435 | Producing a Covered Through Substrate Via Using a Temporary Cap Layer - The present invention relates to a method for producing a substrate with at least one covered via that electrically and preferably also thermally connects a first substrate side with an opposite second substrate side. The processing involves forming a trench on a the first substrate side remains and covering the trench with a permanent layer on top of a temporary, sacrificial cap-layer, which is decomposed in a thermal process step. The method of the invention provides alternative ways to remove decomposition products of the sacrificial cap-layer material without remaining traces or contamination even in the presence of the permanent layer This is, according to a first aspect of the invention, achieved by providing the substrate trench with an overcoat layer that has holes. The holes in the overcoat layer leave room for the removal of the decomposition products of the cap-layer material. According to the second aspect of the invention, opening the covered trench from the second substrate side and allowing the cap-layer material to be removed through that opening provides a solution. Both methods of the present invention are based on the common idea of using a temporary cap-layer even in a situation where the substrate opening is permanently covered before the removal of the temporary cap-layer | 11-13-2008 |
20080299768 | MANUFACTURING METHOD OF SUBSTRATE WITH THROUGH ELECTRODE - A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode formation step of forming the through electrodes on a support plate, a substrate formation step of forming the substrate, a through electrode reception step of stacking the substrate on the support plate | 12-04-2008 |
20090004854 | Method of Fabricating Flash Memory Device - The present invention relates to a method of fabricating a flash memory device. The method may include forming a first and a second interlayer insulating film on a semiconductor substrate having a cell region, etching the second and first interlayer insulating films, thus forming a contact hole through which a junction region of the cell region is exposed, forming a contact plug within the contact hole, the contact plug having a height lower than that of an interface of the first and second interlayer insulating films, and forming a spacer on sidewalls of the contact hole over the contact plug. | 01-01-2009 |
20090047781 | Methods of Forming Through Substrate Interconnects - A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material. | 02-19-2009 |
20090053892 | Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening. | 02-26-2009 |
20090075478 | SEMICONDUCTOR DEVICE,HAVING A THROUGH ELECTRODE, SEMICONDUCTOR MODULE EMPLOYING THEREOF AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING A THROUGH ELECTRODE - The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes | 03-19-2009 |
20090093117 | METHOD OF MANUFACTURING SUBSTRATE - A method of manufacturing a substrate, includes: (a) forming the through hole by etching the silicon substrate from a first surface of the silicon substrate by a Bosch process; (b) forming a thermal oxide film such that the thermal oxide film covers the first surface of the silicon substrate, a second surface of the silicon substrate opposite to the first surface, and a surface of the silicon substrate corresponding to a side surface of the through hole, by thermally oxidizing the silicon substrate where the through hole is formed; (c) removing the thermal oxide film; (d) forming an insulating film such that the insulating film covers the first and second surfaces of the silicon substrate and the surface of the silicon substrate corresponding to the side surface of the through hole; and (e) forming the through electrode in the through hole on which the insulating film is formed. | 04-09-2009 |
20090098731 | Methods for Forming a Through Via - A through via is constructed in a two-stage process. A void in a portion of the depth of the substrate is filled from a first surface of the semiconductor substrate creating an enclosed volume within the substrate. Thereafter, the enclosed volume is exposed and the remaining portion of the void is filled. | 04-16-2009 |
20090104772 | PROCESS OF FABRICATING CIRCUIT STRUCTURE - A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad. | 04-23-2009 |
20090111263 | Method of Forming Programmable Via Devices - A device is formed by providing a contact via in a dielectric layer, providing a capping layer overlying at least a portion of the contact via, and forming a conductive element in physical contact with the capping layer. The conductive element is formed using a masked deposition process. This process comprises forming a seed layer overlying the capping layer and at least a portion of an uppermost surface of the dielectric layer, forming a masking layer on the seed layer, the masking layer defining an opening exposing a portion of the seed layer that overlies the capping layer, and selectively depositing a conductive material onto the exposed portion of the seed layer. | 04-30-2009 |
20090130846 | SEMICONDUCTOR DEVICE FABRICATION METHOD - Methods of fabricating a semiconductor device including a through-silicon via that is electrically insulated from the semiconductor substrate. An exemplary method includes preparing a semiconductor wafer including a semiconductor substrate, a semiconductor element, an interlayer insulating, pads that are electrically connected to the semiconductor element, and a protective film; forming upper terminals electrically connected to the pads; forming annular grooves below the pads and extending to the interlayer insulating film; forming an annular insulating layer in the annular grooves and forming a bottom insulating film on the bottom surface of the semiconductor substrate; forming electrode-forming extending to the pads; filling the electrode-forming holes with a conductive material to form through-silicon vias electrically connected to the pads; and forming lower terminals on the bottom insulating film electrically connected to the through-silicon vias. | 05-21-2009 |
20090156001 | Structure for reducing stress for vias and fabricating method thereof - A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block. | 06-18-2009 |
20090170313 | Method for Manufacturing Semiconductor Device - A semiconductor device and method for manufacturing the same are provided. A dielectric can be formed on a silicon substrate, and a contact hole can be formed in the dielectric. A portion of the silicon substrate can etched through the contact hole. | 07-02-2009 |
20090191708 | METHOD FOR FORMING A THROUGH SILICON VIA LAYOUT - A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields. | 07-30-2009 |
20090215263 | METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias. | 08-27-2009 |
20090253261 | Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape - A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other, forming in the semiconductor substrate at least one trench of a predetermined geometric shape in the first main surface, lining the at least one trench with a dielectric material, filling the at least one trench with a conductive material, electrically connecting an electrical component to the conductive material of the at least one trench at the first main surface; and mounting a cap to the first main surface. The at least one trench extends to a first depth position D in the semiconductor substrate. The cap encloses at least a portion of the electrical component and the electrical connection between the electrical component and the conductive material. | 10-08-2009 |
20090280647 | SEMICONDUCTOR THROUGH-ELECTRODE FORMING METHOD - When forming a resin material in a through hole, an electrode pad is formed in the bottom portion of the through hole, an insulating material is formed about the periphery of the through hole and a conductive material is formed in the central portion by an inkjet method, inkjet-ejected resins being ejected in such a manner that concavo-convex indentations and projections are formed in the surface thereof, whereby the adhesiveness between the insulating material and the conductive material and the adhesiveness between the insulating material and the inner walls of the through hole can be improved. Therefore, it is possible to suppress mechanical defects such as detachment of conductive material at the interfaces between the inner surface of the through hole and the resin or conductor layer, or electrical defects such as insulation defects, conduction defects, or the like. | 11-12-2009 |
20090298285 | Fabricating a Top Conductive Layer in a Semiconductor Die - According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment. | 12-03-2009 |
20090305502 | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 12-10-2009 |
20100035430 | METHOD OF MAKING THROUGH WAFER VIAS - A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench. | 02-11-2010 |
20100081279 | Method for Forming Through-base Wafer Vias in Fabrication of Stacked Devices - An effective method for forming through-base wafer vias in the fabrication of stacked devices is described. The base wafer can be a silicon wafer in which case the method relates to TSV (through-silicon via) technology. The method affords high removal rates of both silicon and metal (e.g., copper) under appropriate conditions and is tuneable with respect to base wafer material to metal selectivity. | 04-01-2010 |
20100093169 | THROUGH SUBSTRATE VIA PROCESS - A through substrate via (TSV) process is provided. A substrate having a first side and a second side opposite the first side is provided. A plurality of holes is formed in the substrate at the first side. A first dielectric layer is formed on a sidewall and a bottom of the holes. A second dielectric layer is formed in the holes, wherein a material of the second dielectric layer is different from that of the first dielectric layer. A semiconductor device and an interconnect are formed on the substrate at the first side. At least a portion of the substrate at the second side is removed to expose the second dielectric layer in the holes. The second dielectric layer is removed. A conductive layer is formed in the holes. | 04-15-2010 |
20100130008 | THROUGH-VIA AND METHOD OF FORMING - In one embodiment, a method of forming a via includes forming an first opening in the semiconductor substrate, wherein the first opening has a bottom and sidewalls, forming a sacrificial fill in the first opening, forming a dielectric layer over the sacrificial fill, forming a second opening in the dielectric layer, wherein the second opening is over the sacrificial fill, removing the sacrificial fill from the first opening after forming the second opening, and forming a conductive material in the first opening and second opening. | 05-27-2010 |
20100136783 | METHOD OF MANUFACTURING THROUGH-VIA - Disclosed is a method of manufacturing a through-via. The through-via manufacturing method includes forming a core-via hole in a wafer, forming a suction-via hole adjacent to the core-via hole in the wafer, forming a via core in the core-via hole, forming a polymer-via hole connected to the suction-via hole in the wafer, filling the polymer-via hole with polymer solution by creating a vacuum inside the polymer-via hole by drawing air out of the suction-via hole, and polishing the wafer such that the via core formed in the core-via hole is exposed. | 06-03-2010 |
20100167534 | METHOD FOR FABRICATING A SEMICONDUCTOR CHIP DEVICE HAVING THROUGH-SILICON-VIA (TSV) - A semiconductor device with TSV and its fabrication method are revealed. The semiconductor device primarily comprises a chip and a flexible metal wire inside. A redistributed trace layer and a passivation layer are formed on the active surface of the chip. A through hole penetrates the chip from the active surface to the back surface, in which an insulation layer is disposed. The flexible metal wire has a first terminal and a second terminal where the first terminal is bonded to a redistributed pad of the redistributed trace layer and the second terminal passes through the through hole and protrudes from the back surface of the chip. Therefore, the flexible metal wire passing through the chip has two protruded integral terminals to achieve high stress resistance TSV with lower costs for good electrical connections of vertical stacking chips. | 07-01-2010 |
20100190338 | Method for manufacturing semiconductor device - An insulator layer is formed on a part of semiconductor substrate to form an isolation layer that insulates and separates active elements from each other in the first region, and to form a dummy portion which is composed of a base material of the semiconductor substrate exposed in the insulator layer in a second region. Active elements are formed in the first region. A silicide layer is formed on the first and second regions excluding at least a portion in which the TSV electrode should be formed. At least one TSV hole extending from a reverse surface side of the semiconductor substrate to an electrode pad via the second region is formed. A conductive film is formed on the inner wall of the TSV hole to form a TSV electrode electrically connected to the electrode pad. | 07-29-2010 |
20100203726 | Method of Forming a Through Substrate Via in a Compound Semiconductor - A method is provided for forming a through substrate via in a compound semiconductor having a transistor on a front side of the substrate. The method comprises forming a protective stop pad over a contact area on the front side of the substrate, forming a contact pad overlying the protective stop pad, such that the contact pad is in contact with a terminal of the transistor and plasma etching a backside of the substrate to form a contact coupling via to the protective stop pad. The method further comprises performing a chemical wet etch to remove the protective stop pad and depositing a conductive contact layer in the contact coupling via to provide a conductive contact to the contact pad. | 08-12-2010 |
20100297844 | INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer. | 11-25-2010 |
20100304565 | PROCESSED WAFER VIA - An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer. | 12-02-2010 |
20100317190 | CONDUCTIVE INTERCONNECT STRUCTURES AND FORMATION METHODS USING SUPERCRITICAL FLUIDS - Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via. | 12-16-2010 |
20100330803 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even. | 12-30-2010 |
20110027990 | SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip includes a semiconductor substrate, a through via provided in a through hole that passes through the semiconductor substrate, insulating layers laminated on the semiconductor substrate, a multi-layered wiring structure having a first wiring pattern and a second wiring pattern, and an external connection terminal provided on an uppermost layer of the multi-layered wiring structure, wherein the through via and the external connection terminal are connected electrically by the second wiring pattern. | 02-03-2011 |
20110034027 | Structure and Process for the Formation of TSVs - An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer. | 02-10-2011 |
20110039409 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a capacitor including a lower electrode and a upper electrode, and a capacitive film formed therebetween; a first via group including one or more first vias which is electrically connected to the lower electrode; and a second via group including one or more second vias which is electrically connected to the upper electrode and formed simultaneously with the first via group. The semiconductor device is designed by a method including a step of setting the number of the first vias and the second vias so that a value obtained by dividing a capacitance value of the capacitor by the total number of the first vias and the second vias included in the first via group and the second via group is set to be equal to or less than a predetermined value. | 02-17-2011 |
20110076846 | SEMICONDUCTOR DEVICE HAVING FINE CONTACTS AND METHOD OF FABRICATING THE SAME - A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes. | 03-31-2011 |
20110111591 | Semiconductor Wafer Having Through-Hole Vias on Saw Streets With Backside Redistribution Layer - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die. | 05-12-2011 |
20110117739 | METHODS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURES - The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed. | 05-19-2011 |
20110129998 | CLEANING LIQUID FOR LITHOGRAPHY AND METHOD FOR FORMING WIRING - Provided are a cleaning liquid for lithography that exhibits excellent corrosion suppression performance in relation to tungsten, and excellent removal performance in relation to a resist film or the like, and a method for forming a wiring using the cleaning liquid for lithography. The cleaning liquid for lithography according to the present invention includes a quaternary ammonium hydroxide, a water-soluble organic solvent, water, an inorganic salt and an anti-corrosion agent represented by a general formula (1) below. | 06-02-2011 |
20110129999 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device including: an electrode formation step of forming an electrode on one surface of a semiconductor substrate; a through hole formation step of forming a through hole starting from a position on the other surface corresponding to the position of the electrode; a first insulating layer formation step of forming a first insulating layer on at least an inner circumferential surface, a periphery of an opening, and a bottom surface of the through hole; a modifying step of reforming a first portion of the first insulating layer formed on the bottom surface of the through hole; a modified region removal step of removing the modified region; and a conductive layer formation step of forming a conductive layer on the electrode exposed inside the through hole and on the first insulating layer such that the conductive layer is electrically connected with the electrode. | 06-02-2011 |
20110143536 | Method for Making an Aperture in a Carrier and Electrically Connecting Two Opposite Faces of the Carrier - Disclosed is a method for making an aperture in a carrier and electrically connecting two opposite faces of the carrier. At first, a carrier is provided. Secondly, a heater is provided for heating a portion of the carrier in an environment rich in oxygen, thus making an aperture in the carrier and forming an isolative layer on the wall of the aperture synchronously. Finally, the aperture is filled with a conductive material. | 06-16-2011 |
20110151667 | Methods of Manufacturing Three-Dimensional Semiconductor Devices and Related Devices - A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed. | 06-23-2011 |
20110165776 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 07-07-2011 |
20110171829 | Method for Forming a Via in a Substrate and Substrate with a Via - The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the second surface of the substrate to expose the first conductive metal, the center insulating material and the first insulating material. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even. | 07-14-2011 |
20110177688 | PACKAGING BOARD AND MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFOR, AND PORTABLE DEVICE - A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area of the conductor and on the other face of the insulating layer; a fourth process of preparing a substrate on which a circuit element is formed, the second wiring being formed on the substrate; and a fifth process of embedding the conductor in the insulating layer by press-bonding the insulating layer and the substrate in a state where the conductor on which the first wiring layer is provided by the third process is disposed counter to the second wiring layer. Wiring is formed without causing damaging to the circuit element. | 07-21-2011 |
20110183517 | METHOD FOR ELECTRON BEAM INDUCED DEPOSITION OF CONDUCTIVE MATERIAL - The invention relates to a method for electron beam induced deposition of electrically conductive material from a metal carbonyl with the method steps of providing at least one electron beam at a position of a substrate ( | 07-28-2011 |
20110195572 | Chip-stacked semiconductor device and manufacturing method thereof - A method of manufacturing a semiconductor device, includes forming a trench surrounding a first area of a semiconductor substrate, the trench having a bottom surface and two side surfaces being opposite to each other, forming a silicon film on the bottom surface and side surfaces of the trench, forming an insulation film on the silicon film in the trench, grinding a bottom surface of the semiconductor substrate to expose the insulation film formed over the bottom surface of the trench, and forming a through electrode in the first area after grinding the bottom surface of the semiconductor substrate, the through electrode penetrating the semiconductor substrate. | 08-11-2011 |
20110207322 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes, but is not limited to, the following processes. A seed layer is formed over a substrate. The seed layer includes first, second, and third portions. A first electrode covering the first portion of the seed layer is formed without forming an electrode on the second and third portions of the seed layer. The third portion of the seed layer is removed so that the first and second portions remain over the substrate, and the first and second portions are separated from each other. | 08-25-2011 |
20110212619 | Semiconductor Device Having Dummy Pattern and the Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming an interlayer dielectric film on a semiconductor substrate including a pattern region and a dummy region, forming a photoresist pattern on the interlayer dielectric film such that the pattern region and the dummy region are partially exposed, etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form a contact hole and a dummy contact hole, filling the contact hole and the dummy contact hole with a conductive material to form a contact plug and a dummy plug, depositing a semiconductor layer on the contact plug and the dummy plug, and subjecting the semiconductor layer to patterning to form a semiconductor layer pattern and a dummy pattern. | 09-01-2011 |
20110217841 | METHOD OF FORMING THROUGH SILICON VIA WITH DUMMY STRUCTURE - A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad. | 09-08-2011 |
20110237075 | Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers - A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. | 09-29-2011 |
20110263120 | THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element. | 10-27-2011 |
20110269311 | GOLD-TIN ETCH USING COMBINATION OF HALOGEN PLASMA AND WET ETCH - The present disclosure relates to an implantable medical device. The implantable medical device includes a component comprising a first substrate bonded to a second substrate. A method for forming the component includes removing a first portion of tin (Sn) from gold tin (AuSn) through a halogen plasma. A first portion of gold (Au) is exposed in response to removing the first portion of the Sn. The first portion of the Au through a wet etch. A second portion of the Sn is exposed in response to removing the first portion of Au. | 11-03-2011 |
20110318922 | METHOD OF FORMING SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 12-29-2011 |
20120009784 | METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES - An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face. | 01-12-2012 |
20120015517 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film. | 01-19-2012 |
20120034777 | Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection - A semiconductor package includes a semiconductor wafer having a plurality of semiconductor die. A contact pad is formed over and electrically connected to an active surface of the semiconductor die. A gap is formed between the semiconductor die. An insulating material is deposited in the gap between the semiconductor die. An adhesive layer is formed over a surface of the semiconductor die and the insulating material. A via is formed in the insulating material and the adhesive layer. A conductive material is deposited in the via to form a through hole via (THV). A conductive layer is formed over the contact pad and the THV to electrically connect the contact pad and the THV. The plurality of semiconductor die is singulated. The insulating material can include an organic material. The active surface of the semiconductor die can include an optical device. | 02-09-2012 |
20120040527 | METHOD OF FORMING METAL LINES OF SEMICONDUCTOR DEVICE - A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material. | 02-16-2012 |
20120083119 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a first insulating interlayer positioned above one surface of a substrate, forming a first hole extended from the surface of the first insulating interlayer to midway of the substrate, forming a through-electrode in the first hole, forming an electro-conductive pattern positioned on the surface of the first insulating interlayer, and connected to one end of the through-electrode, making the other end of the through-electrode expose, by removing the other surface of the substrate, and forming a connection terminal connected to the other end of the through-electrode, on the other surface of the substrate. | 04-05-2012 |
20120094485 | METHOD OF FORMING CONTACTS FOR A SEMICONDUCTOR DEVICE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other. | 04-19-2012 |
20120100715 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE - The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region. | 04-26-2012 |
20120115327 | METHOD OF MANUFACTURING VIA HOLE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING VIA HOLES - A first metal mask has a portion exposed at an opening of a second metal mask. The second metal mask is formed to be thicker than the first metal mask. The thickness of the first and second metal masks is such that the etching at an opening of the first mask reaches a source electrode when the etching at the opening of the second mask substantially reaches a semiconductor device forming layer. | 05-10-2012 |
20120135600 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G | 05-31-2012 |
20120142185 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring. | 06-07-2012 |
20120142186 | METHOD FOR MANUFACTURING INTERPOSER - A method for manufacturing an interposer equipped with a plurality of through-hole electrodes comprises a laser light converging step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region in the object; an etching step of anisotropically etching the object after the laser light converging step so as to advance etching selectively along the modified region and form a plurality of through holes in the object, each through hole being tilted with respect to a thickness direction of the object and having a rectangular cross section; an insulating film forming step of forming an insulating film on an inner wall of each through hole after the etching step; and a through-hole electrode forming step of inserting a conductor into the through holes so as to form the through-hole electrodes after the insulating film forming step; wherein the plurality of through holes are arranged such that the through holes aligning in the tilted direction are staggered in a direction perpendicular to the tilted direction as seen from a main face of the object. | 06-07-2012 |
20120142187 | SEMICONDUCTOR DEVICE WITH THROUGH SUBSTRATE VIA - A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube. | 06-07-2012 |
20120156874 | CHEMICAL MECHANICAL POLISHING SLURRY COMPOSITION AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE USING THE SAME - A slurry composition for chemical mechanical polishing, including 0.1% to 20% by weight of an aminosilane-surface treated polishing agent; 0.001% to 5% by weight of an additive selected from amino acids, amino acid derivatives, salts thereof, and combinations thereof; 0.0001% to 0.5% by weight of a corrosion inhibitor; and 0.01% to 5% by weight of an oxidizing agent, with the balance being a solvent, is provided. The slurry composition for chemical mechanical polishing has a conspicuously high polishing rate for silicon oxide films, is capable of selectively preventing the removal of silicon nitride films, does not cause an imbalance in polishing, gives an excellent degree of planarization, has excellent stability over time and dispersion stability, causes less generation of particles and scratches, and produces very satisfactory polished surfaces of barrier metal films and oxide films. | 06-21-2012 |
20120164827 | FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS - A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias. | 06-28-2012 |
20120190193 | AREA EFFICIENT THROUGH-HOLE CONNECTIONS - Using printing technologies to fill conductor materials into holes in silicon substrate, the preferred embodiments of the present improve cost efficiency of through-hole connections. Using silicon substrate as cathode terminal during electrical plating that fill holes in a silicon substrate with conductors, the preferred embodiments of the present improve alignment accuracy and cost efficiency of through-hole manufacturing processes. | 07-26-2012 |
20120220123 | THROUGH-HOLE ELECTRODE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A through-hole electrode substrate related to an embodiment of the present invention is arranged with a semiconductor substrate having a plurality of through-holes, an insulating layer formed with an insulating material on the inner walls of the plurality of through-holes and on at least one surface of the semiconductor substrate, a plurality of through-hole electrodes formed with a metal material inside the through-hole, and a plurality of gas discharge parts formed to contact with each of the plurality of through-hole electrodes which is exposed on at least one surface of the semiconductor substrate, the plurality of gas discharge parts externally discharges gas which is discharged from the inside of the plurality of through-hole electrodes. | 08-30-2012 |
20120244702 | METHOD FOR PRINTING A SUBSTRATE - Embodiments of the present invention generally relate to methods of printing MWT solar cells. The methods include positioning the non-light-receiving side of a solar cell substrate on a support. The solar cell substrate has a plurality of holes formed therethrough. The plurality of holes are then metalized. Metalizing the holes includes applying a first silver-containing paste within the holes, or depositing the first silver-containing paste on the interior surface of the holes. The first silver-containing paste is in electrical communication with the front surface and the back surface of the substrate. Then, a plurality of collection fingers are formed on the front surface of the substrate using a second silver-containing paste. The substrate may then be flipped, and one or more printing processes may be performed on the non-light-receiving side of the substrate. | 09-27-2012 |
20120258594 | On-Chip RF Shields with Backside Redistribution Lines - Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material. | 10-11-2012 |
20120264296 | METHODS OF FORMING THROUGH SILICON VIA OPENINGS - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 10-18-2012 |
20120264297 | METHOD FOR CREATING VIA IN IC MANUFACTURING PROCESS - In a method for creating a via in an IC manufacturing process, a substrate is provided and a circuitry structure is formed over the substrate. Then, a dielectric layer is formed over the circuitry structure; a hard mask is formed on and a trench is created through the dielectric layer; a coating layer is formed on the hard mask, filling the trench; an etch opening is defined in the coating layer by performing a pattern transfer process, wherein a width of the etch opening is greater than a width of the trench; and the bottom of the trench exposed from the etch opening is etched off with the hard mask, thereby creating a via for conductors. | 10-18-2012 |
20120270394 | METHOD OF BEVEL TRIMMING THREE DIMENSIONAL SEMICONDUCTOR DEVICE - A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias. | 10-25-2012 |
20120315758 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device manufacturing method comprises mounting a supporting substrate on a front surface side of a silicon substrate having an interconnection layer and function elements formed on a front surface side, polishing a back surface side of the silicon substrate, forming a mask having an opening and an opening for a dummy hole having a diameter smaller than that of the above opening on the back surface side of the silicon substrate, etching portions exposed to the openings of the mask from the back surface side of the silicon substrate to form a via hole that reaches a part of the interconnection layer and form a dummy hole to an intermediate portion of the silicon substrate, and forming an interconnection material in the via hole. | 12-13-2012 |
20120315759 | METHOD FOR PRODUCING CONTACT OPENINGS IN A SEMICONDUCTOR BODY AND SELF-ALIGNED CONTACT STRUCTURES ON A SEMICONDUCTOR BODY - Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer. | 12-13-2012 |
20120322260 | THROUGH-SILICON VIA FORMING METHOD - A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor. | 12-20-2012 |
20120329276 | METHOD FOR MANUFACTURING A THROUGH HOLE ELECTRODE SUBSTRATE - To provide a method of manufacturing a through hole electrode substrate which comprises forming a plurality of through holes passing through the front and back of a wafer-shaped substrate, forming an insulation film on a surface of the substrate and the though hole, forming a seed layer from a metal on at least one side of the substrate and/or the through hole, forming a metal layer having a cap shape on a bottom part of the through hole on a surface on which the seed layer is formed by an electrolytic plating method supplying direct current to the seed layer for a first time period, and filling a metal material into the plurality of through holes by an electrolytic plating method supplying a pulse current to the seed layer and the metal layer. | 12-27-2012 |
20120329277 | TWO-SIDED SEMICONDUCTOR STRUCTURE - Deep via trenches and deep marker trenches are formed in a bulk substrate and filled with a conductive material to form deep conductive vias and deep marker vias. At least one first semiconductor device is formed on the first surface of the bulk substrate. A disposable dielectric capping layer and a disposable material layer are formed over the first surface of the bulk substrate. The second surface, located on the opposite side of the first surface, of the bulk substrate is polished to expose and planarize the deep conductive vias and deep marker vias, which become through-substrate vias and through-substrate alignment markers, respectively. At least one second semiconductor device and second metal interconnect structures are formed on the second surface of the bulk substrate. The disposable material layer and the disposable dielectric capping layer are removed and first metal interconnect structures are formed on the first surface. | 12-27-2012 |
20130065393 | METHODS OF FORMING SELF-ALIGNED THROUGH SILICON VIA - A method for forming a through silicon via (TSV) in a substrate may include forming a dielectric layer on the substrate; forming an opening through the dielectric layer and into the substrate using a single mask over the dielectric layer; expanding the opening in the dielectric layer, undercutting the single mask, to form an expanded upper portion; removing the single mask; and filling the opening, including the expanded upper portion, with a conductor. A resulting structure may include a substrate; a dielectric layer over the substrate; and a self-aligned through silicon via (TSV) extending through the dielectric layer and the substrate. | 03-14-2013 |
20130089982 | Method of Fabricating a Substrate Having Conductive Through Holes - A method of fabricating a substrate having a plurality of conductive through holes is disclosed. Release films are formed on opposite sides of a substrate, and a plurality of through holes penetrating the release films and the substrate are formed. A first metal layer is formed on the release films and the sidewall of each of the through holes prior to removing the release films and the first metal layer thereon. A second metal layer is formed on the first metal layer on the sidewalls of the through holes by electroless plating. Compared to the prior art, the method is simpler and cheaper to carry out while the conductive through holes and a surface circuit layer thereof are fabricated separately, thereby avoiding disadvantage of forming a circuit layer on the surface of the substrate too thick. | 04-11-2013 |
20130102149 | LINER PROPERTY IMPROVEMENT - Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 μm. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall. | 04-25-2013 |
20130102150 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE HAVING SMALL CONTACT AND RELATED DEVICES - A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode. | 04-25-2013 |
20130115769 | METHOD FOR FORMING AN AIR GAP AROUND A THROUGH-SILICON VIA - Semiconductor devices with air gaps around the through-silicon via are formed. Embodiments include forming a first cavity in a substrate, filling the first cavity with a sacrificial material, forming a second cavity in the substrate, through the sacrificial material, by removing a portion of the sacrificial material and a portion of the substrate below the sacrificial material, filling the second cavity with a conductive material, removing a remaining portion of the sacrificial material to form an air gap between the conductive material and the substrate, and forming a cap over the air gap. | 05-09-2013 |
20130122702 | INTEGRATED VOID FILL FOR THROUGH SILICON VIA - A microelectronic assembly and related method of forming a through hole extending through a first chip and a second chip are provided. The first and second chip have confronting faces, metallic features join the first and second chips leaving a gap chips . A first etch creates a hole through the first chip. The hole has a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening to expose the gap. Material of the first or second chips exposed within the hole is sputtered to form a wall in the gap. A second etch extends the hole into the second chip. An electrically conductive through silicon via can then be formed extending through the first chip, the wall between the chips and into the second chip. | 05-16-2013 |
20130164935 | LOW RESISTANCE THROUGH-WAFER VIA - The present invention provides a wafer ( | 06-27-2013 |
20130171819 | METHODS FOR INTEGRATION OF METAL/DIELECTRIC INTERCONNECTS - Described herein are methods for copper/low-k dielectric material integration. The methods involve depositing and curing a low-k dielectric material and depositing a mask on the low-k dielectric material. A via is patterned in the low-k dielectric material and a trench is patterned in the low-k dielectric material. After the via or trench is patterned, a portion of the low-k material is backfilled with a backfill material. The trench and via are filled with copper, then the mask and the copper filling the via are removed. After a first pre-CLN, the backfill material is removed. This creates a robust copper/porous low-k dielectric material interconnect. | 07-04-2013 |
20130178062 | 3D IC METHOD AND DEVICE - A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding. | 07-11-2013 |
20130196506 | Apparatuses and Methods for Gas Mixed Liquid Polishing, Etching, and Cleaning - In accordance with an embodiment of the present invention, a method of polishing a device includes providing a layer having a non-uniform top surface. The non-uniform top surface includes a plurality of protrusions. The method further includes removing the plurality of protrusions by exposing the layer to a fluid that has gas bubbles and a liquid. | 08-01-2013 |
20130203251 | Method for Three-Dimensional Packaging of Electronic Devices - An interposer is fabricated from a lamina. A donor body is provided, ions are implanted into a first surface of the donor body to define a cleave plane, a temporary carrier is separably contacted to the donor body, and the lamina is cleaved from the donor body. The lamina has front surface and a back surface, with a thickness from the front surface to the back surface. A via hole is formed in the lamina, where the via hole extends through the thickness of the lamina. The temporary carrier is removed from the lamina, and the lamina may be fabricated into an interposer for three-dimensional integrated circuit packages. | 08-08-2013 |
20130230985 | Three-Dimensional System-in-Package Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies. | 09-05-2013 |
20130252421 | METHOD OF PROCESSING SILICON AND GLASS SUBSTRATES USING A LASER PEELING TECHNIQUE - According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate. | 09-26-2013 |
20130252422 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - In a method of forming a semiconductor structure, a through-silicon-via (TSV) opening is formed in a substrate. A dielectric layer is formed to continuously extend over the substrate and into the TSV opening. At least one conductive material is formed over the dielectric layer and in the TSV opening. A portion of the at least one conductive material that is over the dielectric layer is removed to form a TSV structure in the substrate. A metallic line is formed in the dielectric layer. A portion of the substrate is removed, such that the TSV structure continuously extends through the substrate and the dielectric layer. | 09-26-2013 |
20130260556 | BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS - According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad. | 10-03-2013 |
20130267093 | Through Substrate Via Semiconductor Components And Methods of Formation Thereof - A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer. | 10-10-2013 |
20130295766 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 11-07-2013 |
20130309865 | METHOD OF MANUFACTURING SUBSTRATE FOR MOUNTING ELECTRONIC DEVICE - There is provided a method of manufacturing a substrate for mounting an electronic device. The method includes disposing a protective layer on a surface of the substrate except for an edge portion thereof . An oxide film is disposed on the entirety of the surface of the substrate except for where the protective layer is disposed The oxide film is grown. A through hole is formed in a thickness direction of the substrate by selectively etching the protective layer. The oxide film is removed. In the manufacturing method, defects in the substrate for mounting an electronic device may be reduced and manufacturing costs can be reduced. | 11-21-2013 |
20130316534 | FABRICATION METHOD FOR CIRCUIT SUBSTRATE HAVING POST-FED DIE SIDE POWER SUPPLY CONNECTIONS - A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate. | 11-28-2013 |
20130330924 | Gas Cluster Ion Beam Process for Opening Conformal Layer in a High Aspect Ratio Contact Via - A method for opening a conformal layer at the bottom of a contact via on a substrate is described. The method includes providing a substrate having a first layer with a via pattern formed therein and a second layer conformally deposited on the first layer and within the via pattern to establish a contact via pattern characterized by an initial mid-critical dimension (CD). The method further includes etching through the second layer at the bottom of the contact via pattern to extend the contact via pattern through the second layer and form a contact via while retaining at least part of the second layer on the top surface of the first layer, the corner at the entrance to the via pattern, and the sidewalls of the via pattern, wherein the etching is performed by irradiating the substrate with a gas cluster ion beam (GCIB) according to a GCIB etching process. | 12-12-2013 |
20130330925 | METHODS OF TREATING A DEVICE-SUBSTRATE AND SUPPORT-SUBSTRATES USED THEREIN - Disclosed are methods of treating a device-substrate, and support-substrates used therein. The methods may include providing the device-substrate having an integrated circuit, bonding a first top surface of the device-substrate to a support-substrate, and polishing a first bottom surface of the device-substrate. The support-substrates include a second top surface, a second bottom surface opposite to the second top surface, and a sidewall connecting the second top and bottom surfaces. Additionally, the support-substrates further include a grooved portion spaced apart from the sidewall and blocking a crack in the support-substrates occurring from the sidewall. | 12-12-2013 |
20130337647 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 12-19-2013 |
20130344695 | SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME - Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate | 12-26-2013 |
20140038411 | MANUFACTURING METHOD OF DEVICE - A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films. | 02-06-2014 |
20140045332 | Through Silicon Via Keep Out Zone Formation Method and System - Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs. | 02-13-2014 |
20140065821 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 03-06-2014 |
20140073133 | METHOD TO MITIGATE THROUGH-SILICON VIA-INDUCED SUBSTRATE NOISE - A semiconductor manufacture includes a first semiconductor including a substrate die having a first surface and having a second surface upon which integrated circuitry is disposed; a second semiconductor die; a through-silicon via (TSV) extending through the first semiconductor die and electrically connected to the second semiconductor die; and at least one ground plug including an electrically conductive material, positioned proximally to the TSV and extending into the substrate of the first semiconductor die from one of the first surface or the second surface. | 03-13-2014 |
20140073134 | 3-D INTEGRATION USING MULTI STAGE VIAS - A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias. | 03-13-2014 |
20140080303 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING NANOTUBES, AND SEMICONDUCTOR STRUCTURES, DEVICES, AND SYSTEMS FABRICATED USING SUCH METHODS - A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed. | 03-20-2014 |
20140099786 | Methods Of Forming Through Substrate Interconnects - A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material. | 04-10-2014 |
20140113448 | POSITIVE PHOTOSENSITIVE RESIN COMPOSITION FOR SPRAY COATING AND METHOD FOR PRODUCING THROUGH ELECTRODE USING THE SAME - A method for producing a through electrode includes providing a semiconductor wafer having an integrated circuit provided on a surface of the semiconductor wafer and a hole provided in the semiconductor wafer along a thickness direction of the semiconductor wafer. At least a portion of a back surface of an electrode of the integrated circuit is exposed through the hole. A positive photosensitive resin composition is sprayed to form a coating film so that the coating film covers an inner surface of the hole. The positive photosensitive resin composition has a viscosity of 0.5 to 200 cP and includes an alkali-soluble resin, a compound which generates an acid when exposed to light, and a solvent. At least a portion of the coating film is exposed and developed to form a coating film pattern. | 04-24-2014 |
20140127904 | ENHANCED CAPTURE PADS FOR THROUGH SEMICONDUCTOR VIAS - Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs. | 05-08-2014 |
20140148007 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate. | 05-29-2014 |
20140179103 | SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME - A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed. | 06-26-2014 |
20140187040 | 3D IC METHOD AND DEVICE - A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding. | 07-03-2014 |
20140199834 | HYBRID CONDUCTOR THROUGH-SILICON-VIA FOR POWER DISTRIBUTION AND SIGNAL TRANSMISSION - A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate. | 07-17-2014 |
20140235053 | Methods of Forming Through Silicon Via Openings - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 08-21-2014 |
20140242794 | Methods of Patterning Small Via Pitch Dimensions - Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask. | 08-28-2014 |
20140256130 | FRONT SIDE WAFER ID PROCESSING - A method for printing a wafer ID on a wafer, the method comprises identifying a wafer ID on a back side of the wafer. Subsequently, etching a plurality of recesses, consistent in size with chip features of the wafer, into the front side of the wafer, such that the plurality of recesses depicts the wafer ID. The method further comprises filling the recesses with a metal. | 09-11-2014 |
20140273443 | METHODS OF FORMING TRENCH/HOLE TYPE FEATURES IN A LAYER OF MATERIAL OF AN INTEGRATED CIRCUIT PRODUCT - One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material. | 09-18-2014 |
20140287584 | MICROELECTRONIC DEVICES WITH THROUGH-SILICON VIAS AND ASSOCIATED METHODS OF MANUFACTURING - Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material. | 09-25-2014 |
20140302674 | METHOD FOR STRAIN-RELIEVED THROUGH SUBSTRATE VIAS - A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion. | 10-09-2014 |
20140329386 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer. | 11-06-2014 |
20140357077 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES - Provided are methods for fabricating semiconductor devices having through electrodes. The method may comprise forming a polishing stop layer having a multi-layered structure on a substrate, forming a via hole partially penetrating the substrate, providing the substrate with a first cleaning solution to first clean the substrate, providing the substrate with a second cleaning solution to second clean the substrate, the second cleaning solution being different from the first cleaning solution, and forming a through electrode in the via hole. | 12-04-2014 |
20150011086 | NOVEL CONDUCTOR LAYOUT TECHNIQUE TO REDUCE STRESS-INDUCED VOID FORMATIONS - A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. One or multiple notches are designed in the layout on a selective portion of the mask for patterning conductor line. The existence of the notch or notches on the selective portion generates extra stress components within the conductor line than would exist without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device. | 01-08-2015 |
20150017803 | CUSTOMIZED ALLEVIATION OF STRESSES GENERATED BY THROUGH-SUBSTRATE VIA(S) - Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure. | 01-15-2015 |
20150024590 | REMOVING CONDUCTIVE MATERIAL TO FORM CONDUCTIVE FEATURES IN A SUBSTRATE - Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate. | 01-22-2015 |
20150024591 | On-Chip RF Shields with Backside Redistribution Lines - Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material. | 01-22-2015 |
20150056804 | BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS - According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad. | 02-26-2015 |
20150087147 | Methods of Forming Through Substrate Interconnects - A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material. | 03-26-2015 |
20150093896 | SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME - The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole. | 04-02-2015 |
20150099358 | METHOD FOR FORMING THROUGH WAFER VIAS IN SEMICONDUCTOR DEVICES - A method for forming a through wafer via hole in a semiconductor device, wherein the semiconductor device comprises a wafer having a SiC substrate with a front side and a backside, a GaN-based layer formed on the front side of the SiC substrate, and a mask structure formed on the backside of the SiC substrate defining an etching area. The etching area is first descummed A through substrate via hole is formed by etching the etching area through the SiC substrate. The mask structure is removed and the inner surface of the through substrate via hole is cleaned. The inner surface of the through substrate via hole is then descummed A through wafer via hole is formed by etching through the GaN layer in the through substrate via hole. And lastly the inner surface of the through wafer via hole is cleaned. | 04-09-2015 |
20150132949 | FABRICATION METHODS OF CHIP DEVICE PACKAGES - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. | 05-14-2015 |
20150132950 | SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURES INCLUDING THE SAME - A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer. | 05-14-2015 |
20150294910 | INTERCONNECTION STRUCTURE HAVING A VIA STRUCTURE AND FABRICATION THEREOF - A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad. | 10-15-2015 |
20150340264 | METHOD OF APPLICATION OF A CARRIER TO A DEVICE WAFER - A device wafer having a main surface including an edge region and a carrier having a further main surface including an annular surface region corresponding to the edge region of the device wafer are provided. An adhesive is applied in the edge region and/or in the annular surface region, but not on the remaining areas of the main surfaces. The device wafer is fastened to the carrier by the adhesive. The main surface and the further main surface are brought into contact with one another when the device wafer is fastened to the carrier, while the main surface and the further main surface are fastened to one another only in the edge region. The device wafer is removed from the carrier after further process steps, which may include the formation of through-wafer vias in the device wafer. | 11-26-2015 |
20150364372 | DOUBLE SELF-ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 12-17-2015 |
20160005645 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE VIA STRUCTURE - A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer. | 01-07-2016 |
20160020146 | METHOD FOR REDUCING CROSS CONTAMINATION IN INTEGRATED CIRCUIT MANUFACTURING - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices. | 01-21-2016 |
20160093530 | METHOD FOR FORMING THROUGH SUBSTRATE VIAS - A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an annulus in a first side of a silicon substrate, removing material from an opposite side to the level of the annulus, removing the silicon post and replacing it with a metal material to form a metal via extending through the thickness of the substrate. | 03-31-2016 |
20160093531 | METHOD FOR FORMING THROUGH SUBSTRATE VIAS WITH TETHERS - A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an substantially continuous annulus in a first side of a silicon substrate, removing material from an opposite side to the level of the substantially continuous annulus, removing the silicon post and replacing it with a metal material to form a metal via extending through the thickness of the substrate. The substantially continuous annulus may be interrupted by at least one tether which connects the silicon post to the silicon substrate. The tether may be formed of a thing isthmus of silicon, or some suitable insulating material. | 03-31-2016 |
20160126133 | METAL-ASSISTED CHEMICAL ETCHING OF A SEMICONDUCTIVE SUBSTRATE WITH HIGH ASPECT RATIO, HIGH GEOMETIC UNIFORMITY, AND CONTROLLED 3D PROFILES - An embodiment of a method for metal-assisted chemical etching of a semiconductive substrate comprises forming a patterned coating on a top surface of a substrate layer of a silicon wafer; applying a noble metal layer over the patterned coating such that a portion of the noble metal layer is in contact with the top surface of the substrate layer; and immersing the silicon wafer in a wet etching solution to form a trench under the portion of the noble metal layer that is contact with the top surface of the substrate layer. Further, the trench may be filled with copper material to form a through silicon via structure. Such embodiments provide etching techniques that enable etched formations that are deep (e.g., high-aspect-ratio) and uniform as opposed to shallow etchings (i.e., low-aspect-ratio) or non-uniform deep etchings. | 05-05-2016 |
20160133501 | LOW TEMPERATURE ADHESIVE RESINS FOR WAFER BONDING - A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer. | 05-12-2016 |
20160155666 | Providing A Chip Die With Electrically Conductive Elements | 06-02-2016 |
20160163595 | METHOD FOR MANUFACTURING THROUGH-HOLE SILICON VIA - A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon. | 06-09-2016 |
20160163596 | PROCESS AND MATERIAL FOR PREVENTING DELETERIOUS EXPANSION OF HIGH ASPECT RATIO COPPER FILLED THROUGH SILICON VIAS (TSVS) - Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW | 06-09-2016 |
20160163655 | INTEGRATED CIRCUIT COMPONENT SHIELDING - Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a plurality of vias disposed between the first and second conductive regions. The first and second conductive regions and the plurality of vias may surround an integrated circuit (IC) component and individual vias of the plurality of vias are spaced relative to one another to shield incoming or outgoing electromagnetic interference (EMI). Other embodiments may be described and/or claimed. | 06-09-2016 |
20160172242 | SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT | 06-16-2016 |
20160204015 | LOW TEMPERATURE ADHESIVE RESINS FOR WAFER BONDING | 07-14-2016 |
20170233883 | Leveler Compositions for Use in Copper Deposition in Manufacture of Microelectronics | 08-17-2017 |
20170236751 | METHODS OF FORMING WIRING STRUCTURES FOR SEMICONDUCTOR DEVICES | 08-17-2017 |