| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438558000 | From solid dopant source in contact with semiconductor region | 51 |
| 20090017605 | METHODS FOR DOPING NANOSTRUCTURED MATERIALS AND NANOSTRUCTURED THIN FILMS - A method for introducing one or more impurities into nano-structured materials. The method includes providing a nanostructured material having a feature size of about 100 nm and less. The method includes subjecting a surface region of the nanostructured material to one or more impurities to form a first region having a first impurity concentration within a vicinity of the surface region. In a specific embodiment, the method includes applying a driving force to one or more portions of at least the nanostructured material to cause the first region to form a second region having a second impurity concentration. | 01-15-2009 |
| 20090017606 | Method for Producing a Semiconductor Component Having Regions Which are Doped to Different Extents - A method for producing a semiconductor component, in particular a solar cell, having regions which are doped to different extents. A layer is formed which inhibits the diffusion of a dopant and can be penetrated by a dopant, on at least one part of the surface of a semiconductor component material. The diffusion-inhibiting layer is at least partially removed in at least one high-doping region. A dopant source is formed on the diffusion-inhibiting layer and in the at least one high-doping region. Then the dopant is diffused from the dopant source into the semiconductor component material. The semiconductor component is suitable for use in integrated circuits, electronic circuits, solar cell modules, and to produce solar cells having a selective emitter structure. | 01-15-2009 |
| 20090209094 | Semiconductor Element Manufacturing Method - [PROBLEMS] To provide a semiconductor element manufacturing method by which a semiconductor element having high accuracy and high function can be manufactured by controlling diffusion depth and diffusion concentration in a pn junction region with high accuracy. | 08-20-2009 |
| 20090269913 | JUNCTION FORMATION ON WAFER SUBSTRATES USING GROUP IV NANOPARTICLES - A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region. | 10-29-2009 |
| 20100003812 | Solar Cell Fabrication Using Extrusion Mask - Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer, and a central opening that exposes a central active area of the wafer. The extrusion head is then moved relative to the wafer, and the extrusion material is continuously extruded through outlet orifices of the extrusion head to form elongated extruded structures on the active area of the wafer. The mask prevents deposition of the extrusion material along the peripheral edges of the wafer, and facilitates the formation of unbroken extrusion structures. The mask may be provided with a non-rectangular opening to facilitate the formation of non-rectangular (e.g., circular) two-dimensional extrusion patterns. | 01-07-2010 |
| 20100022077 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer. | 01-28-2010 |
| 20100035422 | METHODS FOR FORMING DOPED REGIONS IN A SEMICONDUCTOR MATERIAL - Methods for forming doped regions in a semiconductor material that minimize or eliminate vapor diffusion of a dopant element and/or dopant from a deposited dopant and/or into a semiconductor material and methods for fabricating semiconductor devices that minimize or eliminate vapor diffusion of a dopant element and/or dopant from a deposited dopant and/or into a semiconductor material are provided. In one exemplary embodiment, a method for forming doped regions in a semiconductor material comprises depositing a conductivity-determining type dopant comprising a dopant element overlying a first portion of the semiconductor material. A diffusion barrier material is applied such that it overlies a second portion of the semiconductor material. The dopant element of the conductivity-determining type dopant is diffused into the first portion of the semiconductor material. | 02-11-2010 |
| 20100068873 | Depletion-Free MOS using Atomic-Layer Doping - A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type. | 03-18-2010 |
| 20100221903 | METHODS OF FORMING A LOW RESISTANCE SILICON-METAL CONTACT - A method of forming an ohmic contact on a substrate is described. The method includes depositing a set of silicon particles on the substrate surface. The method also includes heating the substrate in a baking ambient to a baking temperature and for a baking time period in order to create a densified film ink pattern. The method further includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl | 09-02-2010 |
| 20110129990 | METHOD FOR DOPING NON-PLANAR TRANSISTORS - Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching. | 06-02-2011 |
| 20110159673 | NOVEL METHOD FOR CONFORMAL PLASMA IMMERSED ION IMPLANTATION ASSISTED BY ATOMIC LAYER DEPOSITION - Embodiments of the invention provide a novel apparatus and methods for forming a conformal doped layer on the surface of a substrate. A substrate is provided to a process chamber, and a layer of dopant source material is deposited by plasma deposition, atomic layer deposition, or plasma-assisted atomic layer deposition. The substrate is then subjected to thermal processing to activate and diffuse dopants into the substrate surface. | 06-30-2011 |
| 20110183504 | METHODS OF FORMING A DUAL-DOPED EMITTER ON A SUBSTRATE WITH AN INLINE DIFFUSION APPARATUS - A method of forming a multi-doped junction is disclosed. The method includes providing a substrate doped with boron atoms, the substrate comprising a front substrate surface. The method also includes depositing an ink on the front substrate surface in an ink pattern, the ink comprising a set of nanoparticles and a set of solvents; and heating the substrate in a baking ambient at a baking temperature and for a baking time period wherein a densified ink layer is formed. The method further includes exposing the substrate to a phosphorous dopant source at a drive-in temperature and for a drive-in time period. | 07-28-2011 |
| 20110237057 | SYSTEMS AND METHODS FOR CO-DOPING WIDE BAND GAP MATERIALS - Various embodiments of the present disclosure provide a method of simultaneously co-doping a wide band gap material with p-type and n-type impurities to create a p-n junction within the resulting wide band gap composite material. The method includes disposing a sample comprising a dopant including both p-type and n-type impurities between a pair of wide band gap material films and disposing the sample between a pair of opposing electrodes; and subjecting the sample to a preselected vacuum; and heating the sample to a preselected temperature; and applying a preselected voltage across the sample; and subjecting the sample to at least one laser beam having a preselected intensity and a preselected wavelength, such that the p-type and n-type impurities of the dopant substantially simultaneously diffuse into the wide band gap material films resulting in a wide band gap compound material comprising a p-n junction. | 09-29-2011 |
| 20110312168 | FORMATION OF SHALLOW JUNCTIONS BY DIFFUSION FROM A DIELECTRIC DOPED BY CLUSTER OR MOLECULAR ION BEAMS - A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10 | 12-22-2011 |
| 20120028454 | PLASMA ACTIVATED CONFORMAL DIELECTRIC FILM DEPOSITION - Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction. | 02-02-2012 |
| 20120070971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING - There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions. | 03-22-2012 |
| 20120149182 | Dopant Applicator System and Method of Applying Vaporized Doping Compositions to PV Solar Wafers - Silicon wafer processing system, apparatus and method of doping silicon wafers with hot concentrated acid dopant compositions for forming p-n junction and back contact layers during processing into PV solar cells. Highly concentrated acid dopant is atomized with pressurized gas and heated in the range of 80-200° C., then introduced into a concentrated acid vapor processing chamber to apply vapor over 1.5-6 min to wafers moving horizontally on a multi-lane conveyor system through the processing chamber. The wafers are dried and forwarded to a diffusion furnace. An optional UV pre-treatment assembly pre-conditions the wafers with UV radiation prior to dopant application, and doped wafers may be post-treated in a UV treatment module before being fired. The wafers may be cooled in the processing chamber. Post-firing, the wafers exhibit excellent sheet resistance in the 60-95 Ω/sq range, and are highly uniform across the wafers and wafer-to-wafer. | 06-14-2012 |
| 20130040447 | CONFORMAL DOPING VIA PLASMA ACTIVATED ATOMIC LAYER DEPOSITION AND CONFORMAL FILM DEPOSITION - Disclosed herein are methods of doping a patterned substrate in a reaction chamber. The methods may include forming a first conformal film layer which has a dopant source including a dopant, and driving some of the dopant into the substrate to form a conformal doping profile. In some embodiments, forming the first film layer may include introducing a dopant precursor into the reaction chamber, adsorbing the dopant precursor under conditions whereby it forms an adsorption-limited layer, and reacting the adsorbed dopant precursor to form the dopant source. Also disclosed herein are apparatuses for doping a substrate which may include a reaction chamber, a gas inlet, and a controller having machine readable code including instructions for operating the gas inlet to introduce dopant precursor into the reaction chamber so that it is adsorbed, and instructions for reacting the adsorbed dopant precursor to form a film layer containing a dopant source. | 02-14-2013 |
| 20130059433 | METHODS AND COMPOSITIONS FOR DOPING SILICON SUBSTRATES WITH MOLECULAR MONOLAYERS - Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred. | 03-07-2013 |
| 20140094025 | METHOD OF PROCESSING A SEMICONDUCTOR ASSEMBLY - A method for processing a semiconductor assembly is presented. The method includes: (a) contacting at least a portion of a semiconductor assembly with a chalcogen source, wherein the semiconductor assembly comprises a semiconductor layer comprising a semiconductor material disposed on a support; (b) introducing a chalcogen from the chalcogen source into at least a portion of the semiconductor material; and (c) disposing a window layer on the semiconductor layer after the step (b). | 04-03-2014 |
| 20150017794 | METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS - The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. | 01-15-2015 |
| 20150037967 | CONTROLLING IMPURITIES IN A WAFER FOR AN ELECTRONIC CIRCUIT - Methods of processing a silicon wafer for an electronic circuit, substrates for an electronic circuit, and device manufacturing methods are disclosed. According to an embodiment the method of processing a silicon wafer comprises impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1. | 02-05-2015 |
| 20150118833 | METHOD OF MAKING SOURCE/DRAIN CONTACTS BY SPUTTERING A DOPED TARGET - A method of depositing a contact layer material includes sputtering a target including a metal and a dopant. The contact layer material is conductive and may be used in a transistor device to connect a conductive region, such as a source region or a drain region of metal-oxide semiconductor field effect transistor, to a contact plug. The contact plug is used to connect the source/drain region formed in a semiconducting substrate to metal wiring layers formed above the gate level of a semiconductor device. The resulting contact layer may be a metal silicide including the dopant. In some embodiments, the sputtered metal may be nickel and the dopant may be phosphorous and the resulting contact layer a nickel silicide doped with phosphorous. Embodiments described, in general, can provide reduced contact resistance and thus improved performance in semiconductor devices. | 04-30-2015 |
| 20150132931 | HIGH-THROUGHPUT THERMAL PROCESSING METHODS FOR PRODUCING HIGH-EFFICIENCY CRYSTALLINE SILICON SOLAR CELLS - A method for thermal processing of a silicon substrate wherein first a silicon substrate is heated to an idle load temperature in the range of approximately 700° to 900° C. The silicon substrate is then heated to a temperature in the range of approximately 975° to 1200° C. in less than approximately 20 minutes. After thermal processing, the silicon substrate is cooled to an idle unload temperature in the range of approximately 700° to 900° C. in less than approximately 20 minutes. | 05-14-2015 |
| 20150147875 | METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS - The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. | 05-28-2015 |
| 20160099149 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor substrate. An impurity diffusion ingredient can be diffused well and uniformly from a coating film into a semiconductor substrate by forming a coating film having a thickness of not more than 30 nm on a surface of a semiconductor substrate with a diffusion agent composition containing an impurity diffusion ingredient and a silicon compound that can be hydrolyzed to produce a silanol group. | 04-07-2016 |
| 438559000 | Using capping layer over dopant source to prevent out-diffusion of dopant | 11 |
| 20110223751 | DOPING OF SEMICONDUCTOR SUBSTRATE THROUGH CARBONLESS PHOSPHOROUS-CONTAINING LAYER - A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant. | 09-15-2011 |
| 20120009770 | Method of Forming Conductive Lines of Semiconductor Memory Device - A method of forming the conductive lines of a semiconductor memory device comprises forming a first polysilicon layer over an underlying layer, forming first polysilicon patterns by patterning the first polysilicon layer, filling the space between the first polysilicon patterns with an insulating layer, etching a top portion of the first polysilicon patterns to form recess regions, forming spacers on the sidewalls of the recess regions, filling the recess regions with a second polysilicon layer to form second polysilicon patterns, and performing a metal silicidation process to convert the second polysilicon patterns to metal silicide patterns. | 01-12-2012 |
| 20120252197 | METHOD FOR FORMING ULTRA-SHALLOW BORON DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment. | 10-04-2012 |
| 20120302050 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein is a method of manufacturing a semiconductor device. The method comprises forming a first silicon film on a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, and forming a first diffusion barrier film on the third silicon film. The method further comprises performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively. | 11-29-2012 |
| 20130295754 | DOPING OF SEMICONDUCTOR SUBSTRATE THROUGH CARBONLESS PHOSPHOROUS-CONTAINING LAYER - A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant. | 11-07-2013 |
| 20140004689 | Methods Of Doping Substrates With ALD | 01-02-2014 |
| 20140179091 | METHOD FOR FORMING ULTRA-SHALLOW DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming ultra-shallow dopant regions in a substrate is provided. One embodiment includes depositing a first dopant layer containing a first dopant in direct contact with the substrate, patterning the first dopant layer, depositing a second dopant layer containing a second dopant in direct contact with the substrate adjacent the patterned first dopant layer, the first and second dopant layers containing an oxide, a nitride, or an oxynitride, where the first and second dopant layers contain an n-type dopant or a p-type dopant with the proviso that the first or second dopant layer do not contain the same dopant, and diffusing the first dopant from the first dopant layer into the substrate to form a first ultra-shallow dopant region in the substrate, and diffusing the second dopant from the second dopant layer into the substrate to form a second ultra-shallow dopant region in the substrate. | 06-26-2014 |
| 20150111372 | PHOSPHORUS AND ARSENIC DOPING OF SEMICONDUCTOR MATERIALS - Provided are methods for preparing a doped silicon material. The methods include contacting a surface of a silicon material with a dopant solution comprising a dopant-containing compound selected from a phosphorus-containing compound and an arsenic-containing compound, to form a layer of dopant material on the surface; and diffusing the dopant into the silicon material, thereby forming the doped silicon material, wherein the doped silicon material has a sheet resistance (R | 04-23-2015 |
| 20150118834 | SULFUR AND SELENIUM PASSIVATION OF SEMICONDUCTORS - The present invention includes methods directed to improved processes for producing a monolayer of sulfur or selenium on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element. | 04-30-2015 |
| 20150380249 | METHODS FOR FORMING A MOLECULAR DOPANT MONOLAYER ON A SUBSTRATE - Methods for forming a conformal dopant monolayer on a substrate are provided. In one embodiment, a method for forming a semi-conductor device on a substrate includes forming a charged layer on a silicon containing surface disposed on a substrate, wherein the charged layer has a first charge, and forming a dopant monolayer on the charged layer, wherein dopants formed in the dopant monolayer include at least one of a group III or group V atoms. | 12-31-2015 |
| 20160079064 | Methods Of Doping Substrates With ALD - Provided are methods of doping substrates and making doped semiconductor features. An exemplary method includes providing a substrate having at least one feature having an aspect ratio; depositing a layer of dopants onto the substrate, the layer of dopants having a shape conforming to the at least one feature. A dielectric layer is deposited onto the layer of dopants, the dielectric layer having a shape conforming to the layer of dopants. The dielectric layer is annealed to diffuse the dopants into the substrate. | 03-17-2016 |
| 438560000 | Plural diffusion stages | 1 |
| 20150364637 | NA DOSING CONTROL METHOD - A method includes placing at least two substrates on a substrate carrier at a distance from one another, placing the substrate carrier in a reaction chamber, depositing a precursor on the at least two substrates, and performing a first annealing process on the at least two substrates. The at least two substrates include a first content of a first material. The distance between the at least two substrates is based on the first content of the first material and at least one processing parameter. The disclosed method advantageously provides for improved Na-dosing control. | 12-17-2015 |
| 438561000 | Dopant source within trench or groove | 5 |
| 20110237058 | Semiconductor Devices Including Doped Metal Silicide Patterns and Related Methods of Forming Such Devices - Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate. | 09-29-2011 |
| 20120276726 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer. | 11-01-2012 |
| 20120289037 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer. | 11-15-2012 |
| 20140073122 | METHOD FOR FORMING ULTRA-SHALLOW BORON DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment. | 03-13-2014 |
| 20150072510 | METHOD FOR FORMING ULTRA-SHALLOW BORON DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment. | 03-12-2015 |
| 438562000 | Organic source | 2 |
| 20090239363 | METHODS FOR FORMING DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES USING NON-CONTACT PRINTING PROCESSES AND DOPANT-COMPRISING INKS FOR FORMING SUCH DOPED REGIONS USING NON-CONTACT PRINTING PROCESSES - Methods for forming doped regions in semiconductor substrates using non-contact printing processes and dopant-comprising inks for forming such doped regions using non-contact printing processes are provided. In an exemplary embodiment, a method for forming doped regions in a semiconductor substrate is provided. The method comprises providing an ink comprising a conductivity-determining type dopant, applying the ink to the semiconductor substrate using a non-contact printing process, and subjecting the semiconductor substrate to a thermal treatment such that the conductivity-determining type dopant diffuses into the semiconductor substrate. | 09-24-2009 |
| 20150056793 | DOPING OF A SUBSTRATE VIA A DOPANT CONTAINING POLYMER FILM - Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a dopant-containing polymer and a non-polar solvent on a substrate; and annealing the substrate at a temperature of 750 to 1300° C. for 1 second to 24 hours to diffuse the dopant into the substrate; wherein the dopant-containing polymer is a polymer having a covalently bound dopant atom; wherein the dopant-containing polymer is free of nitrogen and silicon; and wherein the method is free of a step of forming an oxide capping layer over the coating prior to the annealing step. | 02-26-2015 |
| 438563000 | Glassy source or doped oxide | 6 |
| 20080248639 | Method for forming electrode for group III nitride based compound semiconductor and method for manufacturing p-type group III nitride based compound semiconductor - An undoped GaN layer having a thickness of 3 μm is formed by MOVPE on a sapphire substrate with a buffer layer composed of aluminum nitride (AlN) therebetween. A GaN layer doped with 5×10 | 10-09-2008 |
| 20140162445 | SILICON SUBSTRATES WITH DOPED SURFACE CONTACTS FORMED FROM DOPED SILICON BASED INKS AND CORRESPONDING PROCESSES - The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells. | 06-12-2014 |
| 20150099352 | COMPOSITION FOR FORMING n-TYPE DIFFUSION LAYER, METHOD OF PRODUCING n-TYPE DIFFUSION LAYER, AND METHOD OF PRODUCING PHOTOVOLTAIC CELL ELEMENT - A composition for forming an n-type diffusion layer includes a glass powder containing P | 04-09-2015 |
| 20160005607 | METHOD FOR SELECTIVELY DEPOSITING A LAYER ON A THREE DIMENSIONAL STRUCTURE - A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion. | 01-07-2016 |
| 20160099151 | Etching Process - A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping oxide layer, the patterning layer leaving exposed regions of the doping oxide layer; performing a sputtering process to the substrate; and after the sputtering process, performing a wet etching process to the semiconductor substrate to remove the doping oxide layer from the exposed regions. | 04-07-2016 |
| 20160379827 | METHOD FOR SELECTIVELY DEPOSITING A LAYER ON A THREE DIMENSIONAL STRUCTURE - A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion. | 12-29-2016 |
