| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438509000 | Heat treatment | 26 |
| 20080280427 | Low etch pit density (EPD) semi-insulating GaAs wafers - A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer. | 11-13-2008 |
| 20090053878 | METHOD FOR FABRICATION OF SEMICONDUCTOR THIN FILMS USING FLASH LAMP PROCESSING - A method for creating a Group IV semiconductor densified thin film is disclosed. The method includes applying a colloidal dispersion to a substrate, wherein the colloidal dispersion includes a plurality of Group IV semiconductor nanoparticles and an organic solvent. The method also includes removing the organic solvent by applying a first temperature for a first time period to form a Group IV semiconductor non-densified thin film; and heating the Group IV semiconductor non-densified thin film to a second temperature for a second time period, wherein the second temperature is a pre-heating target temperature. The method further includes heating the Group IV semiconductor non-densified thin film to a third temperature for a third time period with a flash lamp apparatus, wherein the third temperature is equal to or greater than a sintering temperature, wherein a Group IV semiconductor densified thin film is created. | 02-26-2009 |
| 20090104760 | VERTICAL CVD APPPARATUS FOR FORMING SILICON-GERMANIUM FILM - A vertical CVD apparatus is arranged to process a plurality of target substrates all together to form a silicon germanium film. The apparatus includes a reaction container having a process field configured to accommodate the target substrates, and a common supply system configured to supply a mixture gas into the process field. The mixture gas includes a first process gas of a silane family and a second process gas of a germane family. The common supply system includes a plurality of supply ports disposed at different heights. | 04-23-2009 |
| 20090117721 | Vapor phase growth apparatus - A method of cooling a complex electronic system includes preventing system air from passing through a front side and a rear side of a server system main board, organizing a plurality of electronic segments of the server system main board, providing cool air horizontally to the server system main board through a cool air intake provided at a position located underneath the front side and at a bottom side of the server system main board, using the cool air intake to provide the cool air to a plurality of cooling segments that redirect the cool air vertically at a 90° angle, and using a hot air exhaust after the hot air reaches the top side of the server system main board to redirect the hot air horizontally at a 90° angle and exhaust the hot air. | 05-07-2009 |
| 20090181525 | Wafer structure and epitaxial growth method for growing the same - A wafer structure and epitaxial growth method for growing the same. The method may include forming a mask layer having nano-sized areas on a wafer, forming a porous layer having nano-sized pores on a surface of the wafer by etching the mask layer and a surface of the wafer, and forming an epitaxial material layer on the porous layer using an epitaxial growth process. | 07-16-2009 |
| 20090239362 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An apparatus for manufacturing a semiconductor device, including in a reaction chamber: a rotor provided with a holding member holding a wafer thereon and a heater heating the wafer therein; a rotation drive mechanism; a gas supply mechanism; a gas exhaust mechanism; and a rectifying plate for rectifying the supplied process gas to supply the rectified gas, and including: an annular rectifying fin mounted on a lower portion of the plate, having a larger lower end inside diameter than an upper end inside diameter thereof and downward rectifying gas exhausted in an outer circumferential direction from above the wafer; and a distance control mechanism controlling a vertical distance between the plate and the wafer and a vertical distance between the fin and the rotor top face to be predetermined distances, respectively, thereby providing higher film formation efficiency. | 09-24-2009 |
| 20100173483 | GaN SINGLE-CRYSTAL SUBSTRATE, NITRIDE TYPE SEMICONDUCTOR EPITAXIAL SUBSTRATE, NITRIDE TYPE SEMICONDUCTOR DEVICE, AND METHODS OF MAKING THE SAME - The GaN single-crystal substrate | 07-08-2010 |
| 20100240199 | Scalable Light-Induced Metallic to Semiconducting Conversion of Carbon Nanotubes and Applications to Field-Effect Transistor Devices - Among others, techniques are described for forming nanotubes. In one aspect, a method includes forming a base layer of a transition metal on a substrate. The method also includes heating the substrate with the base layer in a mixture of gases to grow nanotubes on the base layer. | 09-23-2010 |
| 20110034011 | FORMATION OF GRAPHENE WAFERS ON SILICON SUBSTRATES - Processes for forming full graphene wafers on silicon or silicon-on-insulator substrates. The processes comprise formation of a metal carbide layer on the substrate and annealing of the metal carbide layer under high vacuum. For volatile metals, this annealing step results in volatilization of the metal species of the metal carbide layer and reformation of the carbon atoms into the desired graphene wafer. Alternatively, for non-volatile metals, the annealing step results in migration of the metal in the metal carbide layer to the top surface of the layer, thereby forming a metal rich top layer. The desired graphene layer is formed by the carbon atoms left at the interface with the metal rich top layer. The thickness of the graphene layer is controlled by the thickness of the metal carbide layer and by solid phase reactions. | 02-10-2011 |
| 20110177683 | FORMING II-VI CORE-SHELL SEMICONDUCTOR NANOWIRES - A method of making II-VI core-shell semiconductor nanowires includes providing a support; depositing a layer including metal alloy nanoparticles on the support; and heating the support and growing II-VI core semiconductor nanowires where the metal alloy nanoparticles act as catalysts and selectively cause localized growth of the core nanowires. The method further includes modifying the growth conditions and shelling the core nanowires to form II-VI core-shell semiconductor nanowires. | 07-21-2011 |
| 20110294283 | MOCVD REACTOR HAVING CYLINDRICAL GAS INLET ELEMENT - The invention relates to a device for depositing semiconductor layers, comprising a process chamber ( | 12-01-2011 |
| 20120108040 | VAPORIZING POLYMER SPRAY DEPOSITION SYSTEM - A vaporizing spray deposition device for forming a thin film includes a processing chamber, a fluid line, and a spray head coupled to the fluid line proximate the processing chamber. The fluid line is configured to transfer a polymer fluid and solvent mixture to the spray head. The spray head is configured to receive the polymer fluid and solvent mixture and to atomize the polymer fluid and solvent mixture to emit it in a substantially vaporized form to be deposited on a surface and thereby forming a thin film of the polymer on the surface after evaporation of the solvent. In an embodiment, the vaporizing spray deposition device may include a heating device to perform a hard bake process on the polymer. In an embodiment, the vaporizing spray deposition device may be configured to provide a post deposition solvent spray trim process to the thin film polymer. | 05-03-2012 |
| 20120108041 | Patterning of Nanostructures - A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature. | 05-03-2012 |
| 20120208358 | METHOD FOR PRODUCING A MULTILAYER FILM INCLUDING AT LEAST ONE ULTRATHIN LAYER OF CRYSTALLINE SILICON, AND DEVICES OBTAINED BY MEANS OF SAID METHOD - Method of fabricating a multilayer film having at least one ultrathin layer of crystalline silicon, the film being fabricated from a substrate having a crystalline structure and including a previously-cleaned surface. The method includes the steps of: a) exposing the cleaned surface to a radiofrequency plasma generated in a gaseous mixture of SiF4, hydrogen, and argon, so as to form an ultrathin layer of crystalline silicon having an interface sublayer in contact with the substrate and containing microcavities; b) depositing at least one layer of material on the ultrathin layer of crystalline silicon so as form a multilayer film, the multilayer film including at least one mechanically strong layer; and c) annealing the substrate covered in the multilayer film at a temperature higher than 400° C., thereby enabling the multilayer film to be separated from the substrate. | 08-16-2012 |
| 20130005125 | NANOPARTICLE POSITIONING TECHNIQUE - Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more ligands, and these nanoparticles are disposed within respective recesses of the substrate. In some embodiments, the substrate is processed to form nanostructures, such as nanotubes or nanowires, within the recesses. Devices and systems having such nanostructures are also disclosed. | 01-03-2013 |
| 20130115760 | METHOD OF FORMING A THIN LAYER STRUCTURE - A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets. | 05-09-2013 |
| 20130210221 | SELECTIVE EPITAXIAL GERMANIUM GROWTH ON SILICON-TRENCH FILL AND IN SITU DOPING - Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed. | 08-15-2013 |
| 20130309850 | METHOD OF FABRICATING HIGH EFFICIENCY CIGS SOLAR CELLS - A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25−0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency. | 11-21-2013 |
| 20140295653 | Manufacturing Apparatus And Manufacturing Method For Quantum Dot Material - A manufacturing apparatus and a manufacturing method for a quantum dot material. The manufacturing apparatus adds an optical device capable of generating an interference pattern in an existing epitaxial apparatus, so that a substrate applies an interference pattern on an epitaxial layer while performing epitaxial growth. By means of the interference pattern, a regularly distributed temperature field is formed on the epitaxial layer, so that on the epitaxial layer, an atom aggregation phenomenon is formed at dot positions with higher temperature, but no atoms are aggregated on areas having relatively lower temperature. Therefore, according to the temperature distribution on the surface of the epitaxial layer, positions where quantum dots generate can be controlled manually without introducing defects, thereby achieving a defect-free and long-range ordered quantum dot manufacturing. | 10-02-2014 |
| 20150072509 | PECVD MICROCRYSTALLINE SILICON GERMANIUM (SIGE) - Embodiments of the present invention generally relate to methods for forming a SiGe layer. In one embodiment, a seed SiGe layer is first formed using plasma enhanced chemical vapor deposition (PECVD), and a bulk SiGe layer is formed directly on the PECVD seed layer also using PECVD. The processing temperature for both seed and bulk SiGe layers is less than 450 degrees Celsius. | 03-12-2015 |
| 20150132928 | Patterning of Nanostructures - A technique for forming nanostructures including introducing a plurality of molecular-size scale and/or nanoscale building blocks to a region near a substrate and simultaneously scanning a pattern on the substrate with an energy beam, wherein the energy beam causes a change in at least one physical property of at least a portion of the building blocks, such that a probability of the portion of the building blocks adhering to the pattern scanned by the energy beam is increased, and wherein the building blocks adhere to the pattern to form the structure. The energy beam and at least a portion of the building blocks may interact by electrostatic interaction to form the structure. | 05-14-2015 |
| 20160013056 | HEAT TREATMENT APPARATUS AND HEAT TREATMENT METHOD | 01-14-2016 |
| 20160086800 | TUNNELING FIELD EFFECT TRANSISTORS AND TRANSISTOR CIRCUITRY EMPLOYING SAME - A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature molecular beam epitaxy at a growth temperature at or below 500° C. | 03-24-2016 |
| 20160133462 | SYSTEM FOR MANUFACTURING GRAPHENE ON A SUBSTRATE - A method and apparatus for manufacturing a lattice structure of a material on a substrate, wherein the process may be performed at atmospheric pressure, may not require a metallic substrate, may be capable of continuously generating the lattice structure as long as desired, may be as thin as a single layer of the lattice material, and may create the lattice structure with any material that is capable of being vaporized to create a stream of ionized particles and then condensed to form the lattice structure. | 05-12-2016 |
| 20160141175 | METHOD FOR REMOVING NATIVE OXIDE AND RESIDUE FROM A III-V GROUP CONTAINING SURFACE - Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius. | 05-19-2016 |
| 20160155629 | FORMATION OF HETEROEPITAXIAL LAYERS WITH RAPID THERMAL PROCESSING TO REMOVE LATTICE DISLOCATIONS | 06-02-2016 |
