| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438492000 | Fluid growth step with preceding and subsequent diverse operation | 52 |
| 20080220594 | Fabrication method of a mixed substrate and use of the substrate for producing circuits - The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking. | 09-11-2008 |
| 20080233720 | Method of Making a Solar Grade Silicon Wafer - A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing a solar grade wafer mold defining an interior for receiving the slurry; introducing the slurry into the solar grade wafer mold; precipitating the silicon powder from the slurry to form a preform of the solar grade silicon wafer; and crystallizing the preform to make the solar grade silicon wafer. | 09-25-2008 |
| 20080280426 | Gallium nitride-on-silicon interface - A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al | 11-13-2008 |
| 20080305619 | METHOD OF FORMING GROUP IV SEMICONDUCTOR JUNCTIONS USING LASER PROCESSING - A method forming a Group IV semiconductor junction on a substrate is disclosed. The method includes depositing a first set Group IV semiconductor nanoparticles on the substrate. The method also includes applying a first laser at a first laser wavelength, a first fluence, a first pulse duration, a first number of repetitions, and a first repetition rate to the first set Group IV semiconductor nanoparticles to form a first densified film with a first thickness, wherein the first laser wavelength and the first fluence are selected to limit a first depth profile of the first laser to the first thickness. The method further includes depositing a second set Group IV semiconductor nanoparticles on the first densified film. The method also includes applying a second laser at a second laser wavelength, a second fluence, a second pulse duration, a second number of repetitions, and a second repetition rate to the second set Group IV semiconductor nanoparticles to form a second densified film with a second thickness, wherein the second laser wavelength and the second fluence are selected to limit a second depth profile of the second laser to the second thickness. | 12-11-2008 |
| 20090029534 | Liquid phase deposition of contacts in programmable resistance and switching devices - A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer and the bottom composite electrode, and a top electrode layer deposited over the active material layer. The device uses a chemical or electrochemical liquid phase deposition process to selectively and conformally fill the insulative layer opening with the conductive bottom composite electrode layer. Conformally filling the conductive material within the opening reduces structural irregularities within the opening thereby increasing material density and resistivity within the device and thereby improving device performance and reducing programming current. | 01-29-2009 |
| 20090075461 | METHOD OF PROCESSING SEMICONDUCTOR WAFER - Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved. | 03-19-2009 |
| 20090117718 | METHODS FOR INFUSING ONE OR MORE MATERIALS INTO NANO-VOIDS IF NANOPOROUS OR NANOSTRUCTURED MATERIALS - A method of forming composite nanostructures using one or more nanomaterials. The method provides a nanostructure material having a surface region and one or more nano void regions within a first thickness in the surface region. The method subjects the surface region of the nanostructure material with a fluid. An external energy is applied to the fluid and/or the nanostructure material to drive in a portion of the fluid into one or more of the void regions and cause the one or more nano void regions to be substantially filled with the fluid and free from air gaps. | 05-07-2009 |
| 20090163000 | METHOD FOR FABRICATING VERTICAL CHANNEL TRANSISTOR IN A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar. | 06-25-2009 |
| 20100003811 | METHOD FOR MANUFACTURING EPITAXIAL WAFER - A method for manufacturing an epitaxial wafer is provided, which can alleviate distortions on a back surface of the epitaxial wafer. The method for manufacturing an epitaxial wafer using a susceptor for a vapor phase growth system having a concave shaped wafer placement portion on an upper face thereof, on which a semiconductor wafer is placed, includes: an oxide film forming step in which an oxide film Ox is formed on a back surface of the semiconductor wafer; a wafer placing step in which, after the oxide film forming step, the semiconductor wafer is placed on a wafer placement portion so that the back surface of the semiconductor wafer faces downward; and an epitaxial growth step in which, after the wafer placing step, an epitaxial layer is grown on a main surface of the semiconductor wafer. | 01-07-2010 |
| 20100105197 | WIDE-BANDGAP SEMICONDUCTOR DEVICES | 04-29-2010 |
| 20100120236 | FABRICATION OF ULTRA LONG NECKLACE OF NANOPARTICLES - The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. A variety of combinations of nanoparticles, such as Au and CdS nanoparticles, may be used to form a necklace. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V. The present invention also provides methods for constructing such a device. | 05-13-2010 |
| 20100216298 | Method for growing Ge expitaxial layer on patterned structure with cyclic annealing - A Ge epitaxial layer is grown on a silicon substrate with a patterned structure. Through a cyclic annealing, dislocation defects are confined. The present invention provides a method for manufacturing a high-quality Ge epitaxial layer with a low cost and a simple procedure. The Ge epitaxial layer obtained can be applied to high mobility Ge devices or any lattice-mismatched epitaxy on a photonics device. | 08-26-2010 |
| 20100221901 | METHOD FOR PREPARING CADMIUM SULFIDE FILM - A method for preparing a cadmium sulfide film comprises: providing a slurry; coating a first substrate with the slurry; heating the first substrate to produce a vapor; and depositing the vapor on a second substrate to form a cadmium sulfide film. The slurry comprises a dispersant, cadmium particles and sulfur particles. | 09-02-2010 |
| 20100323505 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a resist on a subject layer containing silicon. The method can etch the subject layer using the resist as a mask and with a gas containing a halogen element, which is introduced into a processing chamber. After the etching of the subject layer, the method can slim a planner size of the resist with oxygen gas and a gas containing a halogen element, which are introduced into the same processing chamber. | 12-23-2010 |
| 20110021009 | LOW CLAMP VOLTAGE ESD METHOD - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode. | 01-27-2011 |
| 20110143525 | NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion. | 06-16-2011 |
| 20110201184 | OXYGEN DOPING METHOD TO GALLIUM NITRIDE SINGLE CRYSTAL SUBSTRATE - Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained. | 08-18-2011 |
| 20110263108 | Method of fabricating semiconductor quantum dots - The invention relates to a method of fabricating at least one semiconductor quantum dot at a predefined position, comprising the steps of: patterning a semiconductor base material using nanoimprint lithography and an etching step, to form at least one nano-hole at the predefined position in the semiconductor base material; and growing the at least one semiconductor quantum dot in or on top of the at least one nano-hole by metalorganic chemical vapor deposition. | 10-27-2011 |
| 20120100702 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well. | 04-26-2012 |
| 20120108039 | ETCHANT TREATMENT PROCESSES FOR SUBSTRATE SURFACES AND CHAMBER SURFACES - Embodiments of the invention generally relate to methods for treating a silicon-containing material on a substrate surface and performing a chamber clean process. In one embodiment, a method includes positioning a substrate containing a silicon material having a contaminant thereon within a process chamber and exposing the substrate to an etching gas containing chlorine gas and a silicon source gas while removing the contaminant and maintaining a temperature of the substrate within a range from about 500° C. to less than about 800° C. during an etching process. The method further includes exposing the substrate to a deposition gas after the etching process during a deposition process and exposing the process chamber to a chamber clean gas containing chlorine gas and the silicon source gas after the deposition process during a chamber clean process. The chamber clean process limits the etching of quartz and metal surfaces within the process chamber. | 05-03-2012 |
| 20120156864 | Formation of a Channel Semiconductor Alloy by a Nitride Hard Mask Layer and an Oxide Mask - When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity. | 06-21-2012 |
| 20120231614 | METHOD OF SEMICONDUCTOR MANUFACTURING PROCESS - The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming a semiconductor substrate on the growing substrate; forming a first structure with plural grooves and between the growing substrate and the semiconductor substrate; and changing the temperature of the growing substrate and the semiconductor substrate. | 09-13-2012 |
| 20120282763 | Process Flow to Reduce Hole Defects in P-Active Regions and to Reduce Across-Wafer Threshold Voltage Scatter - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material. | 11-08-2012 |
| 20130072004 | METHOD OF INTEGRATING HIGH VOLTAGE DEVICES - The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance. | 03-21-2013 |
| 20130171808 | DOUBLE-SIDED REUSABLE TEMPLATE FOR FABRICATION OF SEMICONDUCTOR SUBSTRATES FOR PHOTOVOLTAIC CELL AND MICROELECTRONICS DEVICE MANUFACTURING - This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles. | 07-04-2013 |
| 20130171809 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure. | 07-04-2013 |
| 20130178049 | METHOD OF MANUFACTURING SUBSTRATE - The present invention is directed to a method of manufacturing a substrate, which includes loading a base substrate into a reaction furnace; forming a buffer layer on the base substrate; forming a separation layer on the buffer layer; forming a semiconductor layer on the separation layer at least two; and separating the semiconductor layer from the base substrate via the separation layer through natural cooling by unloading the base substrate from the reaction furnace. | 07-11-2013 |
| 20130196489 | METHOD FOR MANUFACTURING DEEP-TRENCH SUPER PN JUNCTIONS - The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material. | 08-01-2013 |
| 20130224936 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - Methods of manufacturing a semiconductor device are provided. The method includes constructing and arranging a semiconductor substrate to include a first active region and a second active region and forming mold patterns on the semiconductor substrate. The mold patterns have openings that expose a top surface of the semiconductor substrate. A plurality of first semiconductor fins are formed in openings at the first active region and a plurality of second semiconductor fins in openings at the second active region and selectively recessing top surfaces of the mold patterns. A recessed depth of the mold patterns on the first active region is different than a recessed depth of the mold patterns on the second active region. A gate electrode is formed over the first and second semiconductor fins. A distance between a first semiconductor fin of the plurality of first semiconductor fins and a second semiconductor fin of the plurality of second semiconductor fins adjacent the first semiconductor fin is greater than a distance between two or more first semiconductor fins of the plurality of first semiconductor fins that are adjacent each other. | 08-29-2013 |
| 20130230977 | THIN CAPPED CHANNEL LAYERS OF SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices and methods of forming the same. The method includes providing a semiconductor substrate having a channel layer over the substrate. A capping layer including silicon and having a first thickness is formed over the channel layer. The capping layer is partially oxidized to form an oxidized portion of the capping layer. The oxidized portion of the capping layer is removed to form a thinned capping layer having a second thickness less than the first thickness. | 09-05-2013 |
| 20130237041 | DEFECT CAPPING METHOD FOR REDUCED DEFECT DENSITY EPITAXIAL ARTICLES - A method for forming an epitaxial layer on a substrate surface having crystalline defect or amorphous regions and crystalline non-defect regions includes preferential polishing or etching the crystalline defect or amorphous regions relative to the crystalline non-defect regions to form a decorated substrate surface having surface recess regions. A capping layer is deposited on the decorated substrate surface to cover the crystalline non-defect regions and to at least partially fill the surface recess regions. The capping layer is patterned by removing the capping layer over the crystalline non-defect regions to form exposed non-defect regions while retaining the capping layer in at least a portion of the surface recess regions. Selective epitaxy is then used to form the epitaxial layer, wherein the capping layer in the surface recess regions restricts epitaxial growth of the epitaxial layer over the surface recess regions. | 09-12-2013 |
| 20130330915 | METHOD OF MAKING A THIN CRYSTALLINE SEMICONDUCTOR MATERIAL - A method of preparing a thin material layer from a semiconductor substrate is presented. The method entails forming a stress-generating epitaxial layer on a base substrate to form a stressed region, and achieving separation along the stressed region to produce a first part and a second part. The stress-generating epitaxial layer may be boron-doped or a Si | 12-12-2013 |
| 20140170840 | Epitaxial Formation Mechanisms of Source and Drain Regions - The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH | 06-19-2014 |
| 20140193967 | METHOD OF FORMING AN EPITAXIAL LAYER ON A SUBSTRATE, AND APPARATUS AND SYSTEM FOR PERFORMING THE SAME - In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution. | 07-10-2014 |
| 20140329376 | STRUCTURE AND METHOD OF FORMING METAMORPHIC HETEROEPI MATERIALS AND III-V CHANNEL STRUCTURES ON SI - Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A <111> surface may be formed on a substrate and a Group III-V material may be grown from the <111> surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure. | 11-06-2014 |
| 20140335683 | METHOD FOR PRODUCING GALLIUM NITRIDE - A method for producing a gallium nitride layer using a pulsed laser is disclosed. The method includes (1) providing a substrate; (2) forming a zinc oxide layer on the substrate; and (3) forming a gallium nitride thin film on the zinc oxide layer by pulsed laser deposition (PLD). | 11-13-2014 |
| 20150147873 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - Provided is a method of manufacturing a semiconductor device. The method includes: carrying a substrate, which has a Ge-containing film on at least a portion of a surface thereof, into a process chamber; heating an inside of the process chamber, into which the substrate is carried, to a first process temperature; and terminating a surface of the Ge-containing film, which is exposed at a portion of the surface of the substrate, by Si by supplying at least a Si-containing gas to the inside of the process chamber heated to the first process temperature. | 05-28-2015 |
| 20150311068 | GALLIUM NITRIDE SUBSTRATE AND MANUFACTURING METHOD OF NITRIDE SEMICONDUCTOR CRYSTAL - The main purpose of the present invention is to provide: a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a technique required for the production of the substrate. | 10-29-2015 |
| 20150340223 | FABRICATION OF THIN-FILM DEVICES USING SELECTIVE AREA EPITAXY - A thin film device described herein includes a first thin film layer, a second film layer and a heterostructure within the second film layer. The first thin film layer is atop a substrate. The second thin film layer is grown from the first thin film layer through a patterned mask, having openings, under selective area growth (SAG) conditions. The second thin film layer is configured to be released from the first thin film layer by etching a trench. The etched trench may provide access to the patterned mask and the patterned mask may be eliminated with a wet etchant. | 11-26-2015 |
| 20150372116 | Apparatus and Method for Multiple Gate Transistors - A method comprises etching away an upper portion of a substrate to form a trench between two adjacent isolation regions, wherein the substrate has a first crystal orientation and is formed of a first semiconductor material, growing a first semiconductor region in the trench over the substrate, wherein the first semiconductor region is formed of a second semiconductor material and an upper portion of the first semiconductor region has a second crystal orientation and growing a second semiconductor region over the first semiconductor region, wherein the second semiconductor region is formed of a third semiconductor material. | 12-24-2015 |
| 20160005825 | CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer. | 01-07-2016 |
| 20160013046 | ATOMIC LAYER EPITAXY FOR SEMICONDUCTOR GATE STACK LAYER FOR ADVANCED CHANNEL DEVICES | 01-14-2016 |
| 20160013274 | HALOGENATED DOPANT PRECURSORS FOR EPITAXY | 01-14-2016 |
| 20160064526 | METHODS OF FORMING ALTERNATIVE CHANNEL MATERIALS ON FINFET SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin. | 03-03-2016 |
| 20160093492 | METHOD FOR GROWING NITRIDE-BASED SEMICONDUCTOR WITH HIGH QUALITY - Disclosed is a method for growing a nitride-based semiconductor with high quality, the method including: forming a first mask layer on a substrate and forming a second mask layer on the first mask layer; performing dry etching on the first mask layer and the second mask layer to form an opening in which a part of the substrate is exposed; performing selective wet etching on the first mask layer in the opening to form a recess in which a part of the substrate is exposed; depositing a third mask layer in the recess; and growing a nitride-based semiconductor from the exposed part of the substrate on sides of the third mask layer and expanding the growth via the opening. | 03-31-2016 |
| 20160104615 | PREPARATION METHOD FOR CRYSTALLINE SILICON THIN FILM BASED ON LAYER TRANSFER - Provided is a preparation method of a crystalline silicon film. The method includes: 1) forming a mask for making a periodic silicon rod array on a monocrystalline silicon wafer substrate, and forming the periodic silicon rod array on the monocrystalline silicon substrate by a wet chemical etching or dry etching process; 2) forming barrier layers on the surface of the monocrystalline silicon substrate and the surface of the silicon rod array for next selectively epitaxial growth of silicon; 3) exposing silicon cores on the heads of the rod array by a selective etching process to form a silicon seed array; 4) growing a continuous silicon film at the top of the rod array by a chemical vapor deposition method using the exposed silicon cores as seeds for selectively epitaxial growth of silicon; and 5) lifting off the silicon film and transferring the silicon film to a preset substrate, and the seeded substrate is reusable. | 04-14-2016 |
| 20160111279 | METHOD FOR MANUFACTURING SILICON-CARBIDE SEMICONDUCTOR ELEMENT - In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate ( | 04-21-2016 |
| 20160111286 | Method of Semiconductor Device Fabrication - A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a hard mask (HM) layer over the dielectric layer, forming a fin trench through the HM layer and the dielectric layer and extending down to the substrate, forming a semiconductor feature in the fin trench and removing the HM layer to expose an upper portion of the semiconductor feature to form fin features. | 04-21-2016 |
| 20160111527 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH FIN-SHAPED STRUCTURE - A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer. | 04-21-2016 |
| 20160118257 | METHOD FOR TREATING SURFACE OF SILICON-CARBIDE SUBSTRATE - This method for treating a surface of a SiC substrate includes a first removal step in which a modified layer produced by subjecting the substrate ( | 04-28-2016 |
| 20160163543 | ACTIVE STRUCTURES OF A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening. | 06-09-2016 |
| 20160190276 | METHOD AND SYSTEM FOR IN-SITU ETCH AND REGROWTH IN GALLIUM NITRIDE BASED DEVICES - A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region. | 06-30-2016 |
