Class / Patent application number | Description | Number of patent applications / Date published |
438488000 | Polycrystalline semiconductor | 69 |
20080206970 | Production Of Polycrystalline Silicon - Polysilicon is deposited onto a tube or other hollow body. The hollow body replaces the slim rod of a conventional Siemens-type reactor and may be heated internally with simple resistance elements. The hollow body diameter is selected to provide a surface area much larger than that of a silicon slim rod. The hollow body material may be chosen such that, upon cooling, deposited polysilicon readily separates from the hollow body due to differences in contraction and falls into a collection container. | 08-28-2008 |
20080213987 | Method of Fabricating a Sige Semiconductor Structure - A method of fabricating an integrated circuit includes providing a substrate and creating base-windows in a layer. The method also includes forming a monocrystalline SiGe base layer in each of the base layers, and polycrystalline SiGe elsewhere. Additionally, the method also includes forming a monocrystalline silicon layer over selectively exposed portions of the surface of the substrate. The integrated circuit beneficially includes silicon-based elements such as a lateral pnp transistor, a varactor, and a polysilicon transistor, which are formed on a common substrate with an npn SiGe bipolar transistor. | 09-04-2008 |
20080248635 | Polycrystalline SiGe Junctions for Advanced Devices - A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions. | 10-09-2008 |
20080311731 | LOW PRESSURE CHEMICAL VAPOR DEPOSITION OF POLYSILICON ON A WAFER - Low pressure chemical vapor deposition (LPCVD) of polysilicon on a wafer in a manner that reduces the generation of particles during the deposition process. In one example embodiment, a method of LPCVD of polysilicon on a wafer positioned in a process tube includes various steps. First, introducing a particle inhibitor is introduced into the process tube. Next, a silicon source gas is introduced into the process tube. Finally, a doping gas is introduced into the process tube, resulting in the formation of a polysilicon film of a uniform thickness on the wafer. | 12-18-2008 |
20090011577 | METHOD OF MAKING PHASE CHANGE MATERIALS ELECTROCHEMICAL ATOMIC LAYER DEPOSITION - A method of making phase change materials on a substrate by electrochemical atomic layer deposition, which includes sequentially electrodepositing at least one atomic layer of a first element of a first solution and at least one atomic layer of a second element of a second solution on a substrate; and repeating the sequential electrodepositing until at least one film of a phase change material is formed on the substrate. | 01-08-2009 |
20090047775 | Method for manufacturing display device - The present invention relates to a method for manufacturing a display device including a p-channel thin film transistor and an n-channel thin film transistor having a microcrystalline semiconductor film each of which are an inverted-staggered type, and relates to a method for formation of an insulating film and a semiconductor film which are included in the thin film transistor. Two or more kinds of high-frequency powers having different frequencies are supplied to an electrode for generating glow discharge plasma in a reaction chamber. High-frequency powers having different frequencies are supplied to generate glow discharge plasma, so that a thin film of a semiconductor or an insulator is formed. High-frequency powers having different frequencies (different wavelength) are superimposed and applied to the electrode of a plasma CVD apparatus, so that densification and uniformity of plasma for preventing the effect of surface standing wave of plasma can be realized. | 02-19-2009 |
20090117717 | METHODS OF SELECTIVELY DEPOSITING SILICON-CONTAINING FILMS - An embodiment provides a method for selectively depositing a single crystalline film. The method includes providing a substrate, which includes a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology. A silicon precursor and BCl | 05-07-2009 |
20090209093 | PLASMA DEPOSITION APPARATUS AND METHOD FOR MAKING POLYCRYSTALLINE SILICON - A plasma deposition apparatus for making polycrystalline silicon including a chamber for depositing said polycrystalline silicon, the chamber having an exhaust system for recovering un-deposited gases; a support located within the deposition chamber for holding a target substrate having a deposition surface, the deposition surface defining a deposition zone; at least one induction coupled plasma torch located within the deposition chamber and spaced apart from the support, the at least one induction coupled plasma torch producing a plasma flame that is substantially perpendicular to the deposition surface, the plasma flame defining a reaction zone for reacting at least one precursor gas source to produce the polycrystalline silicon for depositing a layer of the polycrystalline silicon the deposition surface. | 08-20-2009 |
20090317962 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR PRODUCTION EQUIPMENT AND STORAGE MEDIUM - A method for manufacturing a semiconductor device, semiconductor production equipment, and a storage medium, which suppress abnormal arc discharge occurring when plasma is excited while preventing misalignment of a substrate placed on an electrostatic chuck, are provided. The method includes a first process in which a substrate is placed on an electrostatic chuck in a reaction container and a first electrostatic chuck voltage is applied to the electrostatic chuck to absorb the substrate onto the electrostatic chuck, a second process in which the first electrostatic chuck voltage is reduced to a second electrostatic chuck voltage, a third process in which a high-frequency voltage is applied between parallel plate electrodes in the reaction container to generate plasma, and a fourth process in which the second electrostatic chuck voltage is changed to a third electrostatic chuck voltage higher than the second electrostatic chuck voltage. | 12-24-2009 |
20100041215 | METHODS FOR PREPARATION OF HIGH-PURITY POLYSILICON RODS USING A METALLIC CORE MEANS - The present invention relates to a method for preparing a polysilicon rod using a metallic core means, comprising: installing a core means in an inner space of a deposition reactor used for preparing a silicon rod, wherein the core means is constituted by forming one or a plurality of separation layer(s) on the surface of a metallic core element and is connected to an electrode means; heating the core means by supplying electricity through the electrode means; and supplying a reaction gas into the inner space for silicon deposition, thereby forming a deposition output in an outward direction on the surface of the core means. According to the present invention, the deposition output and the core means can be separated easily from the silicon rod output obtained by the process of silicon deposition, and the contamination of the deposition output caused by impurities of the metallic core element can be minimized, thereby a high-purity silicon can be prepared in a more economic and convenient way. | 02-18-2010 |
20100068871 | Microwave Heating for Semiconductor Nanostructure Fabrication - The present invention grows nanostructures using a microwave heating-based sublimation-sandwich SiC polytype growth method comprising: creating a sandwich cell by placing a source wafer parallel to a substrate wafer, leaving a small gap between the source wafer and the substrate wafer; placing a microwave heating head around the sandwich cell to selectively heat the source wafer to a source wafer temperature and the substrate wafer to a substrate wafer temperature; creating a temperature gradient between the source wafer temperature and the substrate wafer temperature; sublimating Si- and C-containing species from the source wafer, producing Si- and C-containing vapor species; converting the Si- and C-containing vapor species into liquid metallic alloy nanodroplets by allowing the metalized substrate wafer to absorb the Si- and C-containing vapor species; and growing nanostructures on the substrate wafer once the alloy droplets reach a saturation point for SiC. The substrate wafer may be coated with a thin metallic film, metal nanoparticles, and/or a catalyst. | 03-18-2010 |
20100129996 | SILICON MATERIAL SURFACE ETCHING FOR LARGE GRAIN POLYSILICON THIN FILM DEPOSITION AND STRUCTURE - A method of surface treatment for silicon material. The method includes providing a first silicon material having a surface region. The first silicon material has a first purity characteristics and a first surface roughness characteristics. A chemical polishing process is perform to the surface region to cause the surface region to have a second roughness characteristics. Thereafter, a chemical leaching process is performed to the surface region to cause the first silicon material in a depth within a vicinity of the surface region to have a second purity characteristics. A polysilicon material characterized by a grain size greater than about 0.1 mm is formed using a deposition process overlying the surface region. | 05-27-2010 |
20100144129 | Method of manufacturing crystalline silicon - Disclosed is a method of manufacturing crystalline Si by using plasma. According to the disclosed method, silicon (Si) deposition and reduction processes using plasma are cyclically performed in order to completely remove an a-Si layer so as to form crystalline Si on a substrate early in the process. | 06-10-2010 |
20100151666 | Novel Methods for Making and Using Halosilylgermanes - The invention provides compounds of, and methods for the preparation of compounds of, the molecular formula, Si | 06-17-2010 |
20100159677 | SOLID-PHASE SHEET GROWING SUBSTRATE AND METHOD OF MANUFACTURING SOLID-PHASE SHEET - A solid-phase sheet growing substrate ( | 06-24-2010 |
20100197122 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed. Further, a second growing operation for selectively growing the second polycrystalline semiconductor layer and the third polycrystalline semiconductor layer on the exposed portion of the p-type polycrystalline semiconductor film exposed in the lower surface of the visor section without contacting the silicon nitride film, while growing the second semiconductor layer and the third semiconductor layer, so that the third semiconductor layer is in contact with the third polycrystalline semiconductor layer. | 08-05-2010 |
20100210093 | METHOD FOR FORMING SILICON-BASED THIN FILM BY PLASMA CVD METHOD - In the method for forming a silicon-based thin film by the plasma CVD method using high-frequency excitation, a polycrystalline silicon-based thin film having high degree of crystallization is formed relatively at a low temperature, economically, and productively. | 08-19-2010 |
20100285657 | GROWTH REACTOR FOR GALLIUM-NITRIDE CRYSTALS USING AMMONIA AND HYDROGEN CHLORIDE - The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor chamber may be configured to enhance ammonium chloride formation, and the powder may be collected efficiently in it. To avoid ammonium chloride formation in the main reactor, the connection between the main reactor and the second reaction chamber can be maintained at elevated temperature. In addition, the second reactor chamber may have two or more exhaust lines. If one exhaust line becomes clogged with powder, the valve for an alternative exhaust line may open and the valve for the clogged line may be closed to avoid overpressuring the system. The quartz-made main reactor may have e.g. a pyrolytic boron nitride liner to collect polycrystalline gallium nitride efficiently. The new HYPE reactor which can grow gallium nitride crystals for more than 1 day may produce enough source material for ammonothermal growth. Single crystalline gallium nitride and polycrystalline gallium nitride from the HYPE reactor may be used as seed crystals and a nutrient for ammonothermal group III-nitride growth. | 11-11-2010 |
20100297835 | METHODS FOR FABRICATING COPPER INDIUM GALLIUM DISELENIDE (CIGS) COMPOUND THIN FILMS - A method for fabricating a copper-indium-gallium-diselenide (CIGS) compound thin film is provided. In this method, a substrate is first provided. An adhesive layer is formed over the substrate. A metal electrode layer is formed over the adhesive layer. A precursor stacked layer is formed over the metal electrode layer, wherein the precursor stacked layer includes a plurality of copper-gallium (CuGa) alloy layers and at least one copper-indium (CuIn) alloy layer sandwiched between the plurality of CuGa alloy layers. An annealing process is performed to convert the precursor stacked layer into a copper-indium-gallium (CuInGa) alloy layer. A selenization process is performed to convert the CuInGa alloy layer into a copper-indium-gallium-diselenide (CuInGaSe) compound thin film. | 11-25-2010 |
20110014782 | Apparatus and Method for Growing a Microcrystalline Silicon Film - Disclosed is a method for growing a microcrystalline silicon film on a substrate. The method includes the step of disposing the substrate in a chamber, the step of vacuuming the chamber and heating the substrate, the step of introducing reacting gas into the chamber as a precursor and keeping the pressure in the chamber at a predetermined value and the step of using RF energy in the chamber to dissociate the reacting gas to form plasma for growing the microcrystalline silicon film on the substrate. The reacting gas includes SiH | 01-20-2011 |
20110039402 | METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR FILM AND THIN FILM TRANSISTOR - A microcrystalline semiconductor film with high crystallinity is manufactured. In addition, a thin film transistor with excellent electric characteristics and high reliability, and a display device including the thin film transistor are manufactured with high productivity. A deposition gas containing silicon or germanium is introduced from an electrode including a plurality of projecting portions provided in a treatment chamber of a plasma CVD apparatus, glow discharge is caused by supplying high-frequency power, and thereby crystal particles are formed over a substrate, and a microcrystalline semiconductor film is formed over the crystal particles by a plasma CVD method. | 02-17-2011 |
20110045662 | LOW-TEMPERATURE FORMATION OF LAYERS OF POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - The present invention provides a method for forming a layer ( | 02-24-2011 |
20110053356 | GAS MIXING METHOD REALIZED BY BACK DIFFUSION IN A PECVD SYSTEM WITH SHOWERHEAD - Embodiments of the present invention generally relate to methods of forming a microcrystalline silicon layer on a substrate in a deposition chamber. In, one embodiment, the method includes flowing a processing gas into a diffuser region between a backing plate and a showerhead of the deposition chamber, flowing the processing gas through a plurality of holes in the showerhead and into a process volume between the showerhead and a substrate support in the deposition chamber, igniting a plasma in the process volume, back-flowing gas ions formed in the plasma through the plurality of holes in the showerhead and into the diffuser region, mixing the gas ions and the processing gas in the diffuser region, re-flowing the gas ions and processing gas through the plurality of holes in the showerhead and into the process volume, and depositing a microcrystalline silicon layer on the substrate. | 03-03-2011 |
20110053357 | PLASMA CVD APPARATUS, METHOD FOR FORMING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A structure of a plasma CVD apparatus for forming a dense semiconductor film is provided. Further, a technique for forming a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains is provided. An electrode supplied with electric power for generating plasma is included in a reaction chamber of the plasma CVD apparatus. This electrode has a common plane on a surface opposite to a substrate, and the common plane is provided with depressed openings. Gas supply ports are provided on the bottom of the depressed openings or on the common plane of the electrode. The depressed openings are provided in isolation from one another. | 03-03-2011 |
20110053358 | METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus. | 03-03-2011 |
20110086498 | Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures - Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials. | 04-14-2011 |
20110136327 | HIGH MOBILITY MONOLITHIC P-I-N DIODES - Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers. | 06-09-2011 |
20110136328 | METHOD FOR DEPOSITING ULTRA FINE GRAIN POLYSILICON THIN FILM - According to the present invention, a method for depositing an ultra-fine crystal particle polysilicon thin film supplies a source gas in a chamber loaded with a substrate to deposit a polysilicon thin film on the substrate, wherein the source gas contains a silicon-based gas, an oxygen-based gas and a phosphorous-based gas. The mixture ratio of the oxygen-based gas to the silicon-based gas may be 0.15 or lower (but, excluding zero). Oxygen in the thin film may be 0.8 atomic percent or lower (but, excluding zero). | 06-09-2011 |
20110177682 | SUPPRESSION OF OXYGEN PRECIPITATION IN HEAVILY DOPED SINGLE CRYSTAL SILICON SUBSTRATES - This invention generally relates to a process for suppressing oxygen precipitation in epitaxial silicon wafers having a heavily doped silicon substrate and a lightly N-doped silicon epitaxial layer by dissolving existing oxygen clusters and precipitates within the substrate. Furthermore, the formation of oxygen precipitates is prevented upon subsequent oxygen precipitation heat treatment. | 07-21-2011 |
20110207305 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region. | 08-25-2011 |
20110250739 | EPITAXIAL WAFER HAVING A HEAVILY DOPED SUBSTRATE AND PROCESS FOR THE PREPARATION THEREOF - This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops. | 10-13-2011 |
20110275200 | METHODS OF DYNAMICALLY CONTROLLING FILM MICROSTRUCTURE FORMED IN A MICROCRYSTALLINE LAYER - A method for an intrinsic type microcrystalline silicon layer is provided. In one embodiment, a method for forming an intrinsic type microcrystalline silicon layer includes dynamically ramping up a silane gas supplied in a gas mixture to a surface of a substrate disposed in a processing chamber, dynamically ramping down a RF power applied in the gas mixture supplied to the processing chamber to form a plasma in the gas mixture, and forming an intrinsic type microcrystalline silicon layer on the substrate. | 11-10-2011 |
20110300694 | ELECTRODE CIRCUIT, FILM FORMATION DEVICE, ELECTRODE UNIT, AND FILM FORMATION METHOD - An electrode circuit for plasma CVD includes: an alternating-current source; a matching circuit that is connected to the alternating-current source; and parallel plate electrodes that are constituted of a pair of an anode electrode and a cathode electrode, in which the anode electrode and the cathode electrode are arranged such that electrode surfaces of the anode electrode and the cathode electrode face each other. The matching circuit, the parallel plate electrodes, and plasma generated by the parallel plate electrodes form a balanced circuit. | 12-08-2011 |
20110306189 | METHOD FOR ETCHING AND FILLING DEEP TRENCHES - A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer. | 12-15-2011 |
20110312166 | Methods of Manufacturing Power Semiconductor Devices with Shield and Gate Contacts - Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first conductive layer away inside an active trench, forming a second oxide layer and second conductive layer. The second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench. The methods further include forming a third oxide layer over the second conductive layer, etching a first opening through the third oxide layer exposing the second conductive layer outside the active trench, etching a second opening through the second oxide layer outside the active trench in the first region exposing the first conductive layer but not the second conductive layer, and filling the first and second openings with conductive material. | 12-22-2011 |
20110318909 | SYSTEM AND METHOD OF SEMICONDUCTOR MANUFACTURING WITH ENERGY RECOVERY - The invention can provide or facilitate energy recovery operations during semiconductor processing operations by utilizing a bell jar having a radiation shield thereon that is comprised of a mediating layer comprising nickel disposed on an interior surface of the bell jar, and a reflective layer which can comprise a gold layer that is disposed on the mediating layer. The reflective layer has an emissivity of less than 5% and, more preferably, the reflective layer has an emissivity of less than about 1%. Heat from the reaction chamber can be used to reduce the heating load of one or more other unit operations. | 12-29-2011 |
20120028451 | SHAPED NANOCRYSTAL PARTICLES AND METHODS FOR MAKING THE SAME - Shaped nanocrystal particles and methods for making shaped nanocrystal particles are disclosed. One embodiment includes a method for forming a branched, nanocrystal particle. It includes (a) forming a core having a first crystal structure in a solution, (b) forming a first arm extending from the core having a second crystal structure in the solution, and (c) forming a second arm extending from the core having the second crystal structure in the solution. | 02-02-2012 |
20120040519 | METHOD FOR FORMING SILICON FILM HAVING MICROCRYSTAL STRUCTURE - A method for forming a silicon film having a microcrystal structure is provided. The method includes following steps. A plasma-enhanced chemical vapor deposition system having a reaction chamber, a top electrode and a bottom electrode is provided. The top electrode and the bottom electrode are opposite and disposed in the reaction chamber. A substrate is disposed on the bottom electrode. A silane gas is applied into the reaction chamber. A silicon film having a microcrystal structure is formed by simultaneously irradiating the silane gas in the reaction chamber by a carbon dioxide laser and performing a plasma-enhanced chemical vapor deposition step. | 02-16-2012 |
20120040520 | ULTRA-FINE-GRAINED POLYSILICON THIN FILM VAPOUR-DEPOSITION METHOD - Provided is a method of depositing an ultra-fine grain polysilicon thin film. The method includes forming a nitrogen atmosphere in a chamber loaded with a substrate, and supplying a source gas into the chamber to deposit a polysilicon thin film on the substrate, in which the source gas includes a silicon-based gas, a nitrogen-based gas, and a phosphorous-based gas. The forming of the nitrogen atmosphere may include supplying a nitrogen-based gas into the chamber. | 02-16-2012 |
20120142172 | PECVD DEPOSITION OF SMOOTH POLYSILICON FILMS - Smooth silicon and silicon germanium films are deposited by plasma enhanced chemical vapor deposition (PECVD). The films are characterized by roughness (Ra) of less than about 4 Å. In some embodiments, smooth silicon films are undoped and doped polycrystalline silicon films. The dopants can include boron, phosphorus, and arsenic. In some embodiments the smooth polycrystalline silicon films are also highly conductive. For example, boron-doped polycrystalline silicon films having resistivity of less than about 0.015 Ohm cm and Ra of less than about 4 Å can be deposited by PECVD. In some embodiments smooth silicon films are incorporated into stacks of alternating layers of doped and undoped polysilicon, or into stacks of alternating layers of silicon oxide and doped polysilicon employed in memory devices. Smooth films can be deposited using a process gas having a low concentration of silicon-containing precursor and/or a process gas comprising a silicon-containing precursor and H | 06-07-2012 |
20120171852 | REMOTE HYDROGEN PLASMA SOURCE OF SILICON CONTAINING FILM DEPOSITION - Methods for forming and treating a silicon containing layer in a thin film transistor structure or solar cell devices are provided. In one embodiment, a method for forming a silicon containing layer on a substrate includes providing a substrate into a processing chamber, providing a gas mixture having a silicon containing gas into the processing chamber, providing a hydrogen containing gas from a remote plasma source coupled to the processing chamber, applying a RF power less than 17.5 mWatt/cm | 07-05-2012 |
20120315745 | CRYSTALLINE SILICON FILM FORMING METHOD AND PLASMA CVD APPARATUS - A high-quality crystalline silicon film can be formed at a high film forming rate by performing a plasma CVD process. In a crystalline silicon film forming method for forming a crystalline silicon film on a surface of a processing target object by using a plasma CVD apparatus for introducing microwave into a processing chamber through a planar antenna having a multiple number of holes and generating plasma, the crystalline silicon film forming method includes generating plasma by exciting a film forming gas containing a silicon compound represented as Si | 12-13-2012 |
20120322246 | FABRICATION METHODS OF INTEGRATED SEMICONDUCTOR STRUCTURE - A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region. | 12-20-2012 |
20130034950 | METHOD FOR FABRICATING P-TYPE POLYCRYSTALLINE SILICON-GERMANIUM STRUCTURE - A method for fabricating a P-type polycrystalline silicon-germanium structure comprises steps: forming an aluminum layer and an amorphous germanium layer on a P-type monocrystalline silicon substrate in sequence; annealing the P-type monocrystalline silicon substrate, the aluminum layer and the amorphous germanium layer at a temperature of 400-650° C.; and undertaking an aluminum-induced crystallization process in which germanium atoms of the amorphous germanium layer and silicon atoms of the P-type monocrystalline silicon substrate simultaneously pass through the aluminum layer and then the amorphous germanium layer being induced and converted into a P-type polycrystalline silicon-germanium layer between the P-type monocrystalline silicon substrate and the aluminum layer. The present invention is a simple, reliable and low-cost method to fabricate a P-type polycrystalline silicon-germanium layer on a P-type monocrystalline silicon substrate. In addition, the obtained P-type polycrystalline silicon-germanium layer can convert sunlight of longer wavelengths into electric energy. | 02-07-2013 |
20130059432 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern. | 03-07-2013 |
20130109158 | Methods of Fabricating Semiconductor Devices Using Mask Shrinking | 05-02-2013 |
20130157448 | METHOD FOR MANUFACTURING A SILICON CARBIDE WAFER AND RESPECTIVE EQUIPMENT - An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer. | 06-20-2013 |
20130203247 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant. | 08-08-2013 |
20130260540 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element. | 10-03-2013 |
20130280896 | APPARATUS FOR PRODUCING POLYCRYSTALLINE SILICON AND METHOD THEREFOR - To provide an apparatus for producing polycrystalline silicon and a method therefor to allow improvement in efficiency of polycrystalline silicon production by minimizing reactor downtime and to allow polycrystalline silicon production at a relatively low cost and in a large amount in a zinc reduction process for recovering formed silicon in a solid state. In a silicon producing apparatus for producing polycrystalline silicon by reducing silicon tetrachloride with zinc, vertical reactor | 10-24-2013 |
20140134832 | POLYCRYSTALLINE SILICON MANUFACTURING APPARATUS AND POLYCRYSTALLINE SILICON MANUFACTURING METHOD - In order to obtain a polycrystalline silicon rod having an excellent shape, the placement relation between a source gas supplying nozzle | 05-15-2014 |
20140162441 | SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT - In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article. | 06-12-2014 |
20140235041 | CHEMICAL VAPOR DEPOSITION REACTOR HAVING CERAMIC LINING FOR PRODUCTION OF POLYSILICON - Apparatus configured to produce polysilicon by chemical vapor deposition, including a reactor vessel having an inner surface defining at least a portion of a chamber, the inner surface having a lining of quartz ceramic. The apparatus also includes a silicon substrate disposed within the chamber of the reactor vessel, the silicon substrate having a deposition surface upon which polysilicon is deposited. Methods of producing polysilicon using such apparatus, as well as methods for applying the quartz ceramic lining onto a reactor vessel, are also provided. | 08-21-2014 |
20140315375 | SUBSTRATE PROCESSING APPARATUS INCLUDING EXHAUST PORTS AND SUBSTRATE PROCESSING METHOD - Provided is a substrate processing apparatus. The substrate processing apparatus in which processes with respect to substrates are performed includes a lower chamber having an opened upper side, the lower chamber including a passage allowing the substrates to pass therethrough in a side thereof, an external reaction tube closing the opened upper side of the lower chamber to provide a process space in which the processes are performed, a substrate holder on which the one or more substrates are vertically stacked, the substrate holder being movable between a stacking position in which the substrates are stacked within the substrate holder and a process position in which the processes with respect to the substrates are performed, at least one supply nozzle disposed along an inner wall of the external reaction tube, the at least one supply nozzle having a supply hole for discharging a reaction gas, at least one exhaust nozzle disposed along the inner wall of the external reaction tube, the at least one exhaust nozzle having an exhaust hole for suctioning an non-reaction gas and byproducts within the process space, and a rear exhaust line connected to the exhaust nozzle to discharge the non-reaction gas and the byproducts which are suctioned through the exhaust hole. The lower chamber includes an exhaust port connecting the exhaust nozzle to the rear exhaust line and an auxiliary exhaust port connecting a stacking space defined within the lower chamber to the rear exhaust line. | 10-23-2014 |
20140322900 | LOW-PRESSURE CHEMICAL VAPOR DEPOSITION APPARATUS AND THIN-FILM DEPOSITION METHOD THEREOF - A low-pressure chemical vapor deposition (LPCVD) apparatus and a thin-film deposition method thereof The apparatus comprises a reaction furnace, having reaction gas input pipelines respectively arranged at a furnace opening part and a furnace tail part. During thin film deposition, each reaction gas is synchronously introduced into the reaction furnace through the input pipeline at the furnace opening part and the input pipeline at the furnace tail part. | 10-30-2014 |
20150017787 | METHOD AND APPARATUS TO REDUCE CONTAMINATION OF PARTICLES IN A FLUIDIZED BED REACTOR - A method and fluidized bed reactor for reducing or eliminating contamination of silicon-coated particles are disclosed. The metal surface of one or more fluidized bed reactor components is at least partially coated with a hard protective layer comprising a material having an ultimate tensile strength of at least 700 MPa at 650° C. | 01-15-2015 |
20150017788 | METHOD FOR MAKING SILICON-GERMANIUM ABSORBERS FOR THERMAL SENSORS - A system and method for growing polycrystalline silicon-germanium film that includes mixing a GeH | 01-15-2015 |
20150064885 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNELS AND SEMICONDUCTOR DEVICES FORMED USING SUCH METHODS - Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate. | 03-05-2015 |
20150132927 | POLYSILICON MANUFACTURING METHOD THAT CONTROLS GROWTH DIRECTION OF POLYSILICON - The present invention provides a polysilicon manufacturing method that controls a growth direction of polysilicon, including the following steps: (1) forming a first buffer layer ( | 05-14-2015 |
20150140795 | METHOD FOR PRODUCING SEMICONDUCTOR THIN FILMS ON FOREIGN SUBSTRATES - The invention relates to a method by means of which the average single crystal size, in particular the diameter of the single crystals, in a semiconductor thin film applied to a foreign substrate can be increased by an order of magnitude with respect to prior methods. The method is characterized in that a thin semiconductor film is applied to the foreign substrate in a first step. Then the foreign substrate is heated to such an extent that the semiconductor thin film melts. Then the temperature is slowly decreased to below the melting temperature of the semiconductor material. During the cooling process, the foreign substrate is heated in such a way that, proceeding from the surface of the foreign substrate, the temperature continuously decreases in a vertical direction perpendicular through the semiconductor thin film to the surface of the thin film. It is thereby ensured that the thin film crystallizes, or rather solidifies, in the opposite direction during the slow decrease of the temperature to below the melting temperature of the semiconductor thin film. In other words, the atom layers directly at the exposed surface of the thin film crystallize first, then the next deeper atom layers crystallize, etc., until finally the atom layers in the immediate vicinity of the surface of the foreign substrate crystallize. The atom layers directly at the exposed surface of the thin film can freely orient themselves without interference during the crystallization, whereby the formation of extensive single crystals several atom layers thick is promoted. Said extensive single crystals are then used as growth nuclei for the next deeper atom layers in such a way that said extensive single crystals grow in thickness in the direction of the surface of the foreign substrate. Only the atom layers in the immediate vicinity of the surface of the foreign substrate are interfered with during the crystallization and degrade into an amorphous or polycrystalline boundary layer. In order to ensure the aforementioned temperature course perpendicular through the thin film, either a heat source applied to the underside of the foreign substrate in a planar manner or heating of the foreign substrate by means of electric current passage must be selected as the heating type. The method is suitable in particular for producing highly efficient thin film solar cells. The method is also suitable for high-quality annealing of high-temperature semiconductor thin films. | 05-21-2015 |
20150147872 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL POLISHING - Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process. | 05-28-2015 |
20150340236 | METHOD FOR REDUCING DEFECTS IN POLYSILICON LAYERS - Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device. The method comprises providing a substrate, forming an insulating layer over the substrate, and forming a conductive structure over the insulating layer. The conductive structure is formed by forming a first conductive layer, performing a degassing preparation process over a surface of the first conductive layer to substantially prevent a degassing of the first conductive layer from reaching a second conductive layer, and forming the second conductive layer over the first conductive layer. | 11-26-2015 |
20150364323 | METHOD FOR DEPOSITING POLYCRYSTALLINE SILICON - The Siemens process for deposition of polycrystalline silicon in the form of rods in a sealed reactor is improved by, after introduction of deposition gas has ceased, introducing a ventilating gas into the partially sealed reactor, withdrawing a gas stream from the reactor, and monitoring the components in the gas stream withdrawn until a desired concentration of one or more components is reached, and opening the reactor to remove the rods. | 12-17-2015 |
20160111284 | STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET - Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C. | 04-21-2016 |
20220139694 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING PLASMA-ENHANCED ATOMIC LAYER DEPOSITION - A method for fabricating a semiconductor device by using a plasma-enhanced atomic layer deposition apparatus. A substrate comprising a silicon substrate and a first oxide layer is provided. A plurality of stacked structures are deposited on the substrate, which comprises a dielectric layer and a conductive layer. The stacked structures are etched to form trenches. A second oxide layer is deposited by using a plasma-enhanced atomic layer deposition apparatus that includes a chamber, an upper electrode, a lower electrode, and a three-dimensional rotation device. The upper electrode is connected to a first radio-frequency power device. The upper electrode is configured to generate a plasma. The lower electrode is connected to a second radio-frequency power device. The three-dimensional rotation device drives the substrate to rotate. A high resistance layer is deposited on the second oxide layer. A low resistance layer is deposited on the high resistance layer. | 05-05-2022 |
438491000 | And subsequent doping of polycrystalline semiconductor | 4 |
20110287615 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse. | 11-24-2011 |
20130164921 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided. | 06-27-2013 |
20150093886 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method of one embodiment of the present invention is disclosed for growing a polycrystalline silicon layer on a base material to be processed. The plasma processing method includes: (a) a step for preparing, in a processing container, the base material to be processed; and (b) a step for growing the polycrystalline silicon layer on the base material by introducing microwaves for plasma excitation into the processing container, and introducing a silicon-containing raw material gas into the processing container. | 04-02-2015 |
20150303347 | GaAs THIN FILMS AND METHODS OF MAKING AND USING THE SAME - Disclosed herein are embodiments of methods for making GaAs thin films, such as photovoltaic GaAs thin films. The methods disclosed herein utilize sources, precursors, and reagents that do not produce (or require) toxic gas and that are readily available and relatively low in cost. In some embodiments, the methods are readily scalable for industrial applications and can provide GaAs thin films having properties that are at least comparable to or potentially superior to GaAs films obtained from conventional methods. | 10-22-2015 |