| Entries |
| Document | Title | Date |
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| 20080200013 | GALLIUM NITRIDE MATERIALS AND METHODS ASSOCIATED WITH THE SAME - Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance. | 08-21-2008 |
| 20080206966 | QUANTUM DOTS NUCLEATION LAYER OF LATTICE MISMATCHED EPITAXY - Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies. | 08-28-2008 |
| 20080206967 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A thin semiconductor film is crystallized in a high yield by being irradiated with laser light. An insulating film, a semiconductor film, an insulating film, and a semiconductor film are stacked in this order over a substrate. Laser light irradiation is performed from above the substrate to melt the semiconductor films of a lower layer and an upper layer, whereby the semiconductor film of the lower layer is crystallized. With the laser light irradiation, the semiconductor film of the upper layer changes to a liquid state, thereby reflecting the laser light and preventing the semiconductor film of the lower layer from being overheated with the laser light. Further, by melting the semiconductor film of the upper layer as well, time for melting the semiconductor film of the lower layer can be extended. | 08-28-2008 |
| 20080213981 | Method of Fabricating a Silicon-On-Insulator Structure - In the field of sensor fabrication, it is known to form a silicon-on-insulator starting structure from which fabrication of the sensor based. The present invention provides a method of forming a silicon-on-insulator structure comprising a substrate having an insulating layer patterned thereon. A silicon oxide layer is then deposited over the patterned insulating layer before silicon is grown over both an exposed surface of the substrate as well as the silicon oxide layer, mono-crystalline silicon forming on the exposed parts of the substrate and polysilicon forming on the silicon oxide layer. After depositing a capping layer over the structure, the wafer is heated, whereby the polysilicon re-crystallises to form mono-crystalline silicon, resulting in the insulating layer being buried beneath mono-crystalline silicon. | 09-04-2008 |
| 20080227273 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) forming a first groove exposing a side of the first semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; d) forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the first groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; e) respectively forming a third semiconductor layer on an upper surface of the semiconductor substrate and a lower surface of the second semiconductor layer that are facing an inside of the cavity while leaving a space in the cavity; and f) thermally oxidizing the third semiconductor layer so as to form a buried oxide film in the cavity. | 09-18-2008 |
| 20080233717 | SOI WAFER AND MANUFACTURING METHOD THEREOF - An SOI wafer which does not generate slip dislocation even if laser annealing is performed for no more than 0.1 seconds at a maximum temperature of 1200° C. or more is provided. | 09-25-2008 |
| 20080268621 | METHOD FOR MANUFACTURING COMPOUND MATERIAL WAFER AND CORRESPONDING COMPOUND MATERIAL WAFER - The invention relates to methods for manufacturing compound material wafers, in particular silicon on insulator wafers, by the steps of providing a donor substrate, forming an insulating layer, providing a handle substrate, creating a predetermined splitting area in the donor substrate, attaching the donor substrate to the handle substrate and detaching at the predetermined splitting area to achieve the compound material wafer. In order to be able to more often reuse the remainder of the donor substrate in subsequent manufacturing runs, various embodiments are disclosed, such as the insulating layer can be provided on the donor substrate at a maximum thickness of 500 A, or that the insulating layer can be provided by deposition or only upon the handle substrate. Alternatively, no insulating layer is provided so that the donor and handle substrates can have different crystal orientations. | 10-30-2008 |
| 20080305618 | METHOD OF FORMING POLYCRYSTALLINE SEMICONDUCTOR FILM - A method of forming a polycrystalline semiconductor film, which includes irradiating an amorphous semiconductor film formed on an insulating substrate with light to convert the amorphous semiconductor into a polycrystalline semiconductor with laterally grown crystal grains, thus forming a polycrystalline semiconductor film, wherein crystal growth in the semiconductor is controlled such that first crystal grains laterally grow in the first direction along a X-axis from the first group of initial nuclei, the second crystal grains laterally grow in the second direction opposite to the first direction along the X-axis from the second group of initial nuclei arranged apart from the first group of initial nuclei along the X-axis, and the first crystal grains collide against the second crystal grains at different points in time along a Y-axis. | 12-11-2008 |
| 20080311729 | Atmospheric Pressure Chemical Vapor Deposition - A process for coating a substrate at atmospheric pressure comprises the steps of vaporizing a controlled mass of semiconductor material at substantially atmospheric pressure within a heated inert gas stream, to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture at substantially atmospheric pressure onto the substrate having a temperature below the condensation temperature of the semiconductor material, and depositing a layer of the semiconductor material onto a surface of the substrate. | 12-18-2008 |
| 20080311730 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING GATE THEREOF - A method of forming a gate of a semiconductor device includes providing a semiconductor substrate in which an active region is defined by isolation films, forming a gate insulating film on the active region, forming a capping film on the gate insulating film, and performing an annealing process on the resulting surface and then forming a gate in part of the active region. The capping film is formed on the gate insulating film to prevent a reaction between the gate insulating film and subsequent gate materials, thereby preventing a phenomenon in which the work function of a gate changes and also the creation of a gate insulator having a low dielectric constant. The annealing process is performed under fluorine gas ambient to prevent trap sites within the gate insulating film while the gate can be composed of a metal or fully silicided gate to reduce the EOT. | 12-18-2008 |
| 20090004831 | METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES - A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same. | 01-01-2009 |
| 20090004832 | Thick Film Semiconducting Inks - A method of producing a printable composition comprises mixing a quantity of particulate semiconductor material with a quantity of a binder. The semiconductor material is typically nanoparticulate silicon with a particle size in the range from 5 nanometres to 10 microns. The binder is a self-polymerising material comprising a natural oil, or a derivative or synthetic analogue thereof. Preferably the binder comprises a natural polymer formed by auto-polymerisation of a precursor consisting of a natural oil, or its derivatives including pure unsaturated fatty acids, mono- and di-glycerides, or methyl and ethyl esters of the corresponding fatty acids. The method may include applying the printable composition to a substrate, in single or multiple layers, and allowing the printable composition to cure to define the component or conductor on the substrate. | 01-01-2009 |
| 20090011574 | Method for surface modification of semiconductor layer and method of manufacturing semiconductor device - A method for surface modification of a semiconductor layer and a method of manufacturing a semiconductor device are provided. The method for surface modification of the silicon layer includes following steps. First, a semiconductor layer having several particles on its surface is provided. Next, these particles are removed through a clean process. In the clean process, the semiconductor layer is exposed to an organic matter remover, a first peroxide mixture solution and a second peroxide mixture solution sequentially. | 01-08-2009 |
| 20090011575 | Manufacturing method of SOI substrate and manufacturing method of semiconductor device - It is object to provide a manufacturing method of an SOI substrate provided with a single-crystal semiconductor layer, even in the case where a substrate having a low allowable temperature limit, such as a glass substrate, is used and to manufacture a high-performance semiconductor device using such an SOI substrate. Light irradiation is performed on a semiconductor layer which is separated from a semiconductor substrate and bonded to a support substrate having an insulating surface, using light having a wavelength of 365 nm or more and 700 nm or less, and a film thickness d (nm) of the semiconductor layer which is irradiated with the light is made to satisfy d=λ/2n×m±α (nm), when a light wavelength is λ (nm), a refractive index of the semiconductor layer is n, m is a natural number greater than or equal to 1 (m=1, 2, 3, 4, . . . ), and 0≦α≦10 is satisfied. | 01-08-2009 |
| 20090029532 | Method for forming a microcrystalline silicon film - This invention provides a method for forming a microcrystalline silicon film, which employs a three-stage deposition process to form a microcrystalline film. A microcrystalline silicon seed layer is formed on a substrate. Gaseous ions are used to bombard a surface of the microcrystalline silicon seed layer. Microcrystalline silicon is formed on the microcrystalline silicon seed layer after the bombardment to a predetermined thickness. | 01-29-2009 |
| 20090035922 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more. | 02-05-2009 |
| 20090035923 | Method for manufacturing a semiconductor device - A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film. | 02-05-2009 |
| 20090042371 | LASER CRYSTALLIZATION PROCESS AND LASER PROCESS - The present invention provides a laser crystallization process applicable to a fabrication of a stack device structure. The process starts with providing a substrate having active devices formed thereon. Next, a first dielectric layer is formed on the substrate, and a multi-layer reflective layer is formed on the first dielectric layer. Then, a second dielectric layer is formed on the multi-layer reflective layer, and amorphous silicon islands are formed on the second dielectric layer. After that, a laser annealing step is performed so that the amorphous silicon islands are crystallized so as to form a poly-silicon active layer. | 02-12-2009 |
| 20090047774 | Plasma CVD apparatus, method for manufacturing microcrystalline semiconductor layer, and method for manufacturing thin film transistor - As an electrode area of a plasma CVD apparatus is enlarged, influence of the surface standing wave remarkably appears, and there is a problem in that in-plane uniformity of quality and a thickness of a thin film formed over a glass substrate is degraded. Two or more high-frequency electric powers with different frequencies are supplied to an electrode for producing glow discharge plasma in a reaction chamber. With glow discharge plasma produced by supplying the high-frequency electric powers with different frequencies, a semiconductor thin film or an insulating thin film is formed. High-frequency electric powers with different frequencies (different wavelengths), which are superimposed on each other, are applied to an electrode in a plasma CVD apparatus, so that increase in plasma density and uniformity for preventing effect of surface standing wave of plasma are attained. | 02-19-2009 |
| 20090093106 | BONDED SOI SUBSTRATE, AND METHOD FOR MANUFACTURING THE SAME - This bonded SOI substrate includes: an SOI layer having a low density impurity layer in which dopants are present at low density and a high density impurity layer in which dopants are present at high density; a wafer for a support substrate which supports said SOI layer; and a buried insulating film, wherein said SOI layer and said wafer for a support substrate are bonded with said buried insulating film therebetween, and gettering sites are formed in said high density impurity layer. | 04-09-2009 |
| 20090111247 | FORMATION METHOD OF SINGLE CRYSTAL SEMICONDUCTOR LAYER, FORMATION METHOD OF CRYSTALLINE SEMICONDUCTOR LAYER, FORMATION METHOD OF POLYCRYSTALLINE LAYER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for forming a single crystal semiconductor layer in which a first porous layer and a second porous layer are formed over a single crystal semiconductor ingot, a groove is formed in a part of the second porous layer and a single crystal semiconductor layer is formed over the second porous layer, the single crystal semiconductor ingot is attached onto a large insulating substrate, water jet is directed to the interface between the first porous layer and the second porous layer, and the single crystal semiconductor layer is attached to the large insulating substrate, or a method for forming a crystalline semiconductor layer in which a crystalline semiconductor ingot is irradiated with hydrogen ions to form a hydrogen ion irradiation region in the crystalline semiconductor ingot, the crystalline semiconductor ingot is rolled over the large insulating substrate while being heated, the crystalline semiconductor layer is separated from the hydrogen ion irradiation region, and the crystalline semiconductor layer is attached to the large insulating substrate. | 04-30-2009 |
| 20090117714 | Method of producing semiconductor device, and substrate processing apparatus - Disclosed is a method of producing a semiconductor device, comprising the steps of carrying a substrate with an insulating film formed on its surface into a processing chamber; processing the substrate to form silicon grains on the insulating film formed on the surface of the substrate by introducing at least a silicon-base gas into the processing chamber; and carrying the processed substrate out of the processing chamber, wherein in the processing step, a silicon-base gas and a dopant gas are introduced into the processing chamber with the temperature and the pressure inside the processing chamber being so controlled that, when the silicon-base gas is introduced singly, the silicon-base gas is not thermally decomposed under the controlled condition, in such a manner that the flow rate of the dopant gas could be equal to or more than the flow rate of the silicon-base gas. | 05-07-2009 |
| 20090137101 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE - To provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like is used. The semiconductor layer is transferred to a supporting substrate by the steps of irradiating a semiconductor wafer with ions from one surface to form a damaged layer; forming an insulating layer over one surface of the semiconductor wafer; attaching one surface of the supporting substrate to the insulating layer formed over the semiconductor wafer and performing heat treatment to bond the supporting substrate to the semiconductor wafer; and performing separation at the damaged layer into the semiconductor wafer and the supporting substrate. The damaged layer remaining partially over the semiconductor layer is removed by wet etching and a surface of the semiconductor layer is irradiated with a laser beam. | 05-28-2009 |
| 20090137102 | METHOD FOR MAKING QUANTUM DOTS - A method for forming at least one quantum dot at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (w | 05-28-2009 |
| 20090137103 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In order to improve the quality of a microcrystalline semiconductor film which is formed at an early stage of deposition, a microcrystalline semiconductor film near an interface with a base insulating film is formed under a deposition condition in which a deposition rate is low but the quality of a film to be formed is high; then, a microcrystalline semiconductor film is further deposited at a deposition rate which is increased stepwise or gradually. The microcrystalline semiconductor film is formed in a reaction chamber which is provided in a deposition chamber with space around the reaction chamber, by a chemical vapor deposition method. Further, a scaling gas is supplied into the space to help place the reaction chamber in an ultrahigh vacuum, whereby the concentration of an impurity in the microcrystalline semiconductor film near the interface with the base insulating film is reduced. | 05-28-2009 |
| 20090142907 | SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides means for making appropriate a preheat condition at a sapphire substrate preheating step and thereby smoothing sucking and holding of a sapphire substrate. The means includes a hot plate for heating up a sapphire substrate in the atmosphere, support portions for supporting the sapphire substrate with a back surface thereof being opposite to the hot plate and a predetermined spacing being defined therebetween, and a jet hole provided in the hot plate and for jetting gas toward a central part of the sapphire substrate. When the sapphire substrate is preheated by the hot plate, a preheat condition for the sapphire substrate is set assuming that the predetermined spacing is 1 mm or less and the jet amount of the gas from the jet hole is 20 L/min or more. An end condition for the preheat is set as the time when the temperature of the central part of the sapphire substrate becomes lower 65° C. or more than that of an outer peripheral edge portion thereof. | 06-04-2009 |
| 20090170292 | Method for producing semiconductor substrate and semiconductor substrate - A production method for a semiconductor substrate for producing a high quality SGOI substrate | 07-02-2009 |
| 20090176352 | Semiconductor device, method of manufacturing the same, and substrate for manufacturing the same - A semiconductor device includes a substrate, a buffer layer that is formed with an aluminum nitride layer on the substrate and has a film thickness of 5 nm to 40 nm, an operating layer that is formed with a gallium nitride-based semiconductor on the buffer layer, and a control electrode that is formed on the operating layer. | 07-09-2009 |
| 20090209092 | SEIMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF - A FinFET and methods for its manufacture are provided. The method of the invention provides an elegant process for manufacturing FinFETs with separated gates. It is compatible with a wide range of dielectric materials and gate electrode materials, providing that the gate electrode material(s) can be deposited conformally. Provision of at least one upstanding structure (or “dummy fin”) ( | 08-20-2009 |
| 20090233423 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - A method for manufacturing a nitride semiconductor substrate including the steps of: forming a nitride semiconductor layer on a sapphire substrate, and manufacturing a freestanding nitride semiconductor substrate by using the nitride semiconductor layer separated from the sapphire substrate, wherein variability of inclinations of the C-axes, being a difference between a maximum value and a minimum value of inclination of the C-axes in a radially-outward direction at each point on a front surface of the sapphire substrate is 0.3° or more and 1° or less. | 09-17-2009 |
| 20090239359 | INTEGRATED PROCESS SYSTEM AND PROCESS SEQUENCE FOR PRODUCTION OF THIN FILM TRANSISTOR ARRAYS USING DOPED OR COMPOUNDED METAL OXIDE SEMICONDUCTOR - The present invention generally relates to an integrated processing system and process sequence that may be used for thin film transistor (TFT) fabrication. In fabricating TFTs, numerous processes may be performed on a substrate to ultimately produce the desired TFT. These processes may be performed in numerous processing chambers that may be coupled to a common transfer chamber. The arrangement of the processing chambers and the sequence in which the substrate may pass through the processing chambers may affect the device performance. By placing specific processing chambers around a common transfer chamber, multiple processes may be performed without undue exposure of the TFT to atmosphere. Alternatively, by passing the substrate sequentially through specific processing chambers, multiple processes may be performed without undue exposure of the TFT to atmosphere. | 09-24-2009 |
| 20090246946 | METHOD OF FABRICATING A MICROELECTRONIC STRUCTURE OF A SEMICONDUCTOR ON INSULATOR TYPE WITH DIFFERENT PATTERNS - A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged. | 10-01-2009 |
| 20090253251 | CRYSTALLINE SEMICONDUCTOR FILM, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique. If the spin rotational acceleration speed is set low during a period moving from a dripping of the catalyst element solution process to a high velocity spin drying process in a catalyst element spin addition step, then it becomes clear that the non-uniformity of the amount of added catalyst element within the substrate is improved. The above stated problems are therefore solved by applying a spin addition process with a low spin rotational acceleration to a method of manufacturing a crystalline semiconductor film. | 10-08-2009 |
| 20090258476 | APPARATUS AND METHODS FOR MANUFACTURING THIN-FILM SOLAR CELLS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web. | 10-15-2009 |
| 20090269910 | METHOD OF FABRICATING PHASE CHANGE MEMORY DEVICE - In a method of fabricating a phase change memory (PCM) device, a substrate having bottom electrodes formed therein is provided. A first dielectric layer having cup-shaped thermal electrodes is formed over the substrate. Second dielectric layers are formed on the substrate. Stacked structures are formed on the substrate. A PC material film is formed over the substrate and covers the stacked structures and the second dielectric layers. The PC material film is anisotropically etched to form PC material spacers on sidewalls of the stacked structures, and each of the PC material spacers physically and electrically contacts each of the cup-shaped thermal electrodes and top electrodes. The PC material spacers include phase change material. The PC material spacers are over-etched to remove the PC material film on the sidewalls of the second dielectric layers. | 10-29-2009 |
| 20090269911 | NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate ( | 10-29-2009 |
| 20090280626 | FINFET STRUCTURE WITH MULTIPLY STRESSED GATE ELECTRODE - A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin. The semiconductor fin may also be aligned over a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to obtain an enhancement of semiconductor device performance. | 11-12-2009 |
| 20090298268 | Method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same - A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and a Si0 | 12-03-2009 |
| 20090298269 | STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME - A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate. | 12-03-2009 |
| 20100022074 | SUBSTRATE RELEASE METHODS AND APPARATUSES - The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety of techniques may be used to fracture and release the mechanically weak porous semiconductor layer without damaging the TFSS substrate layer or the template layer such as pressure variations, thermal stress generation, and mechanical bending. The methods also allow for processing three dimensional features not possible with current separation processes. Optional cleaning and final lift-off steps may be performed as part of the release step or after the release step. | 01-28-2010 |
| 20100029068 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION SYSTEM - A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film. | 02-04-2010 |
| 20100035414 | METHOD FOR PREPARING A GERMANIUM LAYER FROM A SILICON-GERMANIUM-ON-ISOLATOR SUBSTRATE - A method for making a germanium-on-insulator layer from an SGOI substrate, including: a) depositing on the substrate a layer of a metallic element M capable of selectively forming a silicide, the layer being in contact with a silicon-germanium alloy layer; and b) a reaction between the alloy layer and the layer of a metallic element M, by which a stack of M silicide-germanium-insulator layers is obtained. Such a method may, for example, find application to production of electronic devices such as MOSFET transistors. | 02-11-2010 |
| 20100035415 | MANUFACTURING METHOD FOR A NANOCRYSTAL BASED DEVICE COVERED WITH A LAYER OF NITRIDE DEPOSITED BY CVD - The invention relates to a manufacturing method for a structure comprising semi-conductor material nanocrystals on a dielectric material substrate by chemical vapour deposition (CVD), the nanocrystals being covered by a layer of semi-conductor material nitride. The method comprises a step for forming stable nuclei on the substrate by CVD from a first gaseous precursor of the nuclei; a step of nanocrystal growth from stable nuclei by CVD from a second gaseous precursor; and a step for forming a layer of semi-conductor material nitride on the nanocrystals. The method is characterised in that the passivation step is carried out by selective and stoichiometric CVD of semi-conductor material nitride only on the nanocrystals from a mixture of the second and a third gaseous precursor selected to cause selective and stoichiometric deposition of the nitride only on said nanocrystals, wherein steps for forming the nuclei, forming the nanocrystals and passivation are carried out inside a same, single chamber. | 02-11-2010 |
| 20100062585 | METHOD FOR FORMING SILICON THIN FILM - A method for forming a silicon thin film which can form a crystalline silicon thin film relatively at a low temperature, economically and productively is provided. A method for forming a silicon thin film which can provide a substrate for thin film transistor with a lowered leakage current is provided. | 03-11-2010 |
| 20100062586 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a homogeneous semiconductor film in which variation in the size of crystal grains is reduced. Alternatively, it is an object to provide a homogeneous semiconductor film and to achieve cost reduction. By introducing a glass substrate over which an amorphous semiconductor film is formed into a treatment atmosphere set at more than or equal to a temperature that is needed for crystallization, rapid heating due to heat conduction from the treatment atmosphere is performed so that the amorphous semiconductor film is crystallized. More specifically, for example, after the temperature of the treatment atmosphere is increased in advance to a temperature that is needed for crystallization, the substrate over which the semiconductor film is formed is put into the treatment atmosphere. | 03-11-2010 |
| 20100062587 | METHOD TO MANUFACTURE SILICON QUANTUM ISLANDS AND SINGLE-ELECTRON DEVICES - A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned region offset by a non-selected region. The method also includes forming at least one quantum island from the thinned region by subjecting the thinned region to an annealing process. The non-selected region is aligned with the quantum island and tunnel junctions are formed between the quantum island and the non-selected region. The present invention also includes a single-electron device, and a method of manufacturing an integrated circuit that includes a single-electron device. | 03-11-2010 |
| 20100068869 | METHOD FOR FABRICATING A MICRO-ELECTRONIC DEVICE EQUIPPED WITH SEMI-CONDUCTOR ZONES ON AN INSULATOR WITH A HORIZONTAL GE CONCENTRATION GRADIENT - A method for the realization of a microelectronic device which includes at least one semi-conductor zone which rests on a support and which exhibits a Germanium concentration gradient in a direction parallel to the principal plane of the support,
| 03-18-2010 |
| 20100081262 | METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP). | 04-01-2010 |
| 20100081263 | Methods of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes forming a phase change material pattern on a top surface of an insulating layer including an opening and in the opening, and forming a compressive layer compressing the phase change material pattern on the phase change material pattern. | 04-01-2010 |
| 20100093157 | METHOD FOR PRODUCING GROUP III NITRIDE-BASED COMPOUND SEMICONDUCTOR CRYSTAL - A GaN single crystal | 04-15-2010 |
| 20100112790 | METHOD OF MANUFACTURING SEMICONDUCTOR THIN FILM AND SEMICONDUCTOR DEVICE - On a translucent substrate, an insulating film having a refractive index n and an amorphous silicon film are deposited successively. By irradiating the amorphous silicon film with a laser beam having a beam shape of a band shape extending along a length direction with a wavelength λ, a plurality of times from a side of amorphous silicon film facing the insulating film, while an irradiation position of the laser beam is shifted each of the plurality of times in a width direction of the band shape by a distance smaller than a width dimension of the band shape, a polycrystalline silicon film is formed from the amorphous silicon film. Forming the polycrystalline silicon film forms crystal grain boundaries which extend in the width direction and are disposed at a mean spacing measured along the length direction and ranging from (λ/n)×0.95 to (λ/n)×1.05 inclusive, and crystal grain boundaries which, in a region between crystal grain boundaries adjacent to each other and extending in the width direction, extend in the length direction and are disposed at a mean spacing measured along the width direction and ranging from (λ/n)×0.95 to (λ/n)×1.05 inclusive. | 05-06-2010 |
| 20100112791 | METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE - A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer. | 05-06-2010 |
| 20100129993 | METHOD FOR MANUFACTURING SOI WAFER - The present invention provides a method for manufacturing an SOI wafer wherein an HCl gas is mixed in a reactive gas at a step of forming a silicon epitaxial layer on an entire surface of an SOI layer of the SOI wafer having an oxide film on a terrace portion. As a result, it is possible to provide the method for manufacturing an SOI wafer that can easily grow the silicon epitaxial layer on the SOI layer of the SOI wafer having the oxide film on the terrace portion, suppress warpage of the SOI wafer to be manufactured, reduce generation of particles even at subsequent steps, e.g., device manufacture, and decrease a cost for manufacturing such an SOI wafer. | 05-27-2010 |
| 20100151663 | MANUFACTURING METHOD OF SOI SUBSTRATE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate. | 06-17-2010 |
| 20100151664 | Method of Manufacturing a Semiconductor Device - At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber. | 06-17-2010 |
| 20100178755 | Method of fabricating nonvolatile memory device - A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively. | 07-15-2010 |
| 20100184274 | METHOD FOR MANUFACTURING A TRANSISTOR WITH PARALLEL SEMICONDUCTOR NANOFINGERS - A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material. | 07-22-2010 |
| 20100203712 | PROCESS FOR FORMING A WIRE PORTION IN AN INTEGRATED ELECTRONIC CIRCUIT - A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion ( | 08-12-2010 |
| 20100273317 | METHOD OF GROWING, ON A DIELETRIC MATERIAL, NANOWIRES MADE OF SEMI-CONDUCTOR MATERIALS CONNECTING TWO ELECTRODES - Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material. | 10-28-2010 |
| 20100273318 | SUBSTRATE PRETREATMENT FOR SUBSEQUENT HIGH TEMPERATURE GROUP III DEPOSITIONS - Embodiments of the present invention relate to apparatus and method for pretreatment of substrates for manufacturing devices such as light emitting diodes (LEDs) or laser diodes (LDs). One embodiment of the present invention comprises pre-treating the aluminum oxide containing substrate by exposing a surface of the aluminum oxide containing substrate to a pretreatment gas mixture, wherein the pretreatment gas mixture comprises ammonia (NH | 10-28-2010 |
| 20100273319 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device includes: forming a first and second layers not firmly adhering to each other over a substrate; forming a first semiconductor element layer and a first insulating layer over the second layer; forming a hole reaching the first layer in the first insulating layer; oxidizing the first layer exposed at a bottom of the hole; forming a wiring electrically connected to the first semiconductor element layer over the first insulating layer and in the hole; and separating the first layer and the substrate from the second layer and the first semiconductor element layer and expose the wiring. Further, another method includes providing an anisotropic conductive adhesive between a second semiconductor element layer separated through a manufacturing process similar to the above and the wiring, whereby the first and second semiconductor element layers are electrically connected through the anisotropic conductive adhesive and the wiring. | 10-28-2010 |
| 20100323501 | PLASMA TREATMENT APPARATUS, METHOD FOR FORMING FILM, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A structure of the plasma treatment apparatus is employed in which an upper electrode has projected portions provided with first introduction holes and recessed portions provided with second introduction holes, the first introduction hole of the upper electrode is connected to a first cylinder filled with a gas which is not likely to be dissociated, the second introduction hole is connected to a second cylinder filled with a gas which is likely to be dissociated, the gas which is not likely to be dissociated is introduced into a reaction chamber from an introduction port of the first introduction hole provided on a surface of the projected portion of the upper electrode, and the gas which is likely to be dissociated is introduced into the reaction chamber from an introduction port of the second introduction hole provided on a surface of the recessed portion. | 12-23-2010 |
| 20100330782 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region. | 12-30-2010 |
| 20100330783 | ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE - A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys. | 12-30-2010 |
| 20110014780 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10 | 01-20-2011 |
| 20110021006 | METHOD FOR RELEASING A THIN SEMICONDUCTOR SUBSTRATE FROM A REUSABLE TEMPLATE - The present disclosure relates to methods and apparatuses for releasing a thin semiconductor substrate from a reusable template. The method involves forming a mechanically weak layer conformally on a semiconductor template. Then forming a thin semiconductor substrate conformally on the mechanically weak layer. The thin semiconductor substrate, the mechanically weak layer and the template forming a wafer. Then defining the border of the thin-film semiconductor substrate to be released by exposing the peripheral of the mechanically weak layer. Then releasing the thin-film semiconductor substrate by applying a controlled air flow parallel to said mechanically weak layer wherein the controlled air flow separates the thin semiconductor substrate and template according to lifting forces. | 01-27-2011 |
| 20110039401 | Apparatus and Method for Depositing a Material on a Substrate - Apparatus and a method for depositing a material on a substrate utilizes a distributor including a permeable member through which a carrier gas and a material are passed to provide a vapor that is deposited on a conveyed substrate. A secondary gas can be provided to promote uniform distribution of the material on the substrate. | 02-17-2011 |
| 20110045661 | METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FOR SEMICONDUCTOR INTEGRATED CIRCUITS - A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. In a specific embodiment, the present invention includes providing a semiconductor substrate including a surface region. The method includes forming an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region according to a specific embodiment. The method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers. | 02-24-2011 |
| 20110053353 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed. | 03-03-2011 |
| 20110059598 | METHOD FOR STABILIZING GERMANIUM NANOWIRES OBTAINED BY CONDENSATION - The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated. | 03-10-2011 |
| 20110092056 | ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT - Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate. | 04-21-2011 |
| 20110111579 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer. | 05-12-2011 |
| 20110117730 | Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers - A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars. | 05-19-2011 |
| 20110124183 | METHOD FOR MANUFACTURING FLEXIBLE SEMICONDUCTOR SUBSTRATE - A production method for a flexible semiconductor substrate according to the present invention includes: a step of providing an inorganic substrate | 05-26-2011 |
| 20110136326 | PILLAR DEVICES AND METHODS OF MAKING THEREOF - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 06-09-2011 |
| 20110143524 | Methods of Manufacturing Rewriteable Three-Dimensional Semiconductor Memory Devices - Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer. | 06-16-2011 |
| 20110159668 | Methods For Processing Silicon On Insulator Wafers - Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited. | 06-30-2011 |
| 20110201182 | NONVOLATIVE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME - A method of making a uniform nanoparticle array, including performing diblock copolymer thin film self assembly over a first dielectric on silicon, creating a porous polymer film, transferring a pattern into the first dielectric, selectively growing epitaxial silicon off a silicon substrate from within pores to create a silicon nanoparticle array. | 08-18-2011 |
| 20110207300 | ELECTRONIC DEVICES - A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region. | 08-25-2011 |
| 20110223746 | Method for Fabrication of III-Nitride Heterojunction Semiconductor Device - A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content. | 09-15-2011 |
| 20110244667 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a nitride semiconductor layer having high-precision thickness is provided. The method includes steps of: forming a gallium nitride (GaN) layer whose main face is a +c face on a substrate; forming a trench by selectively etching down a partial region in the +c face of the GaN layer; forming a metal layer so as to bury the trench; and separating the substrate and the GaN layer, after that, polishing a −c face of the GaN layer until the metal layer is exposed, and removing a part in a thickness direction of the GaN layer. | 10-06-2011 |
| 20110244668 | Semiconductor device and manufacturing process therefor - A process for manufacturing a semiconductor device, in which a current flows in a deflected part that includes a semiconductor, includes forming a straight beam having a doubly-clamped beam structure that includes the semiconductor by forming a void under the beam, filling the void with a liquid, and contacting a center of the beam with a bottom of the void by drying the liquid to form the deflected part. | 10-06-2011 |
| 20110263104 | THIN BODY SEMICONDUCTOR DEVICES - A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented. | 10-27-2011 |
| 20110269300 | Integrated Assist Features for Epitaxial Growth - A method for making a semiconductor device is provided which comprises (a) creating a data set ( | 11-03-2011 |
| 20110300693 | Semiconductor Devices - Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern. | 12-08-2011 |
| 20110318907 | COMPOSITION FOR FORMING GATE INSULATING FILM FOR THIN-FILM TRANSISTOR - There is provided a novel composition for forming a gate insulating film taking into consideration also electrical characteristics after other processes such as wiring by irradiation with an ultraviolet ray and the like during the production of an organic transistor using a gate insulating film. A composition for forming a gate insulating film for a thin-film transistor comprising: a component (i): an oligomer compound or a polymer compound containing a repeating unit having a structure in which a nitrogen atom of a triazine-trione ring is bonded to a nitrogen atom of another triazine-trione ring through a hydroxyalkylene group; and a component (ii): a compound having two or more blocked isocyanate groups in one molecule thereof. | 12-29-2011 |
| 20120003824 | METHOD FOR MANUFACTURING GALLIUM NITRIDE WAFER - A method for manufacturing a gallium nitride (GaN) wafer is provided. In the method for manufacturing the GaN wafer according to an embodiment, an etch stop layer is formed on a substrate, and a first GaN layer is formed on the etch stop layer. A portion of the first GaN layer is etched with a silane gas, and a second GaN layer is formed on the etched first GaN layer. A third GaN layer is formed on the second GaN layer. | 01-05-2012 |
| 20120009766 | STRAINED SEMICONDUCTOR-ON-INSULATOR BY ADDITION AND REMOVAL OF ATOMS IN A SEMICONDUCTOR-ON-INSULATOR - A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate. | 01-12-2012 |
| 20120009767 | METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING METALLIZATION COMPRISING SELECT LINES, BIT LINES AND WORD LINES - A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region. | 01-12-2012 |
| 20120009768 | METHOD FOR FORMING SAPPHIRE SUBSTRATE AND SEMICONDUCTOR DEVICE - In a semiconductor device fabricated by growing a compound semiconductor layer on a sapphire substrate, a sapphire substrate enabling the semiconductor device to have a high light-extraction efficiency is provided. | 01-12-2012 |
| 20120015505 | METHOD AND DEVICE FOR PREPARING COMPOUND SEMICONDUCTOR FILM - The present invention discloses a method and a device for preparing a compound semiconductor film. The method comprises the steps of: providing a substrate above at least an evaporation source in a vacuum condition; heating a source material contained in the evaporation source so that the source material is vapor-deposited on the substrate; and taking out the substrate under protection of an inert gas. The substrate may be rotated around an axis of a plane where the evaporation source is positioned, and the substrate is tilted by a predetermined angle with respect to the plane. The compound semi-conductive film thus prepared has a uniform thickness with a larger area. The method provides a simplified process and enhanced efficiency. | 01-19-2012 |
| 20120028449 | METHOD AND INSTALLATION FOR PRODUCING AN ANTI- REFLECTION AND/OR PASSIVATION COATING FOR SEMICONDUCTOR DEVICES - A method of producing an anti-reflection and/or passivation coating for semiconductor devices is provided. The method includes: providing a semiconductor device precursor | 02-02-2012 |
| 20120028450 | VERTICAL-TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated. | 02-02-2012 |
| 20120034764 | SYSTEM AND METHOD FOR FABRICATING THIN-FILM PHOTOVOLTAIC DEVICES - Described are an apparatus and a method for depositing a thin film on a web. The method includes depositing a first layer of a composite metal onto a web. A first selenium layer is deposited onto the first layer and the web is heated to selenize the first layer. Subsequently, a second layer of the composite metal is deposited onto the selenized first layer and a second selenium layer is deposited onto the second layer. The web is then heated to selenize the second layer. The composition of each composite metal layer can be varied to achieve desired bandgap gradients and other film properties. Segregation of gallium and indium is substantially reduced or eliminated because each incremental layer is selenized before the next incremental layer is deposited. The method can be implemented in production systems to deposit CIGS films on metal and plastic foils. | 02-09-2012 |
| 20120058629 | METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves. | 03-08-2012 |
| 20120064700 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR SUBSTRATE - A semiconductor substrate of the present invention is made of nitrides of group III metals having wurtzite crystal structure and is grown in vapor phase either on a (0001) oriented foreign substrate ( | 03-15-2012 |
| 20120064701 | CRYSTALLINE SEMICONDUCTOR FILM MANUFACTURING METHOD AND CRYSTALLINE SEMICONDUCTOR FILM MANUFACTURING APPARATUS - A semiconductor film manufacturing method includes: forming a metal layer above the substrate; forming a gate electrode in each of pixels by patterning a metal layer; forming a gate insulating firm on the gate electrode; forming an amorphous semiconductor film on the gate insulating film; and crystallizing the amorphous semiconductor film by irradiating the amorphous semiconductor film with a laser beam, and a laser irradiation width of the laser beam corresponds to n times a width of each pixel (n is an integer of 2 or above), a laser energy intensity is higher in one end portion of the laser irradiation width than in the other end portion, and in the crystallizing, the laser energy intensity of the laser beam is inverted in increments of n pixels, alternately between one of the end portions of the laser irradiation width of the laser beam and the other end portion. | 03-15-2012 |
| 20120064702 | METHOD OF FABRICATING POLYCRYSTALLINE SILICON THIN FILM - A method of fabricating a polycrystalline silicon thin that includes a metal layer forming operation of forming a metal layer on an insulating substrate, a first silicon layer forming operation of stacking a silicon layer on the metal layer formed in the metal layer forming operation, a first annealing operation of forming a silicide layer using by moving catalyst metal atoms from the metal layer to the silicon layer using an annealing process, a second silicon layer forming operation of stacking an amorphous silicon layer on the silicide layer, and a crystallization operation of crystallizing the amorphous silicon layer into crystalline silicon through the medium of particles of the silicide layer. | 03-15-2012 |
| 20120070966 | METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor element includes etching a surface of a substrate by a dry etching processing, performing a first heat treatment for the surface of the substrate in an atmosphere including halogen, and forming a nitride semiconductor on the surface of the substrate. | 03-22-2012 |
| 20120070967 | Method for Forming Gallium Nitride Devices with Conductive Regions - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 03-22-2012 |
| 20120088355 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: a first monocrystalline layer comprising semiconductor regions, overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer comprising semiconductor regions overlying the isolation layer; and etching portions of the first monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer. | 04-12-2012 |
| 20120108037 | METHODS OF FORMING A PHASE CHANGE MATERIAL - A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed. | 05-03-2012 |
| 20120115314 | PLASMA PROCESSING APPARATUS AND METHOD OF PRODUCING AMORPHOUS SILICON THIN FILM USING SAME - Disclosed is a plasma processing apparatus, wherein a plasma-generating electrode has a plurality of gas exhaust holes which run through the plasma-generating electrode from the surface facing a substrate held by a substrate-holding mechanism, and reach a gas exhaust chamber; gas-feeding pipes, provided connected to a gas-introducing pipe, have gas-feeding ports for discharging source gas toward the inside of the plurality of gas exhaust holes; and the gas-feeding pipes and the gas-feeding ports are arranged in a manner such that extended lines, representing the direction of the flow of the source gas discharged from the gas-feeding ports, intersect the end surface open regions at the interface of the gas exhaust chamber to the gas exhaust holes. Also disclosed is a method of producing the amorphous silicon thin film using the plasma processing apparatus. | 05-10-2012 |
| 20120122303 | SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS - Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material. | 05-17-2012 |
| 20120178246 | PRODUCING TRANSISTOR INCLUDING MULTIPLE REENTRANT PROFILES - A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer. | 07-12-2012 |
| 20120178247 | PRODUCING TRANSISTOR INCLUDING MULTI-LAYER REENTRANT PROFILE - A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer, a second electrically conductive material layer, and a third electrically conductive material layer. A resist material layer is deposited over the third electrically conductive material layer. The resist material layer is patterned to expose a portion of the third electrically conductive material layer. Some of the third electrically conductive material layer is removed to expose a portion of the second electrically conductive material layer. The third electrically conductive material layer is caused to overhang the second electrically conductive material layer by removing some of the second electrically conductive material layer. Some of the first electrically conductive material layer is removed. | 07-12-2012 |
| 20120178248 | METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making an epitaxial structure is provided. The method includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. An epitaxial layer is epitaxially grown on the buffer layer. The substrate and the carbon nanotube layer are removed. | 07-12-2012 |
| 20120178249 | MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced. | 07-12-2012 |
| 20120190178 | POLYSILICON FILMS BY HDP-CVD - Methods of forming polysilicon layers are described. The methods include forming a high-density plasma from a silicon precursor in a substrate processing region containing the deposition substrate. The described methods produce polycrystalline films at reduced substrate temperature (e.g. <500° C.) relative to prior art techniques. The availability of a bias plasma power adjustment further enables adjustment of conformality of the formed polysilicon layer. When dopants are included in the high density plasma, they may be incorporated into the polysilicon layer in such a way that they do not require a separate activation step. | 07-26-2012 |
| 20120190179 | METHODS OF MANUFACTURING FINFET DEVICES - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 07-26-2012 |
| 20120225543 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for manufacturing a highly reliable semiconductor device with less change in threshold voltage is provided. An insulating film from which oxygen can be released by heating is formed in contact with an oxide semiconductor layer, and light irradiation treatment is performed on a gate electrode or a metal layer formed in a region which overlaps with the gate electrode, so that oxygen is added into the oxide semiconductor layer in a region which overlaps with the gate electrode. Accordingly, oxygen vacancies or interface states in the oxide semiconductor layer in a region which overlaps with the gate electrode can be reduced. | 09-06-2012 |
| 20120231613 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 09-13-2012 |
| 20120238081 | Printed Material Constrained By Well Structures And Devices Including Same - A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor. | 09-20-2012 |
| 20120238082 | NANO-WIRE FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE TRANSISTOR, AND INTEGRATED CIRCUIT INCLUDING THE TRANSISTOR - A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation. | 09-20-2012 |
| 20120244687 | METHOD OF MANUFACTURING A BASE SUBSTRATE FOR A SEMI-CONDUCTOR ON INSULATOR TYPE SUBSTRATE - A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure. | 09-27-2012 |
| 20120252193 | DOUBLE AND TRIPLE GATE MOSFET DEVICES AND METHODS FOR MAKING SAME - A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate. | 10-04-2012 |
| 20120258583 | METHOD FOR EPITAXIAL LAYER OVERGROWTH - Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing. | 10-11-2012 |
| 20120258584 | GLASS SUBSTRATE COMPRISING AN EDGE WEB PORTION - A glass ribbon coated with a flexible material, the flexible coating forming a flexible web portion that extends from an edge of the glass ribbon at least one millimeter. The flexible web portion can be used to facilitate handling of the glass ribbon in a manufacturing process, and may include registration markings, or perforations, that further facilitate precise positioning of the ribbon. | 10-11-2012 |
| 20120264277 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING NANOCRYSTAL - A method is provided for forming a semiconductor device having nanocrystals. The method includes: providing a substrate; forming a first insulating layer over a surface of the substrate; forming a first plurality of nanocrystals on the first insulating layer; forming a second insulating layer over the first plurality of nanocrystals; implanting a first material into the second insulating layer; and annealing the first material to form a second plurality of nanocrystals in the second insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density. | 10-18-2012 |
| 20120270383 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND PLASMA OXIDATION TREATMENT METHOD - Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b≧2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively. | 10-25-2012 |
| 20120282762 | Method For Forming Gallium Nitride Semiconductor Device With Improved Forward Conduction - A method for forming a gallium nitride based semiconductor diode includes forming Schottky contacts on the upper surface of mesas formed in a semiconductor body formed on a substrate. Ohmic contacts are formed on the lower surface of the semiconductor body. In one embodiment, an insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and ohmic contacts to form the anode and cathode electrodes. In another embodiment, vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the ohmic contacts. An anode electrode is formed in electrical contact with the Schottky contacts. A cathode electrode is formed in electrical contact with the ohmic contacts on the backside of the substrate. | 11-08-2012 |
| 20120295423 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 11-22-2012 |
| 20120295424 | METHOD FOR DESIGNING SOI WAFER AND METHOD FOR MANUFACTURING SOI WAFER - A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength λ comprises: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength λ of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation. | 11-22-2012 |
| 20120302046 | ELECTRONIC CIRCUIT STRUCTURE AND METHOD FOR FORMING SAME - A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods. | 11-29-2012 |
| 20130005122 | METHOD FOR FINISHING A SUBSTRATE OF THE SEMICONDUCTOR-ON-INSULATOR TYPE - The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises:
| 01-03-2013 |
| 20130012006 | PLASMA TREATMENT APPARATUS, METHOD FOR FORMING FILM, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A structure of the plasma treatment apparatus is employed in which an upper electrode has projected portions provided with first introduction holes and recessed portions provided with second introduction holes, the first introduction hole of the upper electrode is connected to a first cylinder filled with a gas which is not likely to be dissociated, the second introduction hole is connected to a second cylinder filled with a gas which is likely to be dissociated, the gas which is not likely to be dissociated is introduced into a reaction chamber from an introduction port of the first introduction hole provided on a surface of the projected portion of the upper electrode, and the gas which is likely to be dissociated is introduced into the reaction chamber from an introduction port of the second introduction hole provided on a surface of the recessed portion. | 01-10-2013 |
| 20130017673 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls. | 01-17-2013 |
| 20130029478 | METHOD OF FABRICATING HIGH-MOBILITY DUAL CHANNEL MATERIAL BASED ON SOI SUBSTRATE - The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation. | 01-31-2013 |
| 20130029479 | ARRANGEMENT, SYSTEM, AND METHOD FOR PROCESSING MULTILAYER BODIES - The invention relates to a multilayer body arrangement, which comprises at least two multilayer bodies each having at least one surface to be processed as well as at least one device for positioning the multilayer bodies, wherein the device is configured such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs. It further relates to a system for processing multilayer bodies with such a multilayer body arrangement, as well as a method for processing multilayer bodies, wherein the multilayer bodies are disposed such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs. | 01-31-2013 |
| 20130059431 | DEVICE AND METHOD FOR SUBSTRATE PROCESSING - The present invention relates to a device for processing substrates in a processing system with at least one process tool disposed in at least one process area, which tool has two substrate levels disposed opposite each other in the process area, which are aligned at least approximately vertical, wherein the device is adapted to process at least two substrates at the same time in the process area by means of the process tool, wherein the substrates can be disposed in the substrate levels such that coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates. It further relates to a method for processing coated substrates in a processing system, wherein the substrates have coatings and the substrates are each disposed opposite each other such that the coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates. | 03-07-2013 |
| 20130065381 | VERTICAL-TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated. | 03-14-2013 |
| 20130072003 | SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE - Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier. | 03-21-2013 |
| 20130084692 | PRODUCING VERTICAL TRANSISTOR HAVING REDUCED PARASITIC CAPACITANCE - A method of producing a transistor includes providing a substrate including an electrically conductive material layer stack positioned on the substrate. A first electrically insulating material layer is deposited so that the first electrically insulating material layer contacts a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally deposited so that the second electrically insulating material contacts the first electrically insulating layer, and contacts a second portion of the electrically conductive material layer stack, and contacts at least a portion of the substrate. | 04-04-2013 |
| 20130089973 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method of manufacturing a nitride semiconductor device includes the step of forming a second nitride semiconductor layer having an inclined facet by metal-organic chemical vapor deposition, in which a molar flow ratio of a group V element gas to a group III element gas that are supplied to a growth chamber of a metal-organic chemical vapor deposition growth apparatus is set at 240 or less. | 04-11-2013 |
| 20130130478 | Non-Volatile Memory Device And Method Of Manufacturing The Same - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers. | 05-23-2013 |
| 20130130479 | Semiconductor-on-Insulator with Back Side Body Connection - Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region. | 05-23-2013 |
| 20130130480 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device having a multilayer structure. The method for manufacturing a semiconductor device according to the present invention comprises the loading of a substrate into the chamber of a chemical vapor deposition apparatus and the forming of a multilayer structure in which a plurality of doped amorphous silicon layers and a plurality of insulation layers are alternately stacked. Said layers are stacked by alternately and repetitively forming the doped amorphous silicon layer on the substrate by supplying a conductive dopant and silicon precursor into the chamber where the substrate is loaded, and forming the insulation layer containing silicon on the substrate by introducing the silicon precursor and a reaction gas into the chamber where the substrate is loaded. | 05-23-2013 |
| 20130143394 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING - A method of forming a semiconductor substrate including forming a base layer of a Group 13-15 material on a growth substrate during a growth process, forming a mask having mask regions and gap regions overlying the base layer during the growth process, and preferentially removing a portion of the base layer underlying the mask during the growth process. | 06-06-2013 |
| 20130149847 | METHOD OF MANUFACTURING GaN-BASED FILM AND COMPOSITE SUBSTRATE USED THEREFOR - The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate including a support substrate dissoluble in hydrofluoric acid and a single crystal film arranged on a side of a main surface of the support substrate, a coefficient of thermal expansion in the main surface of the support substrate being more than 0.8 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal, forming a GaN-based film on a main surface of the single crystal film arranged on the side of the main surface of the support substrate, and removing the support substrate by dissolving the support substrate in hydrofluoric acid. Thus, the method of manufacturing a GaN-based film capable of efficiently obtaining a GaN-based film having a large main surface area, less warpage, and good crystallinity, as well as a composite substrate used therefor are provided. | 06-13-2013 |
| 20130157446 | SUBSTRATE SHEET - The invention provides a method for producing a flexible barrier sheet ( | 06-20-2013 |
| 20130164920 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction. | 06-27-2013 |
| 20130171807 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING DUAL TRANSISTORS - Provided are a semiconductor device having dual transistors, and methods of fabricating a semiconductor device, including sequentially forming an insulating layer and a polysilicon layer on a substrate having a first region and a second region, forming a first mask to cover the polysilicon layer on the second region, injecting at least one n-type impurity into the polysilicon layer on the first region to form an N-region, injecting nitrogen into the N-region, forming a second mask to cover the N-region, and injecting at least one p-type impurity into the polysilicon layer on the second region to form a P-region. | 07-04-2013 |
| 20130189831 | SILICON/GERMANIUM NANOPARTICLE INKS AND METHODS OF FORMING INKS WITH DESIRED PRINTING PROPERTIES - Improved silicon/germanium nanoparticle inks are described that have silicon/germanium nanoparticles well distributed within a stable dispersion. In particular the inks are formulated with a centrifugation step to remove contaminants as well as less well dispersed portions of the dispersion. A sonication step can be used after the centrifugation, which is observed to result in a synergistic improvement to the quality of some of the inks. The silicon/germanium ink properties can be engineered for particular deposition applications, such as spin coating or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon/germanium nanoparticles. The silicon/germanium nanoparticles are well suited for forming semiconductor components, such as components for thin film transistors or solar cell contacts. | 07-25-2013 |
| 20130196487 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR CRYSTAL LAYER - According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness. | 08-01-2013 |
| 20130217214 | Closed-Space Annealing Process for Production of CIGS Thin-Films - In one embodiment, a method includes depositing a CIGS precursor layer onto a substrate, introducing a source-material layer into proximity with the precursor layer, where the source-material layer includes one or more of Cu, In, or Ga, and one or more of S or Se, and annealing the precursor layer in proximity with of the source-material layer, where the annealing is performed in a constrained volume, and where the presence of the source-material layer reduces decomposition of volatile species from the precursor layer during annealing. | 08-22-2013 |
| 20130224935 | OPTICAL INPUT/OUTPUT DEVICE FOR PHOTO-ELECTRIC INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING SAME - A photo-electric integrated circuit device comprises an on-die optical input/output device. The on-die optical input/output device comprises a substrate having a trench, a lower cladding layer disposed in the trench and having an upper surface lower than an upper surface of the substrate, and a core disposed on the lower cladding layer at a distance from sidewalls of the trench and having an upper surface at substantially the same level as the upper surface of the substrate. | 08-29-2013 |
| 20130237038 | TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH - A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield. | 09-12-2013 |
| 20130237039 | TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH - A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield. | 09-12-2013 |
| 20130237040 | RESIN COMPOSITION, LAMINATE AND PROCESS FOR PRODUCTION THEREOF, STRUCTURE AND PROCESS FOR PRODUCTION THEREOF, AND PROCESS FOR PRODUCTION OF ELECTRONIC DEVICE - The present invention relates to a resin composition containing: a polyimide silicone which has, in a silicone moiety therein, a crosslinking site at which a crosslinking reaction occurs upon heating at a second temperature, in which the crosslinking reaction proceeds by heating a third temperature that exceeds the second temperature further than the second temperature; and a solvent which vaporizes upon heating at a first temperature that is lower than the second temperature. | 09-12-2013 |
| 20130273723 | GRAPHENE LAYER FORMATION AT LOW SUBSTRATE TEMPERATURE ON A METAL AND CARBON BASED SUBSTRATE - A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source. | 10-17-2013 |
| 20130280893 | METHOD FOR PRODUCTION OF SELECTIVE GROWTH MASKS USING IMPRINT LITHOGRAPHY - The present invention discloses a method for production of selective growth masks using imprint lithography. The method includes steps of: providing a sapphire substrate, forming a GaN layer, an insulation layer, and a photo-resistive layer, performing imprint lithography, performing exposure and development, performing dry etching, and removing the remained photo-resistive layer. The selective growth masks produced by the method of the present invention make the growth of nanowires cylindrical and perpendicular to the GaN layer, and each nanowire is parallel to one another. | 10-24-2013 |
| 20130280894 | METHOD FOR PRODUCTION OF SELECTIVE GROWTH MASKS USING UNDERFILL DISPENSING AND SINTERING - The present invention discloses a method for production of selective growth masks using underfill dispensing and sintering. The method includes steps of: providing a sapphire substrate, growing a gallium nitride base layer on the sapphire substrate, coating a photoresist layer, performing imprint lithography, exposure and development, performing underfill dispensing, and performing sintering. The production method of the present invention can be applied in the atmosphere, and vacuum chambers as known production approaches are unnecessary. The selective growth masks produced by the method of the present invention make the growth of nanowires cylindrical and perpendicular to the gallium nitride base layer, and each nanowire is parallel to one another. | 10-24-2013 |
| 20130309849 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole. | 11-21-2013 |
| 20130323912 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like. | 12-05-2013 |
| 20130323913 | DICHALCOGENOBENZODIPYRROLE COMPOUND - A dichalcogenobenzodipyrrole compound represented by the formula (1): | 12-05-2013 |
| 20130330914 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to provide a thin film transistor having favorable electric characteristics and high reliability and a semiconductor device which includes the thin film transistor as a switching element. An In—Ga—Zn—O-based film having an incubation state that shows an electron diffraction pattern, which is different from a conventionally known amorphous state where a halo shape pattern appears and from a conventionally known crystal state where a spot appears clearly, is formed. The In—Ga—Zn—O-based film having an incubation state is used for a channel formation region of a channel etched thin film transistor. | 12-12-2013 |
| 20130337639 | Method for Substrate Pretreatment To Achieve High-Quality III-Nitride Epitaxy - The present invention relates to a method for producing a modified surface of a substrate that stimulates the growth of epitaxial layers of group-III nitride semiconductors with substantially improved structural perfection and surface flatness. The modification is conducted outside or inside a growth reactor by exposing the substrate to a gas-product of the reaction between hydrogen chloride (HCl) and aluminum metal (Al). As a single-step or an essential part of the multi-step pretreatment procedure, the modification gains in coherent coordination between the substrate and group-III nitride epitaxial structure to be deposited. Along with epilayer, total epitaxial structure may include buffer inter-layer to accomplish precise substrate-epilayer coordination. While this modification is a powerful tool to make high-quality group-III nitride epitaxial layers attainable even on foreign substrates having polar, semipolar and nonpolar orientation, it remains gentle enough to keep the surface of the epilayer extremely smooth. Various embodiments are disclosed. | 12-19-2013 |
| 20140004687 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE | 01-02-2014 |
| 20140030876 | METHODS FOR FABRICATING HIGH CARRIER MOBILITY FINFET STRUCTURES - A method for fabricating an integrated circuit having a FinFET structure includes providing a semiconductor substrate comprising silicon and a high carrier mobility material, forming one or more fin structures on the semiconductor substrate, and subjecting the substrate to a condensation process for the condensation of the high carrier mobility material. The condensation process results in the formation of condensed fin structures formed substantially entirely of the high carrier mobility material and a layer of silicon oxide formed over the condensed fin structures. The method further includes removing the silicon oxide formed over the condensed fin structures so as to expose the condensed fin structures. | 01-30-2014 |
| 20140030877 | PROCESS TO DISSOLVE THE OXIDE LAYER IN THE PERIPHERAL RING OF A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - A process for avoiding formation of a Si—SiO | 01-30-2014 |
| 20140057418 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention discloses a method for manufacturing a high mobility material layer, comprising: forming a plurality of precursors in/on a substrate; and performing a pulse laser processing such that the plurality of precursors react with each other to produce a high mobility material layer. Furthermore, the present invention also provides a method for manufacturing a semiconductor device, comprising: forming a buffer layer on an insulating substrate; forming a first high mobility material layer on the buffer layer using the method for manufacturing the high mobility material layer; forming a second high mobility material layer on the first high mobility material layer using the method for manufacturing the high mobility material layer; and forming trench isolations and defining active regions in the first and second high mobility material layers. | 02-27-2014 |
| 20140065802 | TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES - Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided. | 03-06-2014 |
| 20140065803 | PATTERNED THIN FILM DIELECTRIC STACK FORMATION - A method of producing an inorganic multi-layered thin film structure includes providing a substrate. A patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. A second inorganic thin film material layer is selectively deposited on the region of the substrate where the thin film deposition inhibiting material layer is not present using an atomic layer deposition process. | 03-06-2014 |
| 20140127889 | SYSTEM AND METHOD FOR DEPOSITING A MATERIAL ON A SUBSTRATE - A method and apparatus for depositing a film on a substrate includes introducing a material and a carrier gas into a heated chamber. The material may be a semiconductor material, such as a cadmium chalcogenide. A resulting mixture of vapor and carrier gas containing no unvaporized material is provided. The mixture of vapor and carrier gas are remixed to achieve a uniform vapor/carrier gas composition, which is directed toward a surface of a substrate, such as a glass substrate, where the vapor is deposited as a uniform film. | 05-08-2014 |
| 20140141600 | METHODS OF PREPARING GRAPHENE AND DEVICE INCLUDING GRAPHENE - A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film. | 05-22-2014 |
| 20140141601 | METHODS OF GROWING HETEROEPITAXIAL SINGLE CRYSTAL OR LARGE GRAINED SEMICONDUCTOR FILMS AND DEVICES THEREON - A method is provided for producing field effect transistors (FETs) for display applications. The method involves low temperature deposition of semiconductor films on inexpensive substrates such as ordinary soda-lime glass or borosilicate glass. | 05-22-2014 |
| 20140147995 | METHOD FOR PRODUCING P-TYPE NITRIDE SEMICONDUCTOR LAYER - A method of manufacturing a p type nitride semiconductor layer doped with carbon in a highly reproducible manner with an increased productivity is provided. The method includes supplying an III-group material gas for a predetermined time period T | 05-29-2014 |
| 20140170839 | METHODS OF FORMING FINS FOR A FINFET DEVICE WHEREIN THE FINS HAVE A HIGH GERMANIUM CONTENT - One illustrative method disclosed herein includes forming a silicon/germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration. | 06-19-2014 |
| 20140187024 | METHOD OF FORMING SEED LAYER, METHOD OF FORMING SILICON FILM, AND FILM FORMING APPARATUS - Provided is a method of forming a seed layer as a seed of a thin film on an underlayer, which includes: forming a first seed layer on a surface of the underlayer by heating the underlayer, followed by supplying an aminosilane-based gas onto the surface of the heated underlayer; and forming a second seed layer on the surface of the underlayer with the first seed layer formed thereon by heating the underlayer, followed by supplying a disilane or higher order silane-based gas onto the surface of the heated underlayer. | 07-03-2014 |
| 20140193966 | METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves. | 07-10-2014 |
| 20140199825 | SILICON-GERMANIUM HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF - A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects. The preparation method according to the present invention has a simple process, which is compatible with the CMOS process and is applicable to mass industrial production. | 07-17-2014 |
| 20140213044 | METHOD FOR PRODUCING PERIODIC CRYSTALLINE SILICON NANOSTRUCTURES - A method for producing periodic crystalline silicon nanostructures of large surface area by: generating a periodic structure having a lattice constant of between 100 nm and 2 μm on a substrate, the substrate used being a material which is stable at up to at least 570° C., and the structure being produced with periodically repeating shallow and steep areas/flanks, and, subsequently, depositing silicon by directed deposition onto the periodically structured substrate, with a thickness in the range from 0.2 to 3 times the lattice constant, or 40 nm to 6 μm, at a substrate temperature of up to 400° C., followed by thermally treating the deposited Si layer to effect solid-phase crystallization, at temperatures between 570° C. and 1400° C., over a few minutes up to several days, and optionally subsequently wet-chemically selective etching to remove resultant porous regions of the Si layer. | 07-31-2014 |
| 20140242785 | SEMICONDUCTOR FILMS ON SAPPHIRE GLASS - A method is disclosed for growing large grain to single crystalline semiconductor films on inexpensive glass substrates. The method comprises deposition of semiconductor films from a eutectic melt on sapphire glass | 08-28-2014 |
| 20140256116 | Semiconductor Device and Manufacturing Method Thereof - There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more. | 09-11-2014 |
| 20140273418 | BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION - A method of forming a semiconductor device is disclosed. The method includes forming a set of doped regions in a substrate; forming a crystalline dielectric layer on the substrate, the crystalline dielectric layer including an epitaxial oxide; forming a semiconductor layer on the crystalline dielectric layer, the semiconductor layer and the crystalline dielectric layer forming an extremely thin semiconductor-on-insulator (ETSOI) structure; and forming a set of devices on the semiconductor layer, wherein at least one device in the set of devices is formed over a doped region. | 09-18-2014 |
| 20140349468 | TRENCH FILLING METHOD AND PROCESSING APPARATUS - The present disclosure provides a method for filling a trench formed on an insulating film of a workpiece. The method includes forming a first impurity-containing amorphous silicon film on a wall surface which defines the trench, forming a second amorphous silicon film on the first amorphous silicon film, and annealing the workpiece after the second amorphous silicon film is formed. | 11-27-2014 |
| 20140357060 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type. | 12-04-2014 |
| 20140357061 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film. | 12-04-2014 |
| 20140357062 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including forming a trench on a substrate; forming an insulating layer pattern within the trench; depositing an amorphous material on the substrate and the insulating layer pattern; planarizing the amorphous material; removing a portion of the amorphous material, the removed portion of the amorphous material being on an area of the substrate where the trench has been formed; crystallizing remaining portions of the amorphous material into a single crystal material; and planarizing the single crystal material. | 12-04-2014 |
| 20140363953 | METHOD FOR FORMING COMPONENTS ON A SILICON-GERMANIUM LAYER - A method for manufacturing components on an SOI layer coated with a silicon-germanium layer formed by epitaxial deposition, wherein the heat balance of the anneals performed after the epitaxial deposition is such that the germanium concentration remains higher in the silicon-germanium layer than in the SOI layer. | 12-11-2014 |
| 20140377939 | CARRIER FOR FLEXIBLE SUBSTRATE, SUBSTRATE PROCESSING APPARATUS INCLUDING THE CARRIER, AND METHOD OF MANUFACTURING FLEXIBLE DISPLAY APPARATUS - Provided is a carrier for a flexible substrate which is capable of handling a flexible substrate during a flexible substrate processing process, while allowing the flexible substrate to be easily separated. Also provided is a substrate processing apparatus, including the carrier, and a method of manufacturing a flexible display apparatus. The carrier includes a substrate supporting portion having a top surface including a mounting surface, an outer circumferential surface, surrounding the mounting surface, and a first heat cutting portion. The first heat cutting portion is located outside the mounting surface so as to be exposed on the top surface and generates heat when a current flows through the first heat cutting portion. | 12-25-2014 |
| 20150037965 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 02-05-2015 |
| 20150056791 | DEPRESSION FILLING METHOD AND PROCESSING APPARATUS - A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate is provided. The depression penetrating the insulating film is configured so as to extend to the semiconductor substrate. The method includes: forming a thin film of a semiconductor material along a wall surface that defines the depression; annealing the workpiece to cause the semiconductor material of the thin film to move toward a bottom of the depression and to form an epitaxial region corresponding to crystals of the semiconductor substrate; and etching the thin film. | 02-26-2015 |
| 20150064883 | METHOD AND SYSTEM FOR MANUFACTURING A SEMI-CONDUCTING BACKPLANE - Methods and systems to manufacture a semi-conducting backplane are described. According to one set of implementations, semi-conducting particles are positioned in a supporting material of the semi-conducting backplane utilizing perforations in the supporting material or perforations in a removable support member upon which the semi-conducting backplane is constructed. For example, semi-conducting particles are deposited in perforations on a supporting member such that a portion of the semi-conducting particles protrudes from the supporting member. Suction is applied to the semi-conducting particles to retain the semi-conducting particles in the perforations and a layer of encapsulant material is applied onto the supporting member to cover the protruding portion. The supporting member is then removed from the semi-conducting particles and the layer of encapsulant material, which together form an assembly of the semi-conducting particles and the layer of encapsulant material. The portion of the semi-conducting particles is then planarized. | 03-05-2015 |
| 20150079770 | Selective Layer Disordering in III-Nitrides with a Capping Layer - Selective layer disordering in a doped III-nitride superlattice can be achieved by depositing a dielectric capping layer on a portion of the surface of the superlattice and annealing the superlattice to induce disorder of the layer interfaces under the uncapped portion and suppress disorder of the interfaces under the capped portion. The method can be used to create devices, such as optical waveguides, light-emitting diodes, photodetectors, solar cells, modulators, laser, and amplifiers. | 03-19-2015 |
| 20150093884 | METHODS OF FORMING SEMICONDUCTOR PATTERNS INCLUDING REDUCED DISLOCATION DEFECTS AND DEVICES FORMED USING SUCH METHODS - Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate. | 04-02-2015 |
| 20150118830 | Method of Manufacturing GaN-Based Film and Composite Substrate Used Therefor - The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate ( | 04-30-2015 |
| 20150140792 | METHOD FOR DEPOSITING A GROUP III NITRIDE SEMICONDUCTOR FILM - A method for depositing a Group III nitride semiconductor film on a substrate is provided that comprises: providing a sapphire substrate; placing the substrate in a vacuum chamber; | 05-21-2015 |
| 20150303262 | NANOWIRE FET WITH TENSILE CHANNEL STRESSOR - Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions. | 10-22-2015 |
| 20150311070 | Multiple Layer Substrate - A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration. | 10-29-2015 |
| 20150318355 | METHODS OF FORMING DEFECT-FREE SRB ONTO LATTICE-MISMATCHED SUBSTRATES AND DEFECT-FREE FINS ON INSULATORS - A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures. | 11-05-2015 |
| 20150325468 | METHOD FOR PREPARING MATERIAL ON INSULATOR BASED ON ENHANCED ADSORPTION - Provided is a method for preparing a material on an insulator based on enhanced adsorption. In the method: first, a single crystal film having a doped superlattice structure, an intermediate layer, a buffer layer and a top layer film are epitaxially grown in succession on a first substrate; then, low dosage ion implantation is performed on the structure on which the top layer film is formed, so that ions are implanted above an upper surface or below a lower surface of the single crystal film having a doped superlattice structure; next, a second substrate having an insulation layer is bonded to the structure on which ion implantation has already been performed, and an annealing treatment is performed, so that a microscopic crack is produced at the single crystal film having a doped superlattice structure to achieve atomic-scale stripping. The effective stripping of bonding wafers is achieved by means of enhanced adsorption. The stripped surface is smooth and has a low roughness, and the quality of the crystal of the top layer film is high. | 11-12-2015 |
| 20150332915 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer. | 11-19-2015 |
| 20150340470 | METHODS FOR FORMING SEMICONDUCTOR FIN SUPPORT STRUCTURES - One method includes forming trenches that define a fin structure including a first layer of a first semiconductor material and a second layer of a second semiconductor material positioned above a substrate, performing at least one etching process that exposes opposing end surfaces of the first and second layers, performing at least one recess etching process that removes end portions of the first layer and defines a cavity on opposite ends of the first layer, performing an epitaxial deposition process that fills each of the cavities with a support structure including a third semiconductor material, and performing an etching process to selectively remove remaining portions of the recessed first layer relative to the second layer and the support structures, the end portions of the second layer and the support structures defining pillars on opposite ends of the fin structure. | 11-26-2015 |
| 20150348827 | FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION - Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate. | 12-03-2015 |
| 20150349061 | METHODS FOR FABRICATING GRAPHENE DEVICE TOPOGRAPHY AND DEVICES FORMED THEREFROM - Methods for forming graphite-based structures ( | 12-03-2015 |
| 20150357182 | Fabrication of III-Nitride Power Semiconductor Device - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 12-10-2015 |
| 20150357192 | METHOD OF FABRICATING CRYSTALLINE ISLAND ON SUBSTRATE - Certain electronic applications, such as OLED display back panels, require small islands of high-quality semiconductor material distributed over a large area. This area can exceed the areas of crystalline semiconductor wafers that can be fabricated using the traditional boule-based techniques. This specification provides a method of fabricating a crystalline island of an island material, the method comprising depositing particles of the island material abutting a substrate, heating the substrate and the particles of the island material to melt and fuse the particles to form a molten globule, and cooling the substrate and the molten globule to crystallize the molten globule, thereby securing the crystalline island of the island material to the substrate. The method can also be used to fabricate arrays of crystalline islands, distributed over a large area, potentially exceeding the areas of crystalline semiconductor wafers that can be fabricated using boule-based techniques. | 12-10-2015 |
| 20150357193 | METHOD FOR PRODUCING AN EPITAXIAL SEMICONDUCTOR LAYER - A method for producing an epitaxial layer made of a semiconductor material is provided in which at least one surface region of a monocrystalline substrate is subjected to dry etching inside a work chamber. A non-epitaxial semiconductor layer is then deposited on the etched surface region of the monocrystalline substrate by vaporizing a semiconductor material using an electron beam, as a result of which vapour particles of the vaporized semiconductor material are deposited on the etched surface region of the monocrystalline substrate. The non-epitaxial semiconductor layer is finally crystallized by inputting energy. | 12-10-2015 |
| 20150371850 | METHOD OF FORMING SEMICONDUCTOR THIN FILM - Provided is a method of forming a semiconductor thin film. The method may include forming, on a substrate, a thin film that contains one of Ge, Si, and a SiGe mixture, and Sn in a content of 0.1 atomic % or more to 20 atomic % or less, and applying pulsed laser light to the thin film. | 12-24-2015 |
| 20160005611 | Method for manufacturing semiconductor device - The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed. | 01-07-2016 |
| 20160013221 | PEELING APPARATUS AND MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE | 01-14-2016 |
| 20160064249 | LOCAL DOPING OF TWO-DIMENSIONAL MATERIALS - This disclosure provides systems, methods, and apparatus related to locally doping two-dimensional (2D) materials. In one aspect, an assembly including a substrate, a first insulator disposed on the substrate, a second insulator disposed on the first insulator, and a 2D material disposed on the second insulator is formed. A first voltage is applied between the 2D material and the substrate. With the first voltage applied between the 2D material and the substrate, a second voltage is applied between the 2D material and a probe positioned proximate the 2D material. The second voltage between the 2D material and the probe is removed. The first voltage between the 2D material and the substrate is removed. A portion of the 2D material proximate the probe when the second voltage was applied has a different electron density compared to a remainder of the 2D material. | 03-03-2016 |
| 20160064250 | METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE BY PERFORMING A REPLACEMENT GROWTH PROCESS - Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a metastable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 10 | 03-03-2016 |
| 20160118252 | Method Of Forming Silicon On A Substrate - A method for forming a silicon layer using a liquid silane compound is described. The method includes the steps of: forming a first layer on a substrate, preferably a flexible substrate, the first layer having a (poly)silane; and, irradiating with light having one or more wavelength within the range between 200 and 400 nm for transforming the polysilane in silicon, preferably amorphous silicon or polysilicon. | 04-28-2016 |
| 20160118255 | METHODS OF FORMING STRAINED EPITAXIAL SEMICONDUCTOR MATERIAL(S) ABOVE A STRAIN-RELAXED BUFFER LAYER - One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material layer and a second capping layer above a substrate, wherein the first and second material layers are made of semiconductor material having a lattice constant that is different than the substrate, the first material layer is strained as deposited, and a thickness of the first material layer exceeds its critical thickness required to be stable and strained, performing an anneal process after which the strain in the first material layer is substantially relaxed through the formation of crystallographic defects that are substantially confined to the semiconducting substrate, the first material layer, the first capping layer and the second material layer, and forming additional epitaxial semiconductor material on an upper surface of the resulting structure. | 04-28-2016 |
| 20160141173 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, GAS SUPPLY SYSTEM, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film. | 05-19-2016 |
| 20160148803 | SYSTEM AND METHOD FOR CONTROLLING WAFER AND THIN FILM SURFACE TEMPERATURE - A vapor deposition system and its wafer and thin-film temperature control method are disclosed. A susceptor carries a plurality of wafer holders with each bearing a wafer. The susceptor makes revolution around a center axle and each wafer holder rotates around its own axis. A carrier gas approaches a first surface of the wafer and is heated to form a thin film to be deposited on the first surface. An isothermal plate is placed at a second surface of the wafer and the second surface is opposite to the first surface. One or more remote temperature-measuring elements measure a temperature of a rear surface of the isothermal plate and the rear surface is opposite to the wafer, and a wafer-side temperature is calculated by the measured rear surface temperature of the isothermal plate. | 05-26-2016 |
| 20160172207 | PELLICLE MEMBRANE AND METHOD OF MANUFACTURING THE SAME | 06-16-2016 |
| 20160176713 | Method To Transfer Two Dimensional Film Grown On Metal-Coated Wafer To The Wafer Itself In a Face-To-Face Manner | 06-23-2016 |
| 20160181093 | III-N EPITAXY ON MULTILAYER BUFFER WITH PROTECTIVE TOP LAYER | 06-23-2016 |
