| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438466000 | DIRECT APPLICATION OF ELECTRICAL CURRENT | 55 |
| 20080206964 | Carbon Nanotube Transistor Process with Transferred Carbon Nanotubes - During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure. | 08-28-2008 |
| 20080305617 | Method for depositing a conductive capping layer on metal lines - In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance. | 12-11-2008 |
| 20090104753 | Process of Forming a Curved Profile on a Semiconductor Substrate - A semiconductor substrate is shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate. | 04-23-2009 |
| 20100003807 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS AND STORAGE MEDIUM - Provided is a method for performing etching process or film forming process to a substrate W whereupon a prescribed pattern is formed with an opening. The method is provided with a step of mixing a liquid and a gas, at least one of which contains a component that contributes to the etching process or the film forming process, and generating charged nano-bubbles | 01-07-2010 |
| 20100015785 | Method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device and the phase change memory device - According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure. | 01-21-2010 |
| 20100029062 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH SELF-FORMING GAP - A memory device has a first electrode, a second electrode, and memory material defining an inter-electrode current path between the first electrode and the second electrode. A gap is formed by shrinkage of the shrinkable material between the memory material and a shrinkable material next to the memory material. | 02-04-2010 |
| 20100055879 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to be applied to the internal electrode provided in the stage is raised stepwise to gradually increase the contact area between the back surface of the wafer and the top surface of the stage. Finally, a chuck voltage is applied to the internal electrode, so that the entire back surface of the wafer is uniformly attracted to the top surface of the stage. This reduces damage occurring in the top surface of the stage due to rubbing between the back surface of the wafer and the top surface of the stage. | 03-04-2010 |
| 20100190319 | METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER - Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another. | 07-29-2010 |
| 20100197117 | MIXED-SCALE ELECTRONIC INTERFACES - Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state. Other embodiments of the present invention are directed to a nanowire structure including a mixed-scale interface. | 08-05-2010 |
| 20110039398 | EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A NANOTUBE STRUCTURE - Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In addition, the method includes coupling the plurality of transistors in the transistor layer to the one or more power sources based on a state of the nanotube structure. | 02-17-2011 |
| 20110053348 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved. | 03-03-2011 |
| 20110081770 | REMOVING UNDESIRABLE NANOTUBES DURING NANOTUBE DEVICE FABRICATION - Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes, multiwalled nanotubes, and others. The undesirable nanotubes may be removed electrically using voltage or current, or a combination of these. This approach to removing undesirable nanotubes is sometimes referred to as “burn-off.” The undesirable nanotubes may be removed chemically or using radiation. The undesirable nanotubes of an integrated circuit may be removed in sections or one transistor (or a group of transistors) at a time in order to reduce the electrical current used or prevent damage to the integrated circuit during burn-off. | 04-07-2011 |
| 20110165759 | Tuning Capacitance to Enhance FET Stack Voltage Withstand - An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero. | 07-07-2011 |
| 20110189836 | ION/IOFF IN SEMICONDUCTOR DEVICES BY UTILIZING THE BODY EFFECT - A method for reducing leakage current of a semiconductor device includes supplying a substantially constant and non-zero bulk bias to a relatively low threshold voltage semiconductor device during formation of a conductive channel of the semiconductor device and during the formation of a non-conductive channel of the semiconductor device. | 08-04-2011 |
| 20110217827 | Removing Undesirable Nanotubes During Nanotube Device Fabrication - Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes, multiwalled nanotubes, and others. The undesirable nanotubes may be removed electrically using voltage or current, or a combination of these. This approach to removing undesirable nanotubes is sometimes referred to as “burn-off.” The undesirable nanotubes may be removed chemically or using radiation. The undesirable nanotubes of an integrated circuit may be removed in sections or one transistor (or a group of transistors) at a time in order to reduce the electrical current used or prevent damage to the integrated circuit during burn-off. | 09-08-2011 |
| 20110306183 | APPARATUS AND METHOD FOR MANUFACTURING POLYCRYSTALLINE SILICON THIN FILM - An apparatus for manufacturing a polycrystalline silicon thin film, including a crystallization container filled with silicon oil, crystallization electrodes spaced apart from the crystallization container, and a conductive plate positioned between the crystallization electrodes and connected with the crystallization electrodes. Because an insulating layer between the amorphous silicon thin film and the conductive plate is formed by using silicon oil filled within the crystallization container, Joule-heating induced crystallization (JIC) can be performed through a simpler manufacturing process. | 12-15-2011 |
| 20120021589 | METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 01-26-2012 |
| 20120322243 | APPARATUS AND METHOD FOR ELECTROCHEMICAL PROCESSING OF THIN FILMS ON RESISTIVE SUBSTRATES - An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process. | 12-20-2012 |
| 20130122690 | METHOD FOR REMOVING METALLIC NANOTUBE - A method for removing a metallic nanotube which is formed on a substrate in a first direction is disclosed. The method may comprise: forming a plurality of conductors in a second direction crossing the first direction, the conductors electrically contacting the metallic nanotube, respectively; forming at least two voltage-applying electrodes on the conductors, each of the voltage-applying electrodes electrically contacting at least one of the conductors; and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively, wherein among conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube. | 05-16-2013 |
| 20130203242 | METHOD FOR MANUFACTURING A NANOWIRE STRUCTURE - The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires ( | 08-08-2013 |
| 20130217210 | METHOD AND DEVICE FOR CONTROLLING PATTERN AND STRUCTURE FORMATION BY AN ELECTRIC FIELD - A processing method and apparatus uses at least one electric field applicator ( | 08-22-2013 |
| 20130244405 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating. | 09-19-2013 |
| 20130323910 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING SYSTEM - A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate. | 12-05-2013 |
| 20130337635 | FILM DEPOSITION APPARATUS, SUBSTRATE PROCESSING APPARATUS AND FILM DEPOSITION METHOD - A film deposition apparatus configured to perform a film deposition process on a substrate in a vacuum chamber includes a turntable configured to rotate a substrate loading area to receive the substrate, a film deposition area including at least one process gas supplying part configured to supply a process gas onto the substrate loading area and configured to form a thin film by depositing at least one of an atomic layer and a molecular layer along with a rotation of the turntable, a plasma treatment part provided away from the film deposition area in a rotational direction of the turntable and configured to treat the at least one of the atomic layer and the molecular layer for modification by plasma, and a bias electrode part provided under the turntable without contacting the turntable and configured to generate bias potential to attract ions in the plasma toward the substrate. | 12-19-2013 |
| 20140073113 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - A plasma etching method deposits a silicon-containing deposit by a plasma processing using a Si-containing gas on an object to be processed that includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the film to be processed which is exposed between the linear portions and the linear portions. In the plasma etching method, each of the plurality of narrow linear portions of the organic film and the film to be processed between the linear portions are exposed by etching the silicon-containing deposit by plasma of CF-based gas and CHF-based gas after the silicon-containing deposit is deposited. | 03-13-2014 |
| 20140073114 | IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING - Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material. | 03-13-2014 |
| 20140273403 | LIGHT INDUCED NANOWIRE ASSEMBLY - The invention provides a method for assembling semiconducting nanowires, which method can include providing a mixture comprising a dielectric solvent and two or more semiconducting nanowires, wherein the semiconducting nanowires can be the same or different; exposing the mixture to an electrostatic charge under lighting conditions; and allowing macroscopic nanowire alignment to occur, wherein each nanowire is substantially oriented along the direction of the applied electric field. | 09-18-2014 |
| 20140335679 | METHODS FOR ETCHING A SUBSTRATE - In some embodiments, a method for etching features into a substrate may include exposing a substrate having a photoresist layer disposed atop the substrate to a first process gas to form a polymer containing layer atop sidewalls and a bottom of a feature formed in the photoresist layer, wherein the first process gas is selectively provided to a first area of the substrate via a first set of gas nozzles disposed within a process chamber and; exposing the substrate to a second process gas having substantially no oxygen to etch the feature into the substrate, wherein the second process gas is selectively provided to a second area of the substrate via a second set of gas nozzles disposed in the process chamber. | 11-13-2014 |
| 20150024577 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit. | 01-22-2015 |
| 20150072508 | DIRECTIONAL SIO2 ETCH USING PLASMA PRE-TREATMENT AND HIGH-TEMPERATURE ETCHANT DEPOSITION - Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products. | 03-12-2015 |
| 20150325454 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - One method includes sequentially forming an insulating film and a first material film on a semiconductor substrate, forming on the first material film a mask film having a rectangular first opening, and dry-etching the first material film using the mask film as a mask to form an ellipsoidal second opening having its shorter side aligned in a first direction of the first material film. Forming the mask film includes forming a second material film having a side surface that faces the first direction of the first opening, and a third material film having side surfaces facing a second direction of the first opening, and the thickness of the third material film is greater than the thickness of the second material film. | 11-12-2015 |
| 20150364480 | Reducing Retention Loss in Analog Floating Gate Memory - A conditioning process for integrated circuits including floating-gate devices, such as floating-gate capacitors or transistors in analog or other circuits in which the devices are to be programmed to a specific level. Following initial programming of the floating-gate devices to a specific programmed level, the integrated circuits are subjected to a conditioning bake, followed by re-trim back to the initial programmed level. That portion of the charge at the floating-gate device that was weakly held is removed by the conditioning bake, while the re-trim replaces that charge with more strongly held (i.e., higher activation energy) programmed charge. | 12-17-2015 |
| 20160163398 | METHOD FOR CREATING AN OTPROM ARRAY POSSESSING MULTI-BIT CAPACITY WITH TDDB STRESS RELIABILITY MECHANISM - A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level. | 06-09-2016 |
| 438467000 | To alter conductivity of fuse or antifuse element | 9 |
| 20100159673 | METHOD OF CUTTING AN ELECTRICAL FUSE - A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse. | 06-24-2010 |
| 20100178752 | SEMICONDUCTOR DEVICE AND FUSE BLOWOUT METHOD - A fuse includes a fuse portion laid in such a manner that the direction of each turn of the fuse portion is parallel to the direction in which pads are arranged. The distance between the pads and the fuse portion is defined as the distance between the side of a pad facing the fuse portion and the pad nearest to the turn facing the particular side. The distance between the turn of the fuse portion and the nearest pad is the distance between the pads and the fuse portion. The pads and the fuse portion are distant from each other by a length at least ten times the width of the fuse. | 07-15-2010 |
| 20110250735 | METHOD FOR CUTTING AN ELECTRIC FUSE - An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively. | 10-13-2011 |
| 20120129319 | Electrical Antifuse, Method of Manufacture and Method of Programming - An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures. | 05-24-2012 |
| 20120178239 | PROGRAMMABLE SEMICONDUCTOR DEVICE - A programmable device includes a substrate ( | 07-12-2012 |
| 20130071998 | Electrical Fuse With Metal Line Migration - An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element. | 03-21-2013 |
| 20130224933 | Programmable Poly Fuse Using a P-N Junction Breakdown - According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction. | 08-29-2013 |
| 20160005690 | ELECTRICAL FUSE WITH METAL LINE MIGRATION - An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element. | 01-07-2016 |
| 20180025905 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 01-25-2018 |
| 438468000 | Electromigration | 9 |
| 20100136767 | METHOD FOR PRODUCTION OF THIN FILM AND APPARATUS FOR MANUFACTURING THE SAME - A method for manufacturing a thin film is provided. A substrate is loaded into a chamber. A first reaction gas and a second reaction gas are supplied into the chamber. The first reaction gas is dissociated to form crystalline nanoparticles. An amorphous material is inhibited from being formed on the substrate using the second reaction gas. Thereafter, a crystalline thin film is formed from the crystalline nanoparticles provided on the substrate. | 06-03-2010 |
| 20100291757 | METHOD OF FORMING, MODIFYING, OR REPAIRING A SEMICONDUCTOR DEVICE USING FIELD-CONTROLLED DIFFUSION - A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/−50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated, repaired or modified. | 11-18-2010 |
| 20110065262 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure. | 03-17-2011 |
| 20120003818 | Field Effect Resistor for ESD Protection - An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers ( | 01-05-2012 |
| 20120238074 | METHODS AND APPARATUS FOR CONFORMAL DOPING - Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of doping a substrate may include forming a dopant region on a substrate by implanting one or more dopant elements into the dopant region of the substrate using a plasma doping process; forming a cap layer atop the dopant region; annealing the dopant region after forming the cap layer; and removing the cap layer after annealing the dopant region. | 09-20-2012 |
| 20120315740 | SELECTIVE DEPOSITION OF POLYMER FILMS ON BARE SILICON INSTEAD OF OXIDE SURFACE - A method of selective deposition on silicon substrates having regions of bare silicon and regions of oxide formed thereon. The method includes placing the substrate on a wafer support inside a processing chamber, introducing a carbon-containing gas into the reactor, applying a bias to the substrate, generating a plasma from the hydrocarbon gas, implanting carbon ions into the regions of oxide on the substrate by a plasma doping process, and depositing a carbon-containing film on the bare silicon regions. | 12-13-2012 |
| 20130130474 | Quantum Well Device - An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer, The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor. | 05-23-2013 |
| 20130137242 | DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING - Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating. | 05-30-2013 |
| 20160042970 | PATTERN FORMING METHOD - A pattern forming method of forming a pattern on an underlying layer of a target object includes forming a block copolymer layer, which includes a first polymer and a second polymer and is configured to be self-assembled, on the underlying layer; processing the target object to form a first region containing the first polymer and a second region containing the second polymer in the block copolymer layer; etching the second region partway in a thickness direction thereof in a capacitively coupled plasma processing apparatus after the processing of the target object; generating secondary electrons from an upper electrode of the plasma processing apparatus by applying a negative DC voltage to the upper electrode and irradiating the secondary electrons onto the target object, after the etching of the second region; and additionally etching the second region in the plasma processing apparatus after the irradiating of the secondary electrons. | 02-11-2016 |
| 438469000 | Utilizing pulsed current | 3 |
| 20100003808 | METHOD OF PREPARING AN ELECTRICALLY INSULATING FILM AND APPLICATION FOR THE METALLIZATION OF VIAS - The present invention essentially relates to a method of preparing an electrically insulating film at the surface of an electrical conductor or semiconductor substrate, such as a silicon substrate. | 01-07-2010 |
| 20110014778 | Boron-10 coating process for neutron detector integrated circuit with high aspect ratio trenches - A coating process to infill high aspect-ratio vias and trenches in semiconductor substrates with dense boron for the production of neutron detectors and other devices uses a vacuum cathodic arc or other source of fully ionized boron plasma. Biasing of the substrate is used to impart energies to the plasma ions directing them toward the substrate, while repulsing the electrons. The full ionization produced by the source allows control of the energies of the boron ions by means of the bias voltage. The bias is alternated between coating deposition at low ion energies and sputtering of already coated material by energetic ions. Most of the sputtered material comes off the substrate top surface and between the trenches or vias and much of it is redeposited, thereby contributing to the infill. The process is suitable for carbon, boron or similar light elements, and is of particular interest for | 01-20-2011 |
| 20160181121 | ELECTRO-ASSISTED TRANSFER AND FABRICATION OF WIRE ARRAYS | 06-23-2016 |
| 438470000 | Fusion of semiconductor region | 1 |
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