| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438457000 | Warping of semiconductor substrate | 12 |
| 20080242049 | METHOD FOR GENERATING A MICROMECHANICAL STRUCTURE - In a method for manufacturing a micromechanical structure, first a two-dimensional structure is formed in a substrate. The two-dimensional structure is deflected from the substrate plane by action of force and fixed in the deflected state. | 10-02-2008 |
| 20090087961 | Process for fabricating semiconductor structures useful for the production of semiconductor-on-insulator substrates, and its applications - The invention relates to a process for fabricating a semiconductor structure, which comprises:
| 04-02-2009 |
| 20090124062 | DISPLAY DEVICE HAVING A CURVED SURFACE - The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed. | 05-14-2009 |
| 20120094470 | METHOD FOR FORMING INTEGRATED CIRCUITS ON A STRAINED SEMICONDUCTOR SUBSTRATE - A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate. | 04-19-2012 |
| 20130089966 | Methods of Processing Units Comprising Crystalline Materials, and Methods of Forming Semiconductor-On-Insulator Constructions - Some embodiments include methods of processing a unit containing crystalline material. A damage region may be formed within the crystalline material, and a portion of the unit may be above the damage region. A chuck may be used to bend the unit and thereby induce cleavage along the damage region to form a structure from the portion of the unit above the damage region. Some embodiments include methods of forming semiconductor-on-insulator constructions. A unit may be formed to have dielectric material over monocrystalline semiconductor material. A damage region may be formed within the monocrystalline semiconductor material, and a portion of the monocrystalline semiconductor material may be between the damage region and the dielectric material. The unit may be incorporated into an assembly with a handle component, and a chuck may be used to contort the assembly and thereby induce cleavage along the damage region. | 04-11-2013 |
| 20130183810 | SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a system for manufacturing a semiconductor device includes a spontaneous joining unit and a deformative joining unit. The spontaneous joining unit overlaps a first substrate and a second substrate and spontaneously joins mutual center portions of respective joint faces of the first substrate and the second substrate. The deformative joining unit deforms at least one peripheral portion of the respective joint faces of the first substrate and second substrate joined by the spontaneous joining unit toward the other peripheral portion and joins the mutual peripheral portions of the respective joint faces. | 07-18-2013 |
| 20130260534 | STRESS REDUCTION MEANS FOR WARP CONTROL OF SUBSTRATES THROUGH CLAMPING - A method is provided for bonding a semiconductor chip to a packaging substrate while minimizing the variation in the solder ball heights and controlling the stress in the solder balls and the stress in the packaging substrate. During the solder reflow, the warp of the packaging substrate, including the absolute warp, thermal warp, and substrate to substrate variations of the warp, is constrained at a minimal level by providing a clamping constraint to the packaging substrate. During cool down of the solder balls, the stresses and strains of the solder joints are maintained at levels that do not cause tear of the solder joints or breakage of the packaging substrate by removing the clamping constraint. Thus, the bonding process provides both uniform solder height with minimized solder non-wets and stress minimization of the solder balls and the packaging substrate. | 10-03-2013 |
| 20150056783 | SYSTEMS AND METHODS FOR MOLECULAR BONDING OF SUBSTRATES - A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates. | 02-26-2015 |
| 20150357226 | Apparatus and Method for Wafer Level Bonding - A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer. | 12-10-2015 |
| 20160071808 | INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate. | 03-10-2016 |
| 20160104620 | METHOD FOR MANUFACTURING SUBSTRATE - A method for manufacturing a substrate is provided. The method includes irradiating a single crystal substrate with a beam of laser or charged particles while moving an irradiation point of the beam with respect to the single crystal substrate so that a trajectory of the irradiation point on a surface of the single crystal substrate describes a striped pattern of straight lines. Non-crystalline regions are formed in the single crystal substrate along the trajectory. The irradiation is repeated multiple times so that directions of the striped patterns are different from each other among the multiple times of irradiation. The repetition of the irradiation changes warpage of the single crystal substrate. All of directions of the straight lines described in the multiple times of irradiation are not parallel to any of directions of crystal axes of the single crystal substrate in a plane parallel to the surface. | 04-14-2016 |
| 20160126215 | METHOD FOR ASSEMBLING TWO SUBSTRATES OF DIFFERENT NATURES VIA A DUCTILE INTERMEDIATE LAYER - A method for manufacturing a heterostructure, including: contacting a first substrate having a first coefficient of thermal expansion and a second substrate having a different second coefficient of thermal expansion; annealing an assembly formed by contacting the first substrate and the second substrate; after annealing, returning the assembly to room temperature; providing, before the contacting, at least one intermediate layer at a surface of at least one of the first and second substrates, the at least one intermediate layer being made of a material which is ductile during the annealing and returning to room temperature; performing the contacting with the at least one intermediate layer sandwiched between the first and the second substrates; upon returning to room temperature, applying an outer pressure to the assembly to maintain it compressed. | 05-05-2016 |
