| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438439000 | Recessed oxide by localized oxidation (i.e., LOCOS) | 23 |
| 20090197389 | Method for manufacturing semiconductor device - The present invention provides a method for manufacturing a semiconductor device, comprising the steps of preparing a substrate having a quartz support substrate and a silicon layer, forming a base or substrate silicon oxide film over the entire upper surface of the silicon layer, forming a silicon nitride film over the entire upper surface of the substrate silicon oxide film by a plasma CVD method, patterning the silicon nitride film thereby to form a mask pattern having a circumferential exposure portion that exposes the substrate silicon oxide film in a circumferential area, a first opening pattern that exposes the substrate silicon oxide film in an element isolation area, and a second opening pattern that exposes the substrate silicon oxide film within a peripheral area, and thermally oxidizing the substrate using the mask pattern as a mask thereby to form an element isolation structure portion in the element isolation area. | 08-06-2009 |
| 20090239352 | METHOD FOR PRODUCING SILICON OXIDE FILM, CONTROL PROGRAM THEREOF, RECORDING MEDIUM AND PLASMA PROCESSING APPARATUS - A silicon oxide film formation method includes generating plasma inside a process chamber of a plasma processing apparatus, by use of a process gas having an oxygen ratio of 1% or more, and a process pressure of 133.3 Pa or less; and oxidizing by the plasma a silicon surface exposed inside a recessed part formed in a silicon layer on a target object, thereby forming a silicon oxide film. | 09-24-2009 |
| 20100159670 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention enhances the accuracy of an end point detection when an insulation film formed on a semiconductor substrate is dry-etched. Gate layers made of polysilicon are formed, and an end point detection dummy layer made of polysilicon is formed on a LOCOS. After the gate layers and the dummy layer are formed, a TEOS film is formed on a silicon substrate so as to cover the gate layers and the dummy layer. The TEOS film, a thin gate oxide film and a thick gate oxide film are then dry-etched to form sidewalls on the sidewalls of the gate layers and also expose the front surface of the P well of the silicon substrate in a region surrounded by the LOCOS. The end point detection dummy layer helps the end point detection by being exposed during this dry-etching to enhance the accuracy of the end point detection. | 06-24-2010 |
| 20100173471 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor. | 07-08-2010 |
| 20110065256 | SYSTEM AND METHOD FOR INCREASING BREAKDOWN VOLTAGE OF LOCOS ISOLATED DEVICES - An efficient method is disclosed for increasing the breakdown voltage of an integrated circuit device that is isolated by a local oxidation of silicon (LOCOS) process. The method comprises forming a portion of a field oxide in an integrated circuit so that the field oxide has a gradual profile. The gradual profile of the field oxide reduces impact ionization in the field oxide by creating a reduced value of electric field for a given value of applied voltage. The reduction in impact ionization increases the breakdown voltage of the integrated circuit. The gradual profile is formed by using an increased thickness of pad oxide and a reduced thickness of silicon nitride during a field oxide oxidation process. | 03-17-2011 |
| 20110237048 | METHOD FOR MANUFACTURING A FULL SILICIDATION METAL GATE - The present application discloses a method for manufacturing a full silicidation metal gate, comprises the steps of forming locally oxidized isolation or shallow trench isolation, performing prior-implantation oxidation and then doping | 09-29-2011 |
| 20120190170 | PRECISE OXIDE DISSOLUTION - A method for dissolving the buried oxide layer of a SeOI wafer in order to decrease its thickness. The SeOI wafer includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer. The dissolution rate of the buried oxide layer is controlled and set to be below 0.06 Å/sec. | 07-26-2012 |
| 20140120694 | USE OF PLATE OXIDE LAYERS TO INCREASE BULK OXIDE THICKNESS IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described. | 05-01-2014 |
| 438440000 | Including nondopant implantation | 2 |
| 20080242048 | METHOD FOR MANUFACTURING SOI SUBSTRATE - To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. | 10-02-2008 |
| 20080268613 | Semiconductor Substrate And Method For Production Thereof - Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer. | 10-30-2008 |
| 438441000 | With electrolytic treatment step | 1 |
| 20090004820 | Method of Forming Isolation Layer in Flash Memory Device - The invention relates to a method of forming an isolation layer in a flash memory device and comprises providing a semiconductor substrate in which a tunnel insulating layer and a conductive layer are formed on an active region and a trench is formed on an isolation region; forming a first insulating layer in a lower portion of the trench; forming a second insulating layer on the semiconductor substrate and the first insulating layer including the trench to protect a side wall of the conductive layer; forming a third insulating layer in the trench to form an isolation layer; and adjusting an effective field height (EFH) of the isolation layer through a first etching process. | 01-01-2009 |
| 438442000 | With epitaxial semiconductor layer formation | 1 |
| 20150311111 | Fin Structure of Semiconductor Device - The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width. | 10-29-2015 |
| 438443000 | Etchback of recessed oxide | 3 |
| 20090029524 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A TRENCH - A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion. | 01-29-2009 |
| 20100015778 | METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION - A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner. | 01-21-2010 |
| 20100167497 | USE OF FIELD OXIDATION TO SIMPLIFY CHAMBER FABRICATION IN MICROFLUIDIC DEVICES - A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form a chamber, forming a first MOS transistor adjacent the second oxide region, and forming a second MOS transistor separated from the first MOS transistor by the second oxide region. | 07-01-2010 |
| 438444000 | Preliminary etching of groove | 2 |
| 20090023268 | ISOLATION METHOD OF ACTIVE AREA FOR SEMICONDUCTOR DEVICE - An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas. | 01-22-2009 |
| 438445000 | Masking of groove sidewall | 1 |
| 20140087540 | METHOD FOR FORMING TRENCH ISOLATION - A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench. | 03-27-2014 |
| 438448000 | Utilizing oxidation mask having polysilicon component | 2 |
| 20080305614 | PRECISION TRENCH FORMATION FOR SEMICONDUCTOR DEVICE - Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen. | 12-11-2008 |
| 20110081767 | PRECISION TRENCH FORMATION THROUGH OXIDE REGION FORMATION FOR A SEMICONDUCTOR DEVICE - Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen. | 04-07-2011 |
| 438449000 | Dopant addition | 2 |
| 20110275189 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; an element isolation region provided in the semiconductor substrate and having an oxide layer and an oxidant-diffusion prevention layer provided on the oxide layer; a gate dielectric film provided on the semiconductor substrate and the oxidant-diffusion prevention layer; and a gate electrode provided on the gate dielectric film. | 11-10-2011 |
| 438450000 | Implanting through recessed oxide | 1 |
| 20090042360 | STRAINED SEMICONDUCTOR BY FULL WAFER BONDING - One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein. | 02-12-2009 |
| 438452000 | Plural oxidation steps to form recessed oxide | 1 |
| 20110275190 | METHOD OF FORMING AN INSULATION STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform. | 11-10-2011 |
| 438453000 | And electrical conductor formation (i.e., metallization) | 1 |
| 20080318393 | Method for Manufacturing Semiconductor Device - There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate. The method includes forming a first gate electrode of the high breakdown voltage transistor and a second gate electrode of the low breakdown voltage transistor on a transistor formation area of the substrate, as well as a dummy gate electrode on a dummy pattern formation area of the substrate; forming an interlayer insulation film on the substrate so as to cover the first and the second gate electrodes and the dummy gate electrode; and forming a first contact hole on the first gate electrode, a second contact hole on the second gate electrode, and a dummy contact hole on the dummy gate electrode, respectively, by partially dry etching the interlayer insulation film, wherein in the formation of the contact holes, a top surface of the dummy gate electrode is exposed at a bottom of the dummy contact hole before a top surface of the first gate electrode is exposed at a bottom of the first contact hole. | 12-25-2008 |
