Entries |
Document | Title | Date |
20080220587 | Dual Stress STI - The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner. | 09-11-2008 |
20080242044 | Method for Fabricating Nonvolatile Memory Device - A method for fabricating a nonvolatile memory device includes forming a gate insulation layer, a first gate conductive layer, a first sacrificial layer, and a second sacrificial layer over a substrate, etching the first and second sacrificial layers, the first gate conductive layer, the gate insulation layer, and the substrate to form trenches, forming a first insulation layer to fill the trenches, polishing the first insulation layer using the etched second sacrificial layer as a polish stop layer, removing the second sacrificial layer, recessing the first insulation layer inside the trenches, forming a second insulation layer to fill a space produced inside the trenches by the recessing of the first insulation layer, and polishing the second insulation layer using the etched first sacrificial layer as a polish stop layer. | 10-02-2008 |
20080242045 | METHOD FOR FABRICATING TRENCH DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE - A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers. | 10-02-2008 |
20080280418 | METHOD FOR MANUFACTURING THE SHALLOW TRENCH ISOLATION STRUCTURE - A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the patterned mask layer and the patterned pad layer as a mask to form trenches in the substrate. Next, a first insulation layer is formed in the trenches. Afterwards, a protection layer is conformally formed on the substrate. Then, a second insulation layer is formed on the protection layer above the first insulation layer. Next, the patterned mask layer and the patterned pad layer are removed. Finally, a portion of the protection layer and the second insulation layer are removed. | 11-13-2008 |
20080293215 | Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions - Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed. | 11-27-2008 |
20080318392 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming shallow trench isolation structures is provided. The method comprises the following steps: providing a substrate with a “v” shaped trench, forming a first dielectric layer to cover the upper portion of the inner wall of the trench; conducting the first etching process to pull back the uncovered inner wall of the trench; removing the first dielectric layer; and forming a second dielectric layer to cover the trench and form a void inside the trench. | 12-25-2008 |
20090004817 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench. | 01-01-2009 |
20090004818 | Method of Fabricating Flash Memory Device - Disclosed herein is a method of fabricating a semiconductor flash memory device, which method avoids and prevents damage to the conductive layer of a floating gate. The disclosed method can prevent a reduction in the charge trap density characteristics and improve the yield of the device. | 01-01-2009 |
20090004819 | Method of Fabricating Flash Memory Device - In one aspect of the inventive method, a tunnel insulating film, a first conductive layer, and an isolation mask pattern are formed over a semiconductor substrate. The first conductive layer and the tunnel insulating film are patterned along the isolation mask pattern. A trench is formed in the semiconductor substrate. The trench is gap filled with a first insulating film. A polishing process is performed in order to expose the first conductive layer. A height of the first insulating film is lowered. The first conductive layer on the first insulating film is gap-filled with a second insulating film. | 01-01-2009 |
20090035918 | POST DEPOSITION PLASMA TREATMENT TO INCREASE TENSILE STRESS OF HDP-CVD SIO2 - Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure. | 02-05-2009 |
20090068818 | METHOD OF FORMING AN ISOLATION LAYER OF A SEMICONDUCTOR DEVICE - In a method of forming an isolation layer of a semiconductor device, a gate insulating layer, a first conductive layer, and a hard mask are formed in an active region of a semiconductor substrate and a trench is formed in an isolation region. The trench is partially gap-filled by forming a first insulating layer in the trench. The trench is fully gap-filled by forming a second insulating layer on the first insulating layer. A polishing process is performed on the first insulating layer and the second insulating layer formed over the hard mask. An etchback process is performed to lower a height of the second insulating layer in the trench. The trench is gap-filled by forming a third insulating layer over the first insulating layer and the second insulating layer, thereby forming an isolation layer in the trench. Accordingly, the occurrence of a void within the isolation layer is prevented. | 03-12-2009 |
20090075454 | Method and High Gapfill Capability for Semiconductor Devices - A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench. | 03-19-2009 |
20090124061 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprises forming an isolation trench on a semiconductor substrate, exposing a silicon surface of the isolation trench formed on the semiconductor substrate, filling a first insulating film into the semiconductor substrate by means of TEOS/O | 05-14-2009 |
20090155980 | Methods of Forming Trench Isolation and Methods of Forming Floating Gate Transistors - A method of forming trench isolation includes etching first trench lines into semiconductive material of a semiconductor substrate. First isolation material is formed within the first trench lines within the semiconductive material. After forming the first isolation material within the first trench lines, second trench lines are etched into semiconductive material of the substrate between the first trench lines such that the first trench lines and second trench lines alternate. Second isolation material is formed within the second trench lines within the semiconductive material. Alternate and additional aspects are contemplated. | 06-18-2009 |
20090162990 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING THE DECREASE OF THE WIDTH OF AN ACTIVE REGION - A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate. | 06-25-2009 |
20090170282 | Method of Forming Isolation Layer in Semiconductor Device - A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer. | 07-02-2009 |
20090203188 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches. | 08-13-2009 |
20090203189 | METHODS OF MANUFACTURING TRENCH ISOLATION STRUCTURES USING SELECTIVE PLASMA ION IMMERSION IMPLANTATION AND DEPOSITION (PIIID) - A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches. | 08-13-2009 |
20090215243 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching. | 08-27-2009 |
20090286381 | Protective Layer To Enable Damage Free Gap Fill - In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO | 11-19-2009 |
20090311846 | METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS - A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region. | 12-17-2009 |
20100041207 | HIGH DENSITY PLASMA GAPFILL DEPOSITION-ETCH-DEPOSITION PROCESS USING FLUOROCARBON ETCHANT - A high density plasma dep/etch/dep method of depositing a dielectric film into a gap between adjacent raised structures on a substrate disposed in a substrate processing chamber. The method deposits a first portion of the dielectric film within the gap by forming a high density plasma from a first gaseous mixture flown into the process chamber, etches the deposited first portion of the dielectric film by flowing an etchant gas comprising C | 02-18-2010 |
20100041208 | SEMICONDUCTOR DEVICE MANUFACTURED WITH A DOUBLE SHALLOW TRENCH ISOLATION PROCESS - A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area. | 02-18-2010 |
20100055868 | Method of forming insulation layer of semiconductor device and method of forming semiconductor device using the insulation layer - A method of forming an insulating layer of a semiconductor device, the method including preparing a semiconductor substrate having a plurality of structures and gaps between adjacent structures, forming an insulating layer for oxygen supply on the semiconductor substrate, forming an SOG (spin-on-glass) layer on the insulating layer for oxygen supply to fill the gaps, and curing the SOG layer, wherein the insulating layer for oxygen supply supplies oxygen to the SOG layer during curing of the SOG layer. | 03-04-2010 |
20100055869 | Semiconductor device and method of manufacturing same - A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith. | 03-04-2010 |
20100075480 | STI STRESS MODULATION WITH ADDITIONAL IMPLANTATION AND NATURAL PAD SIN MASK - A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation. | 03-25-2010 |
20100099236 | GAPFILL IMPROVEMENT WITH LOW ETCH RATE DIELECTRIC LINERS - A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench. | 04-22-2010 |
20100129983 | Method of Fabricating Semiconductor Device - Methods of fabricating a semiconductor device that is capable of reducing and/or maintaining a proper divot depth at the corners of a device isolation layer. The method includes forming a pad oxide layer and a pad nitride layer sequentially on a semiconductor substrate, forming a trench by selectively etching the pad oxide layer, the pad nitride layer and the semiconductor substrate, depositing an insulating layer in the trench, selectively etching the pad nitride layer and the insulating layer by performing a first etching process, removing the pad nitride layer by performing a second etching process, and forming a gate polysilicon layer over the entire surface of the semiconductor substrate. | 05-27-2010 |
20100144117 | Semiconductor device having device characteristics improved by straining surface of active region and its manufacture method - A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed. | 06-10-2010 |
20100151656 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is not filled; forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns. | 06-17-2010 |
20100197112 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion. | 08-05-2010 |
20100291751 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void. | 11-18-2010 |
20100304548 | Silicon Nitride Hardstop Encapsulation Layer for STI Region - A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer ( | 12-02-2010 |
20100304549 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer. | 12-02-2010 |
20100323495 | RECESSED GATE ELECTRODE MOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess. | 12-23-2010 |
20110027965 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure. | 02-03-2011 |
20110117725 | Methods of Forming Recessed Access Devices Associated with Semiconductor Constructions - The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region. | 05-19-2011 |
20110183492 | Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions - Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition. | 07-28-2011 |
20110207290 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method deposits a dielectric stress-canceling film on oxide films formed on the surfaces of a semiconductor substrate and its isolation trenches, and partly etches the dielectric stress-canceling film to leave a dielectric base film inside each trench and a dielectric top film outside each trench. The trenches are then filled with a dielectric layer that covers the dielectric top and base films, the upper part of this dielectric layer is removed to expose the dielectric top films, and the dielectric top films are selectively etched, using the trench-filling dielectric layer as an etching mask. In the resulting trench isolation structure, the trenches are completely filled with dielectric material, and stress exerted by the oxide films in the trenches during heat treatment is canceled by opposing stress exerted by the dielectric base films. | 08-25-2011 |
20110312155 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a first insulating layer, charge storage layers, element isolation insulating films, and a second insulating layer formed on the charge storage layers and the element isolation insulating films and including a stacked structure of a first silicon nitride film, first silicon oxide film, intermediate insulating film and second silicon oxide film. The first silicon nitride film has a nitrogen concentration of not less than 21×10 | 12-22-2011 |
20120122297 | METHOD OF FABRICATING A NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps. | 05-17-2012 |
20120202336 | METHOD OF FORMING AN ISOLATION STRUCTURE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench. | 08-09-2012 |
20120270380 | METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate. A liner layer that includes a liner nitride layer and a liner oxide layer is formed on an exposed surface of the trench. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed to expose a portion of the liner nitride layer on an upper portion of the trench. A first preheating process is performed to release stress of the liner layer. A second preheating process is performed to oxidize the exposed liner nitride layer. A buffer layer is formed on a portion of the liner layer that is formed on a sidewall of the trench and exposed after the flowable insulation layer is recessed. The buffer layer is etched to smoothen a rough portion of the liner layer that is formed when the flowable insulation layer is recessed. A buried insulation layer is deposited in the trench. | 10-25-2012 |
20120276714 | METHOD OF OXIDIZING POLYSILAZANE - A method of oxidizing polysilazane is disclosed, comprising providing a substrate, comprising a trench, forming a polysilazane layer in the trench, and treating the polysilazane layer in an acid containing solution applied with mega-sonic waves to oxidize the polysilazane layer, wherein the acid containing solution comprises phosphoric acid, sulfuric acid, H | 11-01-2012 |
20120282756 | Thin Film Filling Method - The present invention relates to a thin film filling method, including: feeding reactive gases including a silicon-containing gas, an oxygen-containing gas, an inert gas and a fluent gas into a reaction chamber; forming a first deposited thin film in the trench or gap through HDP CVD; feeding an etching gas and the fluent gas without feeding said silicon-containing gas and oxygen-containing gas, to sputter the surface of the first deposited thin film; feeding said silicon-containing gas and oxygen-containing gas without feeding said etching gas, so that a second deposited thin film is formed on the surface of the sputtered first deposited thin film; feeding said etching gas and fluent gas without feeding said silicon-containing gas and oxygen-containing gas, to sputtering the surface of said second deposited thin film; repeating the last two steps; feeding the silicon-containing gas and oxygen-containing gas without feeding the etching gas to form a plasmas of low pressure and high density, so that a third deposited thin film, which completely fills said trench or gap, is formed on the surface of the sputtered second deposited thin film. | 11-08-2012 |
20120302039 | ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX - Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion. | 11-29-2012 |
20120309166 | PROCESS FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A process for forming a shallow trench isolation structure is provided. Firstly, a semiconductor substrate is provided. Then, a hard mask is formed over the semiconductor substrate, wherein the hard mask includes a pad oxide layer, a silicon nitride layer and an opening. Then, a trench is formed in the semiconductor substrate according to the opening Then, a pull-back process is performed to treat the silicon nitride layer at a sidewall of the opening, wherein the pull-back process is a wet etching process carried out in a phosphoric acid solution. After the pull-back process is performed, an insulating material is filled in the trench, thereby forming the shallow trench isolation structure. | 12-06-2012 |
20130017667 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity. | 01-17-2013 |
20130029471 | REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDUCTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 01-31-2013 |
20130095637 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including forming a mask layer on a semiconductor substrate; forming a trench in the semiconductor substrate using the mask layer as an etch mask; forming a first layer in the trench; and performing a first thermal treatment process on the first layer such that the first thermal treatment process is performed under an atmosphere that includes ozone and water vapor and transforms the first layer into a second layer. | 04-18-2013 |
20130164911 | PLASMA PROCESSING METHOD - The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma. | 06-27-2013 |
20130171803 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide. | 07-04-2013 |
20130260533 | INTRENCH PROFILE - A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. | 10-03-2013 |
20140038387 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions. | 02-06-2014 |
20140162431 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer. | 06-12-2014 |
20140162432 | Semiconductor Structure and Method - An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness. | 06-12-2014 |
20140199822 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING AN INSULATIVE MATERIAL ON A SEMICONDUCTIVE MATERIAL, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICES - A method of forming a semiconductor device structure. The method comprises forming an insulative material on a semiconductive material, and microwave annealing at least an interface between the insulative material and the semiconductive material. Additional methods of forming a semiconductor device structure, and related semiconductor device structures and a semiconductor device are also described. | 07-17-2014 |
20140213038 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes providing a substrate, supplying a first liquid including a terpene to a surface of the substrate, supplying a second liquid including a silicon-containing compound to the surface of the substrate, and converting the silicon-containing compound to a silicon oxide compound. | 07-31-2014 |
20140220762 | METHOD OF MANUFACTURING ISOLATION STRUCTURE - A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity. | 08-07-2014 |
20140242776 | Strained Isolation Regions - A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 08-28-2014 |
20140256115 | SEMICONDUCTOR PROCESS - A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided. | 09-11-2014 |
20150044855 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 02-12-2015 |
20150118824 | METHOD OF FORMING STRESSED SOI LAYER - One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor. | 04-30-2015 |
20160013092 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-14-2016 |
20160254192 | METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES | 09-01-2016 |