| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438430000 | And deposition of polysilicon or noninsulative material into groove | 71 |
| 20080200007 | Methods of forming semiconductor devices - A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern. | 08-21-2008 |
| 20080206957 | Method of Forming Isolation Layer of Semiconductor Memory Device - The present invention relates to a method of forming an isolation layer of a semiconductor memory device. After a trench is formed by etching a semiconductor substrate, a liner insulating film is formed from a DCS-HTO material having a similar wet etch rate to that of a PSZ film that gap fills an isolation layer, and the trench is gap filled with the PSZ film. Accordingly, in a subsequent etch process for EFH control of the isolation layer, residues do not remain on sidewalls of a conductive film for a floating gate, thereby improving electrical properties of devices. | 08-28-2008 |
| 20080213972 | Processes for forming isolation structures for integrated circuit devices - Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 09-04-2008 |
| 20080248628 | Methods of Forming Integrated Circuit Devices Having Single Crystal Semiconductor FIN Structures that Function as Device Active Regions - Methods of forming integrated circuit devices include forming an electrically insulating layer having a semiconductor fin structure extending therethrough. This semiconductor fin structure may include at least one amorphous and/or polycrystalline semiconductor region therein. The at least one amorphous and/or polycrystalline semiconductor region within the semiconductor fin structure is then converted into a single crystalline semiconductor region. This semiconductor fin structure is then used as an active region of a semiconductor device. | 10-09-2008 |
| 20080268610 | METHODS AND SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION USING A CONDUCTIVE REGION - Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench. | 10-30-2008 |
| 20080305612 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating films so that parts of the polycrystalline silicon film on the respective gate insulating films are on a level with each other and serving as a gate electrode. The substrate is formed with a recess defined by a bottom and sidewalls substantially perpendicular to the bottom, the recess corresponding to the part of the gate insulating film with the first film thickness. | 12-11-2008 |
| 20090042358 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench. | 02-12-2009 |
| 20090061592 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing the semiconductor device includes forming a first polysilicon film on an active region and an element isolation region made of a dielectric material provided in a semiconductor substrate; forming a hard mask on the first polysilicon film; etching the first polysilicon film, the semiconductor substrate in the active region and the dielectric material in the element isolation region by using the hard mask to form first and second gate trenches in the active region and the element isolation region, respectively; and filling the first and second gate trenches with a second polysilicon film before the hard mask is removed. | 03-05-2009 |
| 20090155979 | Method of manufacturing a semiconductor device - In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated. | 06-18-2009 |
| 20090181517 | METHOD OF FORMING FLASH MEMORY DEVICE - The present invention relates to a method of forming a flash memory device, which is capable of forming floating gates. According to a method of forming a flash memory device in accordance with the present invention, isolation mask patterns are first formed over a semiconductor substrate. Trenches are formed by performing an etching process using the isolation mask patterns. Isolation layers are formed between the isolation mask patterns, including the insides of the respective trenches. The isolation mask patterns are removed. Tunnel dielectric layers and crystallized first conductive layers are sequentially formed over the exposed semiconductor substrate. A dielectric layer and a second conductive layer are formed over the isolation layers and the first conductive layers. | 07-16-2009 |
| 20090263952 | SEMICONDUCTOR DEVICE FABRICATION USING SPACERS - A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask. | 10-22-2009 |
| 20090280619 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY - The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy. | 11-12-2009 |
| 20100062582 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - There is provided a method of manufacturing a silicon carbide semiconductor device including the steps of: in a semiconductor stacked substrate including a first conductivity type silicon carbide crystal substrate, a first conductivity type silicon carbide crystal layer, a second conductivity type silicon carbide crystal layer, and a first conductivity type semiconductor region, forming a trench extending through the first conductivity type semiconductor region and the second conductivity type silicon carbide crystal layer into the first conductivity type silicon carbide crystal layer defined as a bottom surface; forming a silicon film on at least a part of the trench; heating the semiconductor stacked substrate having the silicon film formed to a temperature that is not less than the melting temperature of the silicon film; removing the heated silicon film; forming a gate insulating film on a surface exposed after the silicon film is removed; and forming a gate electrode layer on a surface of the gate insulating film. | 03-11-2010 |
| 20100120221 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR - A method for fabricating a semiconductor device includes forming a plurality of pillar structures over a substrate, forming gate electrodes over sidewalls of the pillar structures, forming a sacrificial layer buried between the pillar structures, etching the sacrificial layer and the substrate to form trenches in the substrate, forming first inter-layer insulation patterns buried over the trenches and removing the remaining sacrificial layer at substantially the same time, and forming second inter-layer insulation patterns over the first inter-layer insulation patterns and buried between the pillar structures. | 05-13-2010 |
| 20100129982 | INTEGRATION SEQUENCES WITH TOP SURFACE PROFILE MODIFICATION - Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess. | 05-27-2010 |
| 20100197111 | METHOD OF MANUFACTURING MEMORY DEVICE AND METHOD OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE USING THE SAME - A method of manufacturing a memory device and a phase-change memory device is presented. The method of manufacturing the memory device includes performing Ge ion implantation on a top surface of a first layer. The method also includes performing a fast heat treatment on the ion-implanted first layer. The method also includes forming a second layer on a top of the fast heat-treated first layer. | 08-05-2010 |
| 20100330775 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATE - A method for fabricating a semiconductor device with a buried gate includes: etching a substrate to form a plurality of trenches; forming a plurality of buried gates that fill lower portions of the trenches; forming a plurality of sealing layers that gap-fill upper portions of the trenches and have protrusions higher than a top surface of the substrate; forming an inter-layer insulation layer over the whole surface of the substrate including the sealing layers; and etching the inter-layer insulation layer to form a contact hole that is aligned with a space between the protrusions of the sealing layers. | 12-30-2010 |
| 20110003459 | METHOD FOR FABRICATING BURIED GATE USING PRE LANDING PLUGS - A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. | 01-06-2011 |
| 20110053341 | INTEGRATED CIRCUIT ARRANGEMENT COMPRISING ISOLATING TRENCHES AND A FIELD EFFECT TRANSISTOR AND ASSOCIATED PRODUCTION METHOD - A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array. | 03-03-2011 |
| 20110059595 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type non-volatile memory device including a plurality of memory cells stacked along channels protruding from a substrate includes: alternately forming a plurality of first material layers and a plurality of second material layers over the substrate; forming a buffer layer over the substrate with the plurality of the first material layers and the plurality of the second material layers formed thereon; forming trenches by etching the buffer layer, the plurality of the second material layers, and the plurality of the first material layers; forming a material layer for channels over the substrate to fill the trenches; and forming the channels by performing a planarization process until a surface of the buffer layer is exposed. | 03-10-2011 |
| 20110065255 | Methods of Fabricating Nonvolatile Memory Devices - Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening. The extended portion has a smaller width than the bottom portion. A second lower conductive pattern is formed filling the second opening. | 03-17-2011 |
| 20110092048 | METHOD OF FORMING ACTIVE REGION STRUCTURE - A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask. | 04-21-2011 |
| 20110104869 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region. | 05-05-2011 |
| 20110117722 | Semiconductor Device With Charge Storage Pattern And Method For Fabricating The Same - A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns. | 05-19-2011 |
| 20110117723 | NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING - By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like. | 05-19-2011 |
| 20110201173 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A first spin-on-dielectric layer is formed over a semiconductor substrate. An abnormal oxidation of the first spin-on-dielectric layer is carried out. A surface of the first spin-on-dielectric layer is removed. A second spin-on-dielectric layer is formed over the first spin-on-dielectric layer. A non-abnormal oxidation of the first and second spin-on-dielectric layers is carried out to modify the second spin-on-dielectric layer without modifying the first spin-on-dielectric layer. | 08-18-2011 |
| 20110212595 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF MAKING - A process for fabricating a semiconductor device having reduced capacitance for high frequency circuit protection is disclosed that comprises first forming an n+ buried layer in a p-type substrate by depositing n-type dopant on the top surface of the substrate and then drive in or by implanting n-type material into the substrate, and then growing an n-type epitaxial layer atop the n+ buried layer as the device layer. Trenches that surrounds the device region with depth extending from the top surface, going through the n+ buried layer and reaching down to the substrate are then formed and then an n+ layer on the sidewalls of the trenches is formed by diffusion or ion implantation. The trenches are then filled by growing a layer of thermal oxide on the sidewalls of the trenches and followed by deposition of plasma enhanced oxide, nitride, TEOS oxide CVD oxide, or polysilicon into the trenches and then planarizing the top surface by plasma etch back or polishing. Then n+ region of the device is formed by forming an oxide layer on the top surface of the device layer and then etching the oxide by photolithography, then depositing n-type dopant material and then driving in by high temperature diffusion. Finally p+ region of the device is formed by etching the oxide using photolithography, then depositing p-type dopant material by solid or gas phase deposition or ion implantation and then driving in by high temperature diffusion so that the breakdown voltage between cathode and anode of the device is set to a targeted voltage for high frequency circuit protection. | 09-01-2011 |
| 20110237047 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an isolation layer which defines an active region in a substrate, forming recess patterns in the active region and the isolation layer, baking a surface of the recess pattern by conducting an annealing process and forming a gate dielectric layer over a surface of the recess pattern by conducting an oxidation process. | 09-29-2011 |
| 20110256688 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. | 10-20-2011 |
| 20110318903 | MANUFACTURING METHOD FOR FIN-FET HAVING FLOATING BODY - A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide. | 12-29-2011 |
| 20110318904 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided. | 12-29-2011 |
| 20120009760 | METHOD FOR FABRICATING ETCHING BARRIER BY USING SHADOW EFFECT AND METHOD FOR FABRICATING ONE SIDE CONTACT OF VERTICAL TRANSISTOR USING THE SAME - A method for fabricating an etching barrier includes forming wall bodies with a trench in between the wall bodies in a semiconductor substrate. An etching barrier is formed by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by upper portions of the wall bodies. | 01-12-2012 |
| 20120108033 | METHOD OF MANUFACTURING DEVICES HAVING VERTICAL JUNCTION EDGE - Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties. | 05-03-2012 |
| 20120122296 | METHODOLOGY FOR WORDLINE SHORT REDUCTION - The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) providing a plurality of SASTIs with a plurality of first POLY cells deposited thereon; and (b) depositing a first fill-in material having a relatively high etching rate oxide-like material in the plurality of SASTIs and on each side wall of the plurality of first POLY cells. | 05-17-2012 |
| 20120184082 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A high power amplifier used for a front end module of a cellular telephone is a silicon-based CMOS integrated circuit. The output stage of the amplifier includes an LDMOSFET portion in which many LDMOSFET cells are integrated. In the LDMOSFET cell, to reduce the resistance between a backside source electrode and a surface source region, a polysilicon plug doped with boron in a high concentration is embedded into a semiconductor substrate. The polysilicon plug contracts due to solid phase epitaxial growth caused by a heat treatment to generate strain in the silicon substrate. The manufacturing method of a semiconductor device such as an LDMOSFET includes forming a hole passing through an epitaxial layer from the surface of a substrate and embedding a polysilicon plug. A polysilicon member is deposited out in a state where a thin silicon oxide film exists on the inner surface of the hole. | 07-19-2012 |
| 20120190169 | METHOD FOR FABRICATING DEEP TRENCH ISOLATION - The invention provides a method for fabricating a deep trench isolation including: providing a substrate; forming a first trench in the substrate; conformally forming a first liner layer on the sidewall and bottom of the first trench; forming a first filler layer on the first liner layer and filling the first trench; forming an epitaxial layer on the substrate and the first trench; forming a second trench through the epitaxial layer and over the first trench; conformally forming a second liner layer on the sidewall and bottom of the second trench; and forming a second filler layer on the second liner layer and filling the second trench. | 07-26-2012 |
| 20120208347 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Methods of fabricating a three-dimensional semiconductor device are provided. Methods may include forming a stack structure including first layers and second layers alternately stacked on a substrate, patterning the stack structure to form at least one isolation trench, forming channel structures penetrating the stack structure and being spaced apart from the isolation trench, and forming upper interconnection lines on the stack structure to connect the channel structures to each other. An isolation trench may be formed prior to formation of the channel structures. | 08-16-2012 |
| 20120252187 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern. | 10-04-2012 |
| 20120289023 | Method for Producing a Semiconductor Device - A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench. | 11-15-2012 |
| 20120302037 | Method of Protecting STI Structures From Erosion During Processing Operations - Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure. | 11-29-2012 |
| 20130078784 | CMP SLURRY AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, the CMP slurry includes abrasive particles made of colloidal silica in an amount of 0.5 to 3% by mass of a total mass of the CMP slurry, and a polycarboxylic acid having a weight average molecular weight of from 500 to 10,000, in an amount of 0.1 to 1% by mass of the total mass of the CMP slurry. 50 to 90% by mass of the abrasive particles each has a primary particle diameter of 3 to 10 nm. The CMP slurry has a pH within a range of 2.5 to 4.5. | 03-28-2013 |
| 20130109152 | METHOD OF MAKING LOWER PARASITIC CAPACITANCE FINFET | 05-02-2013 |
| 20130164910 | DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE - Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes. | 06-27-2013 |
| 20130178045 | Method of Forming Transistor with Increased Gate Width - Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess. | 07-11-2013 |
| 20130189827 | THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate. | 07-25-2013 |
| 20130260532 | Method for Manufacturing Semiconductor Device - The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a shallow trench in a substrate; forming a shallow trench filling layer in the shallow trench; forming a cap layer on the shallow trench filling layer; and implanting ions into the shallow trench filling layer and performing an annealing to form a shallow trench isolation. In the method for manufacturing the semiconductor device according to the present invention, an insulating material is formed by implanting ions into the filling material in the shallow trench, and a compressive stress is applied to the active region of the substrate due to the volume expansion of the filling material, so that the carrier mobility in the channel regions to be formed later can be increased and the device performance can be improved. | 10-03-2013 |
| 20130323905 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench. | 12-05-2013 |
| 20140030868 | DEPOSIT/ETCH FOR TAPERED OXIDE - A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device. | 01-30-2014 |
| 20140045318 | FORMING A TAPERED OXIDE FROM A THICK OXIDE LAYER - Processes for forming a tapered field plate dielectric in a semiconductor substrate are provided. The process may be used to form a variety of types of devices, such as Schottky diodes, HVFETs, JFET, IGBT, bipolar transistors, and the like. The process may include etching a trench in a semiconductor wafer, depositing an insulating layer on the semiconductor wafer to form a gap within the trench, depositing a masking layer on the insulating layer, and alternatingly etching the masking layer and the insulating layer to form a tapered field plate dielectric region. | 02-13-2014 |
| 20140099772 | METHOD OF FORMING A BACKSIDE CONTACT STRUCTURE HAVING SELECTIVE SIDE-WALL ISOLATION - A backside contact structure is created using the following sequence of steps: etching a deep tench from the front surface of the semiconductor wafer to the buried layer to be contacted; depositing an isolation layer into the trench which covers the surfaces of the trench; performing an ion beam anisotropic etch in order to selectively etch the isolation layer at the bottom of the trench; filling the trench with a conductive material in order to create an electrical connection to the backside layer. The process can either be performed at a front-end stage of wafer processing following the formation of shallow trench isolation structures, or at a back-end stage after device transistors are formed. The backside contact structure so fabricated is used to electrically isolate circuit structures constructed on the wafer's upper surface, so that the various components of an integrated circuit can operate at different reference voltages. | 04-10-2014 |
| 20140099773 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 04-10-2014 |
| 20140134825 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. | 05-15-2014 |
| 20140187019 | DEPOSIT/ETCH FOR TAPERED OXIDE - A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device. | 07-03-2014 |
| 20140220761 | REDUCTION OF POLYSILICON RESIDUE IN A TRENCH FOR POLYSILICON TRENCH FILLING PROCESSES - A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a trench dielectric liner and filled by a first polysilicon layer. The surface of the trench dielectric liner is etched, wherein dips in the trench dielectric liner are formed relative to a top surface of the first polysilicon layer which results in forming a protrusion including the first polysilicon layer. The first polysilicon layer is etched to remove at least a portion of the protrusion. A second dielectric layer is formed over at least the trench after etching the first polysilicon layer. A second polysilicon layer is deposited. The second polysilicon layer is etched to remove it over the trench and provide a patterned second polysilicon layer on the top side of the semiconductor layer. | 08-07-2014 |
| 20140357050 | METHOD OF FORMING ISOLATING STRUCTURE AND THROUGH SILICON VIA - A method of forming an isolation structure and a through silicon via includes the following steps. First, at least a first trench and at least a second trench are formed in the substrate by a single etch step. Then, an insulating layer is formed to simultaneously fill up the first trench and cover a sidewall and a bottom of the second trench. After that, a conductive layer is formed to fill in the second trench. Subsequently, the insulating layer and the conductive layer on a front side of the substrate are removed. Later, a back side of the substrate is thinned to expose the conductive layer in the second trench. The insulating layer in the first trench serves as an insulating filling, and the insulating layer on the sidewall of the second trench serves as a liner of the through silicon via. | 12-04-2014 |
| 20150072503 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes dry-etching a member containing silicon in a first pressure range equal to or more than a first pressure or in a second pressure range equal to or less than a second pressure, wherein the first pressure is obtained by multiplying a saturated pressure by 0.85, the saturated pressure is defined as a pressure under which an etching rate is one of a maximum value or a value obtained by multiplying the maximum value by a predetermined coefficient, and the etching rate is a half value of the maximum value under the second pressure. | 03-12-2015 |
| 20150340368 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - One semiconductor device manufacturing method includes forming, on a principal surface of a semiconductor substrate, multiple active regions which extend in an X-direction within the principal surface and are repeatedly arranged in a Y-direction, forming multiple trenches which extend in the Y-direction and define multiple active regions (silicon pillars) by respectively dividing the multiple active regions in the X-direction, forming element isolation regions by embedding an insulating film in the multiple trenches (T | 11-26-2015 |
| 20150357230 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer. | 12-10-2015 |
| 20150371956 | CRACKSTOPS FOR BULK SEMICONDUCTOR WAFERS - Embodiments of the present invention provide crackstops for bulk semiconductor wafers and methods of fabrication. A die level crackstop is formed as a trench within the wafer around each die. A wafer level crackstop includes one or more trenches formed as rings around the periphery of the wafer near the wafer edge. These crackstops serve to prevent damage during handling of ultra thin wafers and dicing of individual ICs, thereby improving product yield. | 12-24-2015 |
| 20160005642 | ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE - Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. | 01-07-2016 |
| 20160093696 | INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES - An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate. | 03-31-2016 |
| 20160104647 | MANUFACTURING METHOD OF A SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure. | 04-14-2016 |
| 438431000 | Oxidation of deposited material | 9 |
| 20080268611 | Shallow trench isolation by atomic-level silicon reconstruction - Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidewall surface, prior to performing oxidation, by reconstructing silicon atoms at the surface. The suggested STI region can be used in imager pixel cells or memory device applications. | 10-30-2008 |
| 20090017596 | Methods Of Forming Oxides, Methods Of Forming Semiconductor Constructions, And Methods Of Forming Isolation Regions - Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition. | 01-15-2009 |
| 20090047770 | METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS - A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process. | 02-19-2009 |
| 20090291543 | Method for Manufacturing a Field Plate in a Trench of a Power Transistor - A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type is disclosed. The trench is formed in a first main surface of the substrate. | 11-26-2009 |
| 20110117724 | ISOLATION STRUCTURE FOR STRAINED CHANNEL TRANSISTORS - A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region. | 05-19-2011 |
| 20140099774 | Method for Producing Strained Ge Fin Structures - Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer. | 04-10-2014 |
| 20160086842 | Method for Producing a Semiconductor Device - A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench. | 03-24-2016 |
| 438432000 | Nonoxidized portions remaining in groove after oxidation | 2 |
| 20090017597 | METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION - A method for manufacturing semiconductor shallow trench isolation is performed as follows. First, a semiconductor substrate including at least one shallow trench is provided, and the shallow trench is filled with Spin-On-Dielectric (SOD) material, e.g., polysilazane, to form a SOD material layer. Then, the SOD material layer is subjected to a planarization process. Oxygen ions are implanted into the SOD material layer to a predetermined depth, and a high temperature process is performed afterwards to transform the portion of the SOD material layer having oxygen ions into a silicon oxide layer. The oxygen ions can be implanted by plasma doping, immersion doping or ion implantation. | 01-15-2009 |
| 20150140780 | METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION STRUCTURE - A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer. | 05-21-2015 |
