| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438429000 | And epitaxial semiconductor formation in groove | 27 |
| 20080268609 | STACKING FAULT REDUCTION IN EPITAXIALLY GROWN SILICON - Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut. | 10-30-2008 |
| 20090011570 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer. | 01-08-2009 |
| 20090104751 | NARROW SEMICONDUCTOR TRENCH STRUCTURE - Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material. | 04-23-2009 |
| 20090317959 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed. | 12-24-2009 |
| 20090325361 | METHOD FOR PRODUCING A SEMICONDUCTOR INCLUDING A MATERIAL LAYER - A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench. | 12-31-2009 |
| 20100047995 | METHOD FOR FORMING SELF-ALIGNED PHASE-CHANGE SEMICONDUCTOR DIODE MEMORY - A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks. | 02-25-2010 |
| 20100068866 | III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate - A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer. | 03-18-2010 |
| 20100120220 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL GATE - A method for fabricating a semiconductor device includes: forming a stack structure including pillar regions whose upper portion has a wider width than a lower portion over a substrate, the lower portion including at least a conductive layer; forming a gate insulation layer on sidewalls of the pillar regions; forming active pillars to gap-fill the pillar regions; and forming vertical gates that serve as both gate electrode and word lines by selectively etching the conductive layer. | 05-13-2010 |
| 20100124812 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL GATE - A method for fabricating a semiconductor device includes forming buried bit lines in a first substrate; forming a trench that separate the buried bit lines from each other; forming an interlayer insulation layer to gap-fill the trench; forming a second substrate over the first substrate gap-filled with the interlayer insulation layer; forming a protective pattern over the second substrate; forming a plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and forming vertical gates surrounding sidewalls of the active pillars. | 05-20-2010 |
| 20100197110 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH SEG FILM ACTIVE REGION - A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved. | 08-05-2010 |
| 20120094467 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD WITH IMPROVED EPITAXIAL QUALITY OF III-V COMPOUND ON SILICON SURFACES - Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing. | 04-19-2012 |
| 20130017666 | METHOD OF FORMING ISOLATION STRUCTUREAANM Chung; Jui HsuanAACI New Taipei CityAACO TWAAGP Chung; Jui Hsuan New Taipei City TW - A method of forming an isolation structure includes the steps of forming an insulating spacer on the side surfaces of a trench in a substrate, exposing a portion of the substrate, growing an epitaxial silicon layer above a bottom surface of the trench, oxidizing the epitaxial silicon layer to form a thermal oxide layer, and filling a portion of the trench above the thermal oxide layer with a dielectric material. | 01-17-2013 |
| 20130071995 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate. | 03-21-2013 |
| 20130122686 | Reverse Tone STI Formation - A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. | 05-16-2013 |
| 20130149838 | PROCESS FOR FILLING DEEP TRENCHES IN A SEMICONDUCTOR MATERIAL BODY, AND SEMICONDUCTOR DEVICE RESULTING FROM THE SAME PROCESS - A process for manufacturing a semiconductor device envisages the steps of: providing a semiconductor material body having at least one deep trench that extends through said body of semiconductor material starting from a top surface thereof; and filling the deep trench via an epitaxial growth of semiconductor material, thereby forming a columnar structure within the body of semiconductor material. The manufacturing process further envisages the step of modulating the epitaxial growth by means of a concurrent chemical etching of the semiconductor material that is undergoing epitaxial growth so as to obtain a compact filling free from voids of the deep trench; in particular, a flow of etching gas is introduced into the same reaction environment as that of the epitaxial growth, wherein a flow of source gas is supplied for the same epitaxial growth. | 06-13-2013 |
| 20140099771 | Reverse Tone STI Formation - A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. | 04-10-2014 |
| 20140127878 | FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION - Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate. | 05-08-2014 |
| 20140141594 | Method for Manufacturing a Semiconductor Device - A method for producing a semiconductor device is provided. The method includes: providing a wafer including an upper surface and a plurality of semiconductor mesas extending to the upper surface; forming a first support structure made of a first material and adjoining the plurality of semiconductor mesas at the upper surface so that adjacent pairs of the plurality of semiconductor mesas are bridged by the first support structure; forming a second support structure made of a second material different from the first material and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the plurality of semiconductor mesas are bridged by the second support structure; removing the first support structure; and at least partly removing the second support structure. | 05-22-2014 |
| 20140213037 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS - Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate. | 07-31-2014 |
| 20140357049 | Semiconductor Structures and Methods with High Mobility and High Energy Bandgap Materials - An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin. | 12-04-2014 |
| 20150056782 | Method of Manufacturing a Super Junction Semiconductor Device with Overcompensation Zones - According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns. | 02-26-2015 |
| 20150132920 | Fin Structure for a FinFET Device - A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin. | 05-14-2015 |
| 20160064530 | FinFETs with Vertical Fins and Methods for Forming the Same - In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins. | 03-03-2016 |
| 20160126335 | LATTICE MATCHED ASPECT RATIO TRAPPING TO REDUCE DEFECTS IN III-V LAYER DIRECTLY GROWN ON SILICON - A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions. | 05-05-2016 |
| 20160172470 | Isolation Structure of Fin Field Effect Transistor | 06-16-2016 |
| 20160204036 | MAKING A DEFECT FREE FIN BASED DEVICE IN LATERAL EPITAXY OVERGROWTH REGION | 07-14-2016 |
| 20160204037 | INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON | 07-14-2016 |
