| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438427000 | Refilling multiple grooves of different widths or depths | 40 |
| 20080206956 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A method for fabricating a semiconductor device, includes forming a silicon nitride film on a base body, forming a silicon film on said silicon nitride film, forming at least one groove extending from said silicon film to inside of said base body, forming by high-density plasma-enhanced chemical vapor deposition a silicon-containing dielectric film in said groove and on said silicon film in such a way that a silicon-rich layer is formed at a height position spaced apart from said base body within said groove, said silicon-rich layer being higher in silicon content than remaining silicon-containing dielectric film, removing by etching a portion of said silicon-containing dielectric film above said silicon film and a portion of said remaining silicon-containing dielectric film above said silicon-rich layer, if any, and after having removed said silicon-containing dielectric film, removing by etching said silicon-rich layer and said silicon film. | 08-28-2008 |
| 20080213971 | Semiconductor device having dual-STI and manufacturing method thereof - A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved. | 09-04-2008 |
| 20080248627 | Method of Manufacturing Integrated Deep and Shallow Trench Isolation Structures - A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack. | 10-09-2008 |
| 20090111240 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a mask including a first silicon nitride film over a semiconductor substrate, forming a trench in a surface of the semiconductor substrate using the mask, forming a silicon oxide film over the mask to embed the silicon oxide film in the trench, performing a first nitriding treatment to selectively convert a portion of the silicon oxide film above the trench into an oxynitride film, performing a second nitriding treatment of the silicon oxide and oxynitride film to form a second silicon nitride film, and planarizing the first silicon nitride film and second silicon nitride film. | 04-30-2009 |
| 20090162989 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A LAYER SUSPENDED ACROSS A TRENCH - In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth. | 06-25-2009 |
| 20090215242 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a first element isolation trench with a first opening width and a second element isolation trench with a second opening width larger than the first opening width, the first and second element isolation trenches having respective inner surfaces, the second element isolation trench having opposed sidewalls and bottom, a first element-isolating insulation film formed on the inner surfaces of the first and second element isolation trenches, a second element-isolating insulation film formed on the first element-isolating insulation film so as to fill the first element isolation trench and further formed on the first element-isolating insulation film formed on the sidewall of the second element isolation trench, and a third element-isolating insulation film provided on the second element-isolating insulation film and the first element-isolating insulation film formed on the bottom of the second element isolation trench, so as to fill the second element isolation trench. | 08-27-2009 |
| 20100081250 | SEMICONDUCTOR DEVICE HAVING AN OXIDE FILM FORMED ON A SEMICONDUCTOR SUBSTRATE SIDEWALL OF AN ELEMENT REGION AND ON A SIDEWALL OF A GATE ELECTRODE - A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film. | 04-01-2010 |
| 20100105188 | DOUBLE TRENCH FOR ISOLATION OF SEMICONDUCTOR DEVICES - Semiconductor device has a substrate ( | 04-29-2010 |
| 20100144116 | Method of forming high lateral voltage isolation structure involving two separate trench fills - In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench. | 06-10-2010 |
| 20100173470 | Methods of forming a silicon oxide layer and methods of forming an isolation layer - In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a basic material and an oxidant, under a pressure of from about 1.5 atm to about 100 atm. The cured SOG layer may be baked. | 07-08-2010 |
| 20100197109 | METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE - Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed. | 08-05-2010 |
| 20100291750 | METHOD OF FABRICATING FLASH MEMORY DEVICE - A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth. | 11-18-2010 |
| 20100330774 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove. | 12-30-2010 |
| 20110003458 | METHOD OF FORMING DEVICE ISOLATION LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a method of forming a device isolation layer and a method of fabricating a semiconductor device. The method includes: forming a first trench and a second trench in a substrate, wherein the second trench is connected to the first trench and has a width smaller than the first trench; forming a liner insulation layer in the second trench such that the liner insulation layer is buried in the second trench; and forming a gap fill insulation layer on the liner insulation layer such that the gap fill insulation layer is buried in the first trench. | 01-06-2011 |
| 20110059594 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers. | 03-10-2011 |
| 20110124178 | STRUCTURE AND METHOD OF FABRICATING A TRANSISTOR HAVING A TRENCH GATE - An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation. | 05-26-2011 |
| 20110165757 | SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME - A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer. | 07-07-2011 |
| 20110244650 | SEMICONDUCTOR DEVICE WITH STI AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area. | 10-06-2011 |
| 20120276713 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device, which provides an isolation region in which a dense silicon oxide film is formed in a trench that requires high aspect ratio. The method includes forming an isolation trench using, as an etching mask, a nitride mask film formed on a substrate, forming a liner nitride film in the isolation trench, depositing a flowable silazane compound by a CVD method such that the height of the flowable silazane compound is higher than the upper surface of the nitride mask film from the upper portion of the trench, performing heat treatment under an oxidizing atmosphere to convert the flowable silazane compound film into a silicon oxide film and simultaneously densifying therefor, and planarizing the silicon oxide film to the height of the upper surface of the nitride mask film. | 11-01-2012 |
| 20130005115 | Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate - A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed. | 01-03-2013 |
| 20130034949 | METHOD OF FORMING TRENCH ISOLATION - A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure. | 02-07-2013 |
| 20130052795 | TRENCH FILLING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a trench filling method, which includes: forming a silicon oxide liner on a semiconductor substrate with trenches formed therein, the trenches including narrow-width portions having a first minimum isolation width and wide-width portions having a second minimum isolation width being wider than the first minimum isolation width; forming an oxidation-barrier film on the silicon oxide liner; forming a silicon liner on the oxidation-barrier film; filling the narrow-width portions with a first filling material; filling the wide-width portions with a second filling material; and oxidizing the silicon liner. | 02-28-2013 |
| 20130137240 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness. | 05-30-2013 |
| 20130149837 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced. | 06-13-2013 |
| 20130183808 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections. | 07-18-2013 |
| 20130183809 | METHOD OF FABRICATING MEMORY DEVICE - A method of fabricating a memory device comprises forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks. | 07-18-2013 |
| 20130288451 | SOI DEVICE WITH DTI AND STI - A method of forming an SOI structure which includes providing a semiconductor on insulator (SOI) substrate having an SOI layer, an intermediate buried oxide (BOX) layer and a bottom substrate; patterning the SOI layer to form first and second openings in the SOI layer; extending the first openings into the bottom substrate; enlarging the first openings within the bottom substrate; filling the first and second openings with an insulator material to form deep trench isolations (DTIs) from the first openings and shallow trench isolations (STIs) from the second openings; implanting in the bottom substrate between the DTIs to form wells; and forming semiconductor devices in the SOI layer between the DTIs with each semiconductor device being separated from an adjacent semiconductor device by an STI. | 10-31-2013 |
| 20130344678 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first well and a second well formed in a substrate and having a different impurity doping concentration; a first isolation layer and a second isolation layer formed in the first well and the second well, respectively, and having a different depth; and a third isolation layer formed in a boundary region in which the first well and the second well are in contact with each other, and having a combination type of the first isolation layer and the second isolation layer. | 12-26-2013 |
| 20140045317 | Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate - A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed. | 02-13-2014 |
| 20140242775 | METHOD OF FABRICATING FINFETS - The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height. | 08-28-2014 |
| 20140302663 | SEMICONDUCTOR DEVICE WITH ISOLATION LAYER, ELECTRONIC DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE SAME - A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench. | 10-09-2014 |
| 20140349464 | METHOD FOR FORMING DUAL STI STRUCTURE - A method for forming dual shallow trench isolation (STI) structure, which includes a first etching process for forming a deep STI structure in a logic region using a hard mask layer as a mask and a second etching process for forming a shallow STI structure in a pixel region using a photoresist as a mask. Independence between these two etching processes can avoid the prior art problems of double slope profile of the sidewalls of the deep STI structure and a thickness inconsistency of the hard mask layer between on the pixel region and on the logic region. | 11-27-2014 |
| 20150132919 | PHOTOMASK AND METHOD FOR FORMING DUAL STI STRUCTURE BY USING THE SAME - In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench. | 05-14-2015 |
| 20150295029 | PROCESS OF FORMING AN ELECTRONIC DEVICE HAVING A TERMINATION REGION INCLUDING AN INSULATING REGION - An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region. | 10-15-2015 |
| 20150357232 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - One method for manufacturing a semiconductor device includes forming element isolation grooves and an element isolation groove having a width greater than that of the element isolation grooves in the semiconductor substrate, forming insulating films having relatively low fluidity and having upwardly released voids inside the element isolation grooves, and also covering substantially all of the interior surface of the element isolation groove, forming an insulating film having relatively high fluidity, whereby the insulating film is embedded in the interior of the voids, and reforming the insulating film. | 12-10-2015 |
| 20160064234 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height. | 03-03-2016 |
| 20160086843 | Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same - Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed. | 03-24-2016 |
| 20160379894 | Semiconductor Device Structure With 110-PFET and 111-NFET Current Flow Direction - A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned. | 12-29-2016 |
| 438428000 | Reflow of insulator | 2 |
| 20090298257 | DEVICE ISOLATION TECHNOLOGY ON SEMICONDUCTOR SUBSTRATE - A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing. | 12-03-2009 |
| 20110117721 | METHOD OF FORMING ISOLATION LAYER STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME - An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein. | 05-19-2011 |
