| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438425000 | Combined with formation of recessed oxide by localized oxidation | 46 |
| 20080200006 | Method for Forming Shallow Trench Isolation of Semiconductor Device - A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as a mask to form a trench having a vertical sidewall in a portion of the substrate predetermined to be a device isolation region, performing a plasma treatment process on the sidewall of the trench to form a plasma oxide film, forming an oxide film over the resulting structure to fill the trench, and performing a planarization process over the resulting structure. | 08-21-2008 |
| 20080213970 | PROCESS FOR THE FORMATION OF DIELECTRIC ISOLATION STRUCTURES IN SEMICONDUCTOR DEVICES - A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a silicon dioxide deposition treatment to form a second liner layer on the first liner layer. A silicon nitride deposition treatment is also performed to form a third liner layer on the second liner layer. The trench is filled with isolating material. | 09-04-2008 |
| 20080227268 | METHOD OF FORMING AN ISOLATION LAYER IN A SEMICONDUCTOR MEMORY DEVICE - A method of forming an isolation layer in a semiconductor memory device is disclosed. After a trench is formed in a semiconductor substrate, a plasma nitrification annealing process is performed before and preferably after a wall oxide layer is formed to prevent trap charges and degradation problems at the interface and sidewalls of a tunnel insulating layer due to PSZ stress induced in a subsequent process. Accordingly, a variation in the ISPP step can be prevented. | 09-18-2008 |
| 20080227269 | Termination trench structure for mosgated device and process for its manufacture - A process for the fabrication of a MOSgated device that includes a plurality of spaced trenches in the termination region thereof. | 09-18-2008 |
| 20080254593 | Method for Fabricating Isolation Layer in Semiconductor Device - A method of fabricating an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, depositing a high-density plasma (HDP) oxide layer partially filling the trench by supplying an HDP deposition source, etching an overhang generated while the HDP oxide layer is deposited using a fluorine-containing etching gas, depositing a liner HDP oxide layer on the HDP oxide layer by supplying an inert gas and an HDP deposition source such that fluorine (F) is trapped in the liner HDP oxide layer, performing an isotropic etching on an overhang portion of a side surface of the HDP oxide layer using the fluorine (F) trapped in the liner HDP oxide layer, and forming an HDP capping layer on the liner HDP oxide layer to fill a remaining portion of the trench. | 10-16-2008 |
| 20080286935 | METHOD OF FABRICATING AN ISOLATION SHALLOW TRENCH - A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench. | 11-20-2008 |
| 20080299740 | METHOD FOR FORMING STI STRUCTURE - A method for forming a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate, having a trench-like opening therein exposing a portion of the substrate. A thermal oxidation process is performed to the substrate. An anisotropic etching process is performed using the patterned mask layer as a mask to form a trench in the substrate, and then the trench is filled with an insulating material. | 12-04-2008 |
| 20080299741 | Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation - An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide. | 12-04-2008 |
| 20080305611 | COATING COMPOSITION FOR FORMING OXIDE FILM AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE USING THE SAME - A coating composition for forming an oxide film, which can suppress the phenomenon of an increased wet etching rate caused by a part of the SOG film embedded inside a groove becoming low-density, and which can suppress the volume expansion coefficient to a low level, and a method for producing a semiconductor device using the same are provided. An oxide film is formed inside a groove by: coating a coating composition for forming an oxide film, which contains a polysilazane or a hydrogenated silsesquioxane, and a polysilane, on a substrate having a groove; and thereafter heat treatment in an oxidizing atmosphere. This method is suitable for forming a device isolation region and a wiring interlayer dielectric film. | 12-11-2008 |
| 20090004815 | Method for Manufacturing Semiconductor Device - Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to prevent generation of a void when a device isolation structure is formed by a Shallow Trench Isolation (STI) method, and to prevent formation of stress between the semiconductor substrate and the FOX. | 01-01-2009 |
| 20090004816 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method of forming an isolation layer in a semiconductor device using rapid vapor deposition to fill in a trench of the semiconductor device comprises forming a hydrophilic layer on the trench and forming a hydrophobic layer on a region other than the trench, and selectively forming a buried insulating layer in the trench using a catalytic reaction of the hydrophilic layer. | 01-01-2009 |
| 20090029522 | Method of Forming Isolation Layer of Semiconductor Device - A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material. | 01-29-2009 |
| 20090029523 | Method of Fabricating Flash Memory Device - The invention relates to a method of fabricating flash memory device. In accordance with an aspect of the invention, the method includes forming a gate insulating layer, a first conductive layer, and an isolation mask over a semiconductor substrate. The isolation mask is patterned to expose regions in which an isolation layer will be formed. The first conductive layer, the gate insulating layer, and the semiconductor substrate are etched using the patterned isolation mask to form trenches. A liner oxide layer is formed on the resulting structure including the trenches. The trenches in which the liner oxide layer is formed are filled with an insulating layer. A planarizing process and a cleaning process are carried out such that wing spacers covering the gate insulating layer are formed at top edge portions of the isolation layer, thereby forming the isolation layer. | 01-29-2009 |
| 20090035917 | METHOD FOR FORMING DEVICE ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE USING ANNEALING STEPS TO ANNEAL FLOWABLE INSULATION LAYER - A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern. | 02-05-2009 |
| 20090068816 | METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - Provided is a method for forming an isolation layer in a semiconductor device. In the method, a trench is formed in a semiconductor substrate, and a liner layer is formed on an exposed surface of the trench. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buffer layer is formed on a portion of the liner layer that is formed on a sidewall of the trench and exposed after the flowable insulation layer is recessed. The buffer layer is etched to smoothen a rough portion of the liner layer that is formed when the flowable insulation layer is recessed. A buried insulation layer is deposited in the trench. | 03-12-2009 |
| 20090068817 | METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buried insulation layer is deposited on the flowable insulation layer while keeping a deposition sputtering rate (DSR) below about 22 so as to fill the trench with the buried insulation layer while restraining the buried insulation layer from growing on a lateral portion of the trench. | 03-12-2009 |
| 20090111238 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF INCREASING CURRENT DRIVABILITY OF PMOS TRANSISTOR - A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate. | 04-30-2009 |
| 20090148999 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed. | 06-11-2009 |
| 20090170279 | METHOD OF PREPARING ACTIVE SILICON REGIONS FOR CMOS OR OTHER DEVICES - A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate ( | 07-02-2009 |
| 20090170280 | Method of Forming Isolation Layer of Semiconductor Device - A method of forming isolation layers of a semiconductor device, comprising providing a semiconductor substrate in which a tunnel dielectric layer and a conductive layer are formed in active regions having two ends and trenches are formed in isolation regions; rounding both ends of each active region by performing an O | 07-02-2009 |
| 20090170281 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR - The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer. | 07-02-2009 |
| 20090286380 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device includes forming an oxide film uniformly in a trench in the device isolation by, for example, a radical oxidation process. The method also includes increasing the thickness of the oxide film positioned at recess sidewalls by forming a gate oxide film. Manufacturing the device according to this method will prevent junction leakage and maintain a gate oxidation intensity characteristic that will improve the refresh characteristic of the device. | 11-19-2009 |
| 20110104868 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device include the following processes. A groove is formed in a semiconductor substrate. A first insulating film is formed on a bottom surface of the groove and a second insulating film on a side surface of the groove. The second insulating film is thinner than the first insulating film. A conductive layer is formed on the first insulating film. | 05-05-2011 |
| 20110136318 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING OPTICAL DEVICES - Provided is a method of manufacturing a semiconductor device. According to the method, a first buried oxide layer is formed in the semiconductor substrate in a first region, such that a first semiconductor layer is defined on the first buried oxide layer. An active portion is defined by forming a trench in the semiconductor substrate in a second region. A capping semiconductor pattern is formed on a top surface and an upper portion of a sidewall of the active portion. An oxide layer is formed by oxidizing the capping semiconductor pattern and an exposed lower portion of the sidewall of the active portion, such that the oxide layer surrounds a non-oxidized portion of the active portion. The non-oxidized portion of the active portion is a core and one end of the core is connected to a first optical device formed at the first semiconductor. | 06-09-2011 |
| 20110244649 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: a process to form an element isolation trench on a semiconductor substrate, the element isolation trench having a crystal plane orientation that is different from a crystal plane orientation on a surface of the semiconductor substrate; a process to deposit, on the semiconductor substrate, one of a metal that promotes generation of oxygen radicals and a metal containing film that promotes generation of the oxygen radicals; a process to oxidize the semiconductor substrate; and a process to remove the one of the metal and the metal containing film. | 10-06-2011 |
| 20110263094 | METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION - A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner. | 10-27-2011 |
| 20110300689 | Methods of Forming Trench Isolation in the Fabrication of Integrated Circuitry and Methods of Fabricating Integrated Circuitry - First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material. The spin-on-dielectric is densified within the second isolation trench. | 12-08-2011 |
| 20120028437 | TRENCH-FILLING METHOD AND FILM-FORMING SYSTEM - A method of filling a trench comprises heating a semiconductor substrate having a trench formed therein and an oxide film formed at least on the sidewall of the trench and supplying an aminosilane gas to the surface of the substrate so as to form a seed layer on the semiconductor substrate, heating the semiconductor substrate having the seed layer formed thereon and supplying a monosilane gas to the surface of the seed layer so as to form a silicon film on the seed layer, filling the trench of the semiconductor substrate, which has the silicon film formed thereon, with a filling material that shrinks by burning, and burning the semiconductor substrate coated by the filling material filling the trench in an atmosphere containing water and/or a hydroxy group while changing the filling material into a silicon oxide and changing the silicon film and the seed layer into a silicon oxide. | 02-02-2012 |
| 20120208346 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO | 08-16-2012 |
| 20130005114 | METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL - Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin. | 01-03-2013 |
| 20130143386 | METHOD OF FILLING SHALLOW TRENCHES - A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced. | 06-06-2013 |
| 20130164909 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask. | 06-27-2013 |
| 20140106539 | SEMICONDUCTOR ISOLATION STRUCTURE AND METHOD OF MANUFACTURE - A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described. | 04-17-2014 |
| 20140308798 | Multiple-Time Programming Memory Cells and Methods for Forming the Same - A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess. | 10-16-2014 |
| 20140322891 | METHOD OF FORMING SHALLOW TRENCH ISOLATIONS - A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer. | 10-30-2014 |
| 20150294901 | LOCALIZED REGION OF ISOLATED SILICON OVER RECESSED DIELECTRIC LAYER - An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer. | 10-15-2015 |
| 20160005640 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. | 01-07-2016 |
| 20160086840 | Isolation Structure of Semiconductor Device - The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench. | 03-24-2016 |
| 20160190238 | NON-PLANAR SEMICONDUCTOR DEVICE WITH ASPECT RATIO TRAPPING - As disclosed herein, a semiconductor device with aspect ratio trapping including, a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The size of the gaps between the isolation pillars is selected to statistically eliminate defects caused by a lattice mismatch between the bulk substrate and the oxide layer. The semiconductor device may also contain an aspect-ratio trapping layer between the bulk substrate and oxide layer. | 06-30-2016 |
| 438426000 | Recessed oxide laterally extending from groove | 7 |
| 20080220586 | METHODS FOR FORMING SEMICONDUCTOR STRUCTURES WITH BURIED ISOLATION COLLARS AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS - A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls. | 09-11-2008 |
| 20090111239 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes determining an active region in a semiconductor substrate, forming a recess in a gate region crossing over the active region, annealing an oxide layer formed in the recess to oxidize the active region in the gate region, and etching the active region by using the oxidized active region as an etch mask. | 04-30-2009 |
| 20090155978 | Recessed Shallow Trench Isolation - In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. | 06-18-2009 |
| 20090181516 | Method of Forming Isolation Layer of Semiconductor Device - A method of forming an isolation layer of a semiconductor device is disclosed. In the method according to one aspect, a semiconductor substrate having a trench formed therein is provided. A first insulating layer is formed over an entire surface of the semiconductor substrate including a surface of the trench. A passivation layer, preferably silicon, including oxygen is formed on a surface of the first insulating layer. A second insulating layer is formed on the passivation layer formed within the trench. | 07-16-2009 |
| 20090186463 | METHOD FOR MANUFACTURING SOI STRUCTURE IN DESIRED REGION OF A SEMICONDUCTOR DEVICE - Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed. | 07-23-2009 |
| 20130288450 | SHALLOW TRENCH FORMING METHOD - A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO | 10-31-2013 |
| 20140065795 | METHOD FOR FORMING TRENCH ISOLATION - A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench. | 03-06-2014 |
