| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438404000 | Total dielectric isolation | 64 |
| 20080311724 | TFD LCD PANEL - Active devices in a thin film diode (TFD) liquid crystal display (LCD) panel used to control liquid crystal are formed by a metal layer, a transparent conductive layer, and an insulating layer sequentially on a substrate, wherein the metal layer is used as transmitting signal and the transparent conductive layer is used as bottom metal layer of metal-insulator-metal (MIM) thin film diode. The metal layer, the transparent conductive layer, and the insulating layer are defined with desired patterns. Further, a dielectric layer is formed over the substrate, metal layer, the transparent conductive layer, and the insulating layer, and defined to form the locations of electrode terminal and MIM thin film diode by using lithographic process. Next, another transparent conductive layer is formed on the dielectric layer and defined to form a pixel electrode and top metal layer of the MIM thin film diode by using lithographic process. | 12-18-2008 |
| 20090269903 | METHODS FOR FABRICATING ACTIVE DEVICES ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE UTILIZING MULTIPLE DEPTH SHALLOW TRENCH ISOLATIONS - Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer. | 10-29-2009 |
| 20090311845 | One Transistor Memory Cell with Bias Gate - One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held. | 12-17-2009 |
| 20100167492 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer. | 07-01-2010 |
| 20110201171 | Processes For Forming Isolation Structures For Integrated Circuit Devices - Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 08-18-2011 |
| 20110244648 | Method of Manufacturing Nonvolatile Memory Device - In one embodiment of a method of manufacturing a nonvolatile memory device, a tunnel insulating layer and a charge trap layer are first formed over a semiconductor substrate that defines active regions and isolation regions. The tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions are etched to form trenches for isolation in the respective isolation regions. The trenches for isolation are filled with an insulating layer to form isolation layers in the respective trenches. A lower passivation layer is formed over an entire surface including top surfaces of the isolation layers. A first oxide layer is formed over an entire surface including the lower passivation layer. Meta-stable bond structures within the lower passivation layer are changed to stable bonds. A nitride layer, a second oxide layer, and an upper passivation layer are sequentially formed over an entire surface including the first oxide layer. | 10-06-2011 |
| 20110306177 | METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE - A method is described for reducing dielectric overetch. The method includes: ( | 12-15-2011 |
| 20110312154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, and the side face of the conductive pattern comprises a notch. | 12-22-2011 |
| 20120009759 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING SHARED BIT LINE STRUCTURE - A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions. | 01-12-2012 |
| 20120108032 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH STRESSED TRENCH ISOLATION - A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S | 05-03-2012 |
| 20120171841 | BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (Å). This results in a lower parasitic capacitance at the body contact region. | 07-05-2012 |
| 20120276710 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area. | 11-01-2012 |
| 20130230965 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of a semiconductor device includes forming a lower mask film on a semiconductor substrate. The method includes forming a barrier film in a first area. The method includes forming an upper mask film. The method includes removing an upper mask member and leaving a lower mask member in the first area and removing the upper mask member and the lower mask member in the second area. The removing is performed by etching in a condition in which an etching rate of the upper mask member and an etching rate of the lower mask member are higher than that of the barrier member. The method includes forming a conductive film. The method includes selectively removing the conductive film by performing etching in a condition in which an etching rate of the conductive film is higher than that of the lower mask member. | 09-05-2013 |
| 20140024198 | POST-GATE ISOLATION AREA FORMATION FOR FIN FIELD EFFECT TRANSISTOR DEVICE - A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins. | 01-23-2014 |
| 20140051225 | TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES - Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided. | 02-20-2014 |
| 20140141591 | Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability - A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride. | 05-22-2014 |
| 20140363949 | Electrical Signal Isolation in Semiconductor Structures - Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer. | 12-11-2014 |
| 20150024572 | PROCESS FOR FACILTIATING FIN ISOLATION SCHEMES - Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures. | 01-22-2015 |
| 20150031187 | METHODS FOR FORMING A ROUND BOTTOM SILICON TRENCH RECESS FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl | 01-29-2015 |
| 20150132918 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer. | 05-14-2015 |
| 20160163546 | 3D MATERIAL MODIFICATION FOR ADVANCED PROCESSING - Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes. | 06-09-2016 |
| 20160181147 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 06-23-2016 |
| 20160254177 | SEMICONDUCTOR DEVICE WITH VOIDS WITHIN SILICON-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE | 09-01-2016 |
| 20170236870 | Integrated Circuit System With Memory Support And Method Of Manufacture Thereof | 08-17-2017 |
| 438405000 | And separate partially isolated semiconductor regions | 2 |
| 20090011568 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE THEREOF AND SEMICONDUCTOR INTEGRATED CIRCUIT - An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region. | 01-08-2009 |
| 20140377935 | Selective Amorphization for Signal Isolation and Linearity - Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer. | 12-25-2014 |
| 438406000 | Bonding of plural semiconductive substrates | 19 |
| 20080254591 | Method for Making a Thin-Film Element - A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed. | 10-16-2008 |
| 20080261376 | Method of manufacturing SOI substrate - To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOI substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered. | 10-23-2008 |
| 20080280416 | Techniques for Layer Transfer Processing - Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided. | 11-13-2008 |
| 20090004811 | Semiconductor composite device, method for manufacturing the semiconductor composite device, led head that employs the semiconductor composite device, and image forming apparatus that employs the led head - A semiconductor composite apparatus includes a semiconductor thin film and a metal layer formed on a substrate. The semiconductor thin film is bonded to the metal layer formed on the substrate. A region is formed between the semiconductor thin film and the metal surface, and contains an oxide of a metal that forms the metal surface. The metal surface is a surface of a metal layer provided on the substrate. The metal surface contains an element selected from the group consisting of Pd, Ni, Ge, Pt, Ti, Cr, and Au. The metal surface is coated with either a Pd layer or an Ni layer. | 01-01-2009 |
| 20090023267 | METHOD OF REDUCING ROUGHNESS OF A THICK INSULATING LAYER - A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cm | 01-22-2009 |
| 20090042356 | Peeling Method and Method of Manufacturing Semiconductor Device - There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer ( | 02-12-2009 |
| 20090061591 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A hydrogen ion-implanted layer is formed on the surface side of a first substrate which is a single-crystal silicon substrate. At least one of the surface of a second substrate, which is a transparent insulating substrate, and the surface of the first substrate is subjected to surface activation treatment, and the two substrates are bonded together. The bonded substrate composed of the single-crystal Si substrate and the transparent insulating substrate thus obtained is mounted on a susceptor and is placed under an infrared lamp. Light having a wave number range including an Si—H bond absorption band is irradiated at the bonded substrate for a predetermined length of time to break the Si—H bonds localized within a “microbubble layer” in the hydrogen ion-implanted layer, thereby separating a silicon thin film layer. | 03-05-2009 |
| 20090075453 | METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE - There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer. | 03-19-2009 |
| 20090081844 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A plurality of single crystal semiconductor substrates are arranged and then the plurality of single crystal semiconductor substrates which have been arranged are overlapped with a base substrate, so that the base substrate and the plurality of single crystal semiconductor substrates are bonded to each other. Then, each of the plurality of single crystal semiconductor substrates is separated to form a plurality of single crystal semiconductor layers over the base substrate. Next, in order to reduce crystal defects in the plurality of single crystal semiconductor layers, the plurality of single crystal semiconductor layers are irradiated with a laser beam. The plurality of single crystal semiconductor layers are thinned by being etched before or after irradiation with a laser beam. | 03-26-2009 |
| 20090081845 | MANUFACTURING METHOD OF SUBSTRATE PROVIDED WITH SEMICONDUCTOR FILMS - A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate. | 03-26-2009 |
| 20090098704 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A method is demonstrated to manufacture SOI substrates with high throughput while resources can be effectively used. The present invention is characterized by the feature in which the following process A and process B are repeated. The process A includes irradiation of a surface of a semiconductor wafer with cluster ions to form a separation layer in the semiconductor wafer. The semiconductor wafer and a substrate having an insulating surface are then overlapped with each other and bonded, which is followed by thermal treatment to separate the semiconductor wafer at or around the separation layer. A separation wafer and an SOI substrate which has a crystalline semiconductor layer over the substrate having the insulating surface are simultaneously obtained by the process A. The process B includes treatment of the separation wafer for reusing, which allows the separation wafer to be successively subjected to the process A. | 04-16-2009 |
| 20090104750 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE - If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate. | 04-23-2009 |
| 20090111236 | METHOD FOR MANUFACTURING SOI SUBSTRATE - An object is to reduce occurrence of defective bonding between a base substrate and a semiconductor substrate even when a silicon nitride film or the like is used as a bonding layer. Another object is to provide a method for manufacturing an SOI substrate by which an increase in the number of steps can be suppressed. A semiconductor substrate and a base substrate are prepared; an oxide film is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form a separation layer at a predetermined depth from a surface of the semiconductor substrate; a nitrogen-containing layer is formed over the oxide film after the ion irradiation; the semiconductor substrate and the base substrate are disposed opposite to each other to bond a surface of the nitrogen-containing layer and a surface of the base substrate to each other; and the semiconductor substrate is heated to cause separation along the separation layer, thereby forming a single crystal semiconductor layer over the base substrate with the oxide film and the nitrogen-containing layer interposed therebetween. | 04-30-2009 |
| 20090111237 | Method for manufacturing semiconductor substrate - A consistent reduction in temperature in an SOI substrate manufacturing process is achieved. | 04-30-2009 |
| 20090117703 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor substrate is provided, which includes a step of forming a buffer layer over a first semiconductor substrate, a step of forming a damaged region in the first semiconductor substrate by irradiating the first semiconductor substrate with ions, a step of bonding the first semiconductor substrate and a second semiconductor substrate with the buffer layer interposed between, a step of separating the first semiconductor substrate with a single crystal semiconductor layer left over the second semiconductor substrate by heating the first semiconductor substrate and the second semiconductor substrate, and a step of irradiating the single crystal semiconductor layer with a laser beam and heating the single crystal semiconductor layer. | 05-07-2009 |
| 20090117704 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - As a base substrate, a substrate having an insulating surface such as a glass substrate is used. Then, a single crystal semiconductor layer is formed over the base substrate with the use of a large-sized semiconductor substrate. Note that, it is preferable that the base substrate be provided with a plurality of single crystal semiconductor layers. After that, the single crystal semiconductor layers are cut to divide the single crystal semiconductor layers into a plurality of single crystal semiconductor regions by patterning. Next, the single crystal semiconductor regions are irradiated with laser light or heat treatment is performed on the single crystal semiconductor regions in order to improve the planarity of surfaces and reduce defects. Peripheral portions of the single crystal semiconductor regions are not used as semiconductor elements, and central portions of the single crystal semiconductor regions are used as the semiconductor elements. | 05-07-2009 |
| 20090181514 | HEAT TREATMENT APPARATUS AND METHOD FOR MANUFACTURING SOI SUBSTRATE USING THE HEAT TREATMENT APPARATUS - A heat treatment apparatus is disclosed, which enables suppression of a warp of a base substrate to which a plurality of single crystal semiconductor substrates are bonded. An example of the apparatus comprises a treatment chamber, a supporting base provided in the treatment chamber, a plurality of supports which are provided over the supporting base and are arranged to support the base substrate, and a heating unit for heating the base substrate, where each position of the plurality of supports can be changed over the supporting base. The use of this apparatus contributes to the reduction in the region where the base substrate and the supports are in contact with each other, which allows uniform heating of the base substrate, leading to the formation of an SOI substrate with high quality. | 07-16-2009 |
| 20090286379 | METHOD OF MANUFACTURING IMPRINT SUBSTRATE AND IMPRINTING METHOD - In a method of manufacturing an imprint substrate, a concave pattern, which is recessed, is formed on a top surface of the mold substrate. A light blocking layer is formed on the concave pattern and the top surface of the mold substrate. After bonding an adhesive substrate to the mold substrate such that the adhesive substrate faces the mold substrate, the adhesive substrate is separated from the mold substrate, so that the light blocking layer on the top surface is removed from the mold substrate. An imprint substrate having the light blocking layer only on the concave pattern is formed. | 11-19-2009 |
| 20100144111 | PROCESS FOR PRODUCTION OF SOI SUBSTRATE AND PROCESS FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands. | 06-10-2010 |
| 438407000 | Nondopant implantation | 3 |
| 20080318390 | Method for fabricating semiconductor device and semiconductor device - A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer. | 12-25-2008 |
| 20090042357 | Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks - A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk-silicon that is latch-up immune. | 02-12-2009 |
| 20150294903 | METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS - A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region. | 10-15-2015 |
| 438408000 | With electrolytic treatment step | 2 |
| 20110097870 | METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS - A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer. | 04-28-2011 |
| 438409000 | Porous semiconductor formation | 1 |
| 20080206952 | Silicon Substrate Processing Method - In a thin film forming step S | 08-28-2008 |
| 438410000 | Encroachment of separate locally oxidized regions | 1 |
| 20080233708 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a semiconductor substrate; forming a first groove penetrating the first semiconductor layer and the second semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; forming a support covering the second semiconductor layer from inside of the first groove to a surface of the second semiconductor layer so as to support the second semiconductor layer; etching a sidewall formed in the first groove of the support so as to render the sidewall thin; forming a second groove exposing the first semiconductor layer by sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer; forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the second groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; and forming a buried oxide film by thermally oxidizing an upper surface of the semiconductor substrate and a lower surface of the second semiconductor layer that are facing inside of the cavity. | 09-25-2008 |
| 438411000 | Air isolation (e.g., beam lead supported semiconductor islands, etc.) | 3 |
| 20120208344 | CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION COMPRISING INORGANIC PARTICLES AND POLYMER PARTICLES - A chemical mechanical polishing (CMP) composition, comprising (A) at least one type of inorganic particles which are dispersed in the liquid medium (C), (B) at least one type of polymer particles which are dispersed in the liquid medium (C), (C) a liquid medium, wherein the zeta-potential of the inorganic particles (A) in the liquid medium (C) and the zeta-potential of the polymer particles in the liquid medium (C) are of same signs. | 08-16-2012 |
| 438412000 | Semiconductor islands formed upon insulating substrate or layer (e.g., mesa isolation, etc.) | 2 |
| 20140370686 | SOI Structure for Signal Isolation and Linearity - Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer. | 12-18-2014 |
| 20160379895 | FORMATION OF STRAINED FINS IN A FINFET DEVICE - In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material. | 12-29-2016 |
| 438413000 | With epitaxial semiconductor formation | 10 |
| 20080206953 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method including: (a) forming a protection film on the semiconductor substrate in the bulk region; (b) exposing a surface of the semiconductor substrate in the silicon-on-insulator region from under the protection film; (c) forming a first semiconductor layer and subsequently a second semiconductor layer on the semiconductor substrate in the silicon-on-insulator region and in the bulk region, using an epitaxy method after the step (a); (d) etching the first semiconductor layer and the second semiconductor layer partially, so as to form a first trench which exposes a side surface of the first semiconductor layer in the silicon-on-insulator region; (e) etching the first semiconductor layer through the first trench with an etching condition in which the first semiconductor layer is easier to be etched than the second semiconductor layer, so as to form a cavity between the semiconductor substrate and the second semiconductor layer in the silicon-on-insulator region; and (f) forming a buried insulating film inside the cavity. | 08-28-2008 |
| 20080227264 | VERTICAL NANOTUBE SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING THE SAME - Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate. | 09-18-2008 |
| 20090035914 | ISOLATION TRENCH PROCESSING FOR STRAIN CONTROL - A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures may be formed, e.g., by epitaxy, on sidewalls of the trench. The structures may be silicon or a silicon compound, e.g., silicon germanium. During the thermal oxidation, the semiconductor structures are consumed. In the case of a silicon germanium, the germanium may diffuse during the thermal oxidation to produce a silicon germanium channel region. | 02-05-2009 |
| 20090181515 | Selective germanium deposition for pillar devices - A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device. | 07-16-2009 |
| 20100190316 | METHOD OF SELECTIVE OXYGEN IMPLANTATION TO DIELECTRICALLLY ISOLATE SEMICONDUCTOR DEVICES USING NO EXTRA MASKS - A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk silicon that is latch-up immune. | 07-29-2010 |
| 20110081764 | METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL - Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin. | 04-07-2011 |
| 20130071993 | Preparation Method for Full-Isolated SOI with Hybrid Crystal Orientations - A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer. The top silicon and the insulating buried layer formed in the method have uniform and controllable thickness, the strained silicon formed in the window and the top silicon outside the window have different crystal orientations, so as to provide higher mobility for the NMOS and the PMOS respectively, thereby improving the performance of the CMOS IC. | 03-21-2013 |
| 20140051226 | GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 02-20-2014 |
| 20150056781 | GATE LENGTH INDEPENDENT SILICON-ON-NOTHING (SON) SCHEME FOR BULK FINFETS - Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate. | 02-26-2015 |
| 20160379866 | Isolated Semiconductor Layer Over Buried Isolation Layer - An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate. | 12-29-2016 |
