Class / Patent application number | Description | Number of patent applications / Date published |
438308000 | Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.) | 32 |
20080233703 | POLYSILICON CONDUCTIVITY IMPROVEMENT IN A SALICIDE PROCESS TECHNOLOGY - An electronic device and method for forming same. The electronic device includes a source and drain region. Each region has an uppermost portion comprised of a first silicide where the first silicide is overlaid with a first dielectric layer. The electronic device further includes a gate region having an uppermost portion comprised of a second silicide. The second silicide is both thicker than the first silicide and has a lower resistivity than the first silicide with at least a portion of the second silicide being formed in an opening in the first dielectric layer. | 09-25-2008 |
20080254588 | METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM - A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %. | 10-16-2008 |
20080268603 | TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation. | 10-30-2008 |
20080293208 | METHOD OF FABRICATING OXIDE SEMICONDUCTOR DEVICE - A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray. | 11-27-2008 |
20080305600 | METHOD AND APPARATUS FOR FABRICATING HIGH TENSILE STRESS FILM - A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature. | 12-11-2008 |
20080305601 | METHOD FOR FORMING SEMICONDUCTOR DEVICE USING MULTI-FUNCTIONAL SACRIFICIAL DIELECTRIC LAYER - A composite dielectric layer including a nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The need to form and remove two separate dielectric material layers is obviated. The nitride layer protects the oxide layer to alleviate oxide damage during a pre-silicidation PAI (pre-amorphization implant) process thereby preventing oxide attack during a subsequent HF dip operation and preventing nickel silicide spiking through the attacked oxide layer during silicidation. | 12-11-2008 |
20090011566 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - After gate insulating films, gate electrodes, and n | 01-08-2009 |
20090042352 | GATE INTERFACE RELAXATION ANNEAL METHOD FOR WAFER PROCESSING WITH POST-IMPLANT DYNAMIC SURFACE ANNEALING - Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration. | 02-12-2009 |
20090042353 | INTEGRATED CIRCUIT FABRICATION PROCESS FOR A HIGH MELTING TEMPERATURE SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing. | 02-12-2009 |
20090042354 | INTEGRATED CIRCUIT FABRICATION PROCESS USING A COMPRESSION CAP LAYER IN FORMING A SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature. | 02-12-2009 |
20090162985 | Method of Fabricating Semiconductor Device - Methods of fabricating a semiconductor device are provided. An insulating layer can be formed on a semiconductor substrate, a sacrificial layer can be formed on the insulating layer, and a trench can be formed in the sacrificial layer. A first gate material layer can be formed on the sacrificial layer and in the trench, and a second gate material layer can be formed on the first gate material layer. A gate electrode can be formed by reacting the first gate material layer and the second gate material layer. | 06-25-2009 |
20100068862 | SEMICONDUCTOR DEVICE HAVING A ROUND-SHAPED NANO-WIRE TRANSISTOR CHANNEL AND METHOD OF MANUFACTURING SAME - A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape. | 03-18-2010 |
20100081247 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film an a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter. | 04-01-2010 |
20100330764 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer,
| 12-30-2010 |
20110020997 | NOISE REDUCTION IN SEMICONDUCTOR DEVICES - An integrated circuit and method of making it, includes a semiconductor substrate and a support layer disposed on the semiconductor substrate. A gate insulator including a support layer doped using a noise-reducing dopant can be disposed on the semiconductor substrate. A gate stack can be disposed on the gate insulator. | 01-27-2011 |
20110223737 | IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS - Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing. | 09-15-2011 |
20110237042 | Methods Utilizing Microwave Radiation During Formation Of Semiconductor Constructions - Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation. | 09-29-2011 |
20110269288 | Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts - The invention included to methods of forming CoSi | 11-03-2011 |
20120021585 | METHOD OF MANUFACTURING POLYCRYSTALLINE SILICON LAYER, AND METHOD OF MANUFACTURING TRANSISTOR HAVING THE POLYCRYSTALLINE SILICON LAYER - An embodiment is directed to a method of manufacturing a polycrystalline silicon layer, the method including providing a crystallization substrate, the crystallization substrate having an amorphous silicon layer on a first substrate, providing a reflection substrate, the reflection substrate having a first region with a reflection panel therein and a second region without the reflection panel, disposing the crystallization substrate and the reflection substrate on one another, and selectively crystallizing the amorphous silicon layer by directing a laser beam onto the crystallization substrate and the reflection substrate, and reflecting the laser beam from the reflection panel. | 01-26-2012 |
20120088346 | THIN FILM TRANSISTORS IN PIXEL AND DRIVING PORTIONS CHARACTERIZED BY SURFACE ROUGHNESS - A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size. The thin film transistor includes: a substrate including a pixel portion and a driver portion; a first semiconductor layer disposed in the pixel portion and having a first surface roughness; and a second semiconductor layer disposed in the driver portion and having a second surface roughness smaller than the first surface roughness. | 04-12-2012 |
20120122288 | METHOD OF FABRICATING A SILICIDE LAYER - During a salicide process, and before a second thermal treatment is performed to a silicide layer of a semiconductor substrate, a thermal conductive layer is formed to cover the silicide layer. The heat provided by the second thermal treatment can be conducted to the silicide layer uniformly through the thermal conductive layer. The thermal conductive layer can be a CESL layer, TiN, or amorphous carbon. Based on different process requirements, the thermal conductive layer can be removed optionally after the second thermal treatment is finished. | 05-17-2012 |
20120164810 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced. | 06-28-2012 |
20120164811 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, WIRING AND SEMICONDUCTOR DEVICE - In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film. | 06-28-2012 |
20130143378 | METHOD OF FORMING POLYSILICON LAYER AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE POLYSILICON LAYER - In one aspect, a method of forming a polysilicon (poly-Si) layer and a method of manufacturing a thin film transistor (TFT) using the poly-Si layer is provided. In one aspect, the method of forming a polysilicon (poly-Si) layer includes forming an amorphous silicon (a-Si) layer on a substrate in a chamber; cleaning the chamber; removing fluorine (F) generated while cleaning the chamber; forming a metal catalyst layer for crystallization, on the a-Si layer; and crystallizing the a-Si layer into a poly-Si layer by performing a thermal processing operation. | 06-06-2013 |
20140120682 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced. | 05-01-2014 |
20140127874 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈ | 05-08-2014 |
20140287565 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) providing a substrate ( | 09-25-2014 |
20140363944 | Aqua Regia and Hydrogen Peroxide HCl Combination to Remove Ni and NiPt Residues - A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate. | 12-11-2014 |
20160027885 | FIELD-EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF - A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer. | 01-28-2016 |
20160118471 | MECHANISM FOR FORMING METAL GATE STRUCTURE - A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively. | 04-28-2016 |
20160126102 | DIRECTIONAL PRE-CLEAN IN SILICIDE AND CONTACT FORMATION - A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer. | 05-05-2016 |
20160254155 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 09-01-2016 |