| Entries |
| Document | Title | Date |
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| 20080200000 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - After the formation of element isolation insulating films, an n-well, and a p-well on a Si substrate, the Si substrate is subjected to cleaning (step S | 08-21-2008 |
| 20080206947 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first silicon oxide film on a surface of a silicon substrate or on a surface of a gate electrode when a silicon nitride film for a dummy side wall is etched off, to provide a protection for such surfaces, and then etching a portion of the silicon nitride film with a chemical solution, and then a second oxide film for supplementing a simultaneously-etched portion of the first silicon oxide film is formed, and eventually performing an etching for completely removing the silicon nitride film for the dummy side wall. | 08-28-2008 |
| 20080227260 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH THIN GATE SPACER - A method for fabricating a transistor. A substrate having a gate electrode thereon and insulated therefrom is provided. A first gate spacer with a first dielectric material is formed on the sidewalls of the gate electrode. A liner with a second dielectric material is formed on the upper surfaces of the substrate, the first gate spacer and the gate electrode, wherein the first dielectric material has an etching selectivity relative to the second dielectric material. Ion implantation is performed on the substrate to form source/drain regions in the substrate and substantially self-aligned with the liner on the first gate spacer. The liner is removed from the upper surfaces of the gate electrode and the source/drain regions. A method for fabricating a semiconductor device is also disclosed. | 09-18-2008 |
| 20080233702 | Method of forming a recess in a semiconductor structure - One embodiment of the present invention relates to a method of processing a semiconductor device. During the method an amorphization implant is performed to amorphize a selected region of a semiconductor structure. The amorphized selected region is then removed by performing a recess etch that is selective thereto. Other methods and systems are also disclosed. | 09-25-2008 |
| 20080261370 | Semiconductor device and method of fabricating the same - According to the present invention, there is provided a semiconductor device fabrication method comprising:
| 10-23-2008 |
| 20080286932 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device may include the steps of: forming a doped polysilicon film by implanting or incorporating dopant ions simultaneously with forming a silicon film; forming a doped polysilicon pattern by patterning the doped polysilicon film; forming a spacer on sides of the doped polysilicon pattern; and forming source and drain regions using the polysilicon pattern and the spacer as a mask. | 11-20-2008 |
| 20080305598 | ION IMPLANTATION DEVICE AND A METHOD OF SEMICONDUCTOR MANUFACTURING BY THE IMPLANTATION OF IONS DERIVED FROM CARBORANE MOLECULAR SPECIES - An ion implantation device and a method of manufacturing a semiconductor device is described, wherein ionized carborane cluster ions are implanted into semiconductor substrates to perform doping of the substrate. The carborane cluster ions have the chemical form C | 12-11-2008 |
| 20080305599 | Gate Control and Endcap Improvement - A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed. | 12-11-2008 |
| 20090011565 | Field effect transistor structure with abrupt source/drain junctions - Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type. | 01-08-2009 |
| 20090023262 | Method for fabricating semiconductor device - To provide a fine transistor of high precision. A method for fabricating a transistor comprises the step of forming a gate electrode ( | 01-22-2009 |
| 20090029516 | METHOD TO IMPROVE TRANSISTOR TOX USING HIGH-ANGLE IMPLANTS WITH NO ADDITIONAL MASKS - A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area. | 01-29-2009 |
| 20090155972 | Method of producing semiconductor memory - A semiconductor memory includes a plurality of memory cell transistors each having a laminated gate. A method of producing the semiconductor memory includes the steps of: forming a plurality of element separation regions for separating the memory cell transistors; forming a first conductive layer through a gate oxide film; etching the first conductive layer to form a plurality of slits; forming spacers on sidewall portions of each of the slits; forming a second conductive layer through an insulating film; etching the first conductive layer, the second conductive layer, and the insulating film using one single mask to form the laminated gate; implanting a conductive impurity into the semiconductor substrate exposed on both sides of the laminated gate to form a drain/source region; forming an interlayer insulating film; forming a contact hole penetrating the interlayer insulating film to reach the semiconductor substrate. | 06-18-2009 |
| 20090176344 | MOS Devices with Corner Spacers - A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third dielectric layer on the second dielectric layer, and etching the first, the second and the third dielectric layers using the third dielectric layer as a mask. The remaining first and second dielectric layers have an L-shape. The method further includes implanting source/drain regions, removing remaining portions of the third dielectric layer, blanket forming a fourth dielectric layer, etching the fourth dielectric layer, siliciding exposed source/drain regions, and forming a contact etch stop layer. The remaining portion of the fourth dielectric layer forms corner spacers. | 07-09-2009 |
| 20090280613 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first semiconductor pattern which is covered with a first insulating film over a first active region, forming a second semiconductor pattern over a second active region, forming a second insulating film over the first insulating film and the first and second semiconductor patterns, forming an opening whose depth reaches the first semiconductor pattern by etching the second insulating film and the first insulating film, forming sidewalls on side surfaces of the second semiconductor pattern by patterning the second insulating film, forming a metal film over the first and second semiconductor patterns respectively, and forming silicide layers by reacting the first and second semiconductor patterns with the metal film. | 11-12-2009 |
| 20090286375 | METHOD OF FORMING SIDEWALL SPACERS TO REDUCE FORMATION OF RECESSES IN THE SUBSTRATE AND INCREASE DOPANT RETENTION IN A SEMICONDUCTOR DEVICE - A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer. | 11-19-2009 |
| 20090325356 | METHODS OF FORMING A LOW TEMPERATURE DEPOSITION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Provided are methods of forming a low temperature deposition layer and methods of manufacturing a semiconductor device using the same. The method of manufacturing a semiconductor device comprises forming a mask layer exposing a gate pattern on a substrate on which the gate pattern is formed, forming a sacrifice layer on the mask layer and on a substrate not covered by the mask layer using a plasma ion immersion implantation and deposition (PIIID), and doping a substrate adjacent to both sidewalls of the gate pattern with an impurity. | 12-31-2009 |
| 20090325357 | Semiconductor device and method of manufacturing the same - A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films. | 12-31-2009 |
| 20100047985 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED STRESSOR AND EXTENSION REGIONS - Methods are provided for fabricating a MOS transistor having self-aligned stressor and extension regions. A method comprises forming a gate stack overlying a layer of semiconductor material and forming a spacer about sidewalls of the gate stack. The method further comprises forming cavities in the layer of semiconductor material, wherein the cavities are substantially aligned with the spacer. The method further comprises forming a stress-inducing semiconductor material in the cavities, and implanting ions of a conductivity-determining impurity type into the stress-inducing semiconductor material using the gate stack and the spacer as an implantation mask. | 02-25-2010 |
| 20100055859 | Semiconductor device and method of manufacturing the same - Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm. | 03-04-2010 |
| 20100068861 | METHOD OF DEFINING GATE STRUCTURE HEIGHT FOR SEMICONDUCTOR DEVICES - Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure. | 03-18-2010 |
| 20100081246 | Method of manufacturing a semiconductor - A semiconductor device and a method of manufacturing a semiconductor device, the method including forming a gate insulation layer and a gate electrode on a substrate, forming a silicon nitride layer on the gate electrode and the gate insulation layer, partially implanting ions into the silicon nitride layer to convert an upper portion of the silicon nitride layer into a treated silicon layer including the ions, etching the treated silicon layer to form a spacer on a sidewall of the gate electrode, and forming an impurity region in the substrate adjacent to the gate electrode. | 04-01-2010 |
| 20100120216 | TRANSISTOR FABRICATION METHOD - A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed. | 05-13-2010 |
| 20100129974 | METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICECIRCUIT DEVICE - When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed. | 05-27-2010 |
| 20100136763 | METHODS OF FORMING SEMICONDUCTOR DEVICE - Provided are methods of forming a semiconductor device, the method including: forming an insulation region on a substrate region, and an active region on the insulation region; patterning the active region to form an active line pattern; forming a gate pattern to surround an upper portion and lateral portions of the active line pattern; separating the gate pattern into a plurality of sub-gate regions, and separating the active line pattern into a plurality of sub-active regions, in order to form a plurality of memory cells that are each formed of the sub-active region and the sub-gate region and that are separated from one another; and forming first and second impurity doping regions along both edges of the sub-active regions included in each of the plurality of the memory cells, wherein the forming of the first and second impurity doping regions comprises doping lateral portions of the sub-active regions via a space between the memory cells. | 06-03-2010 |
| 20100151649 | Method of forming a minute pattern and method of manufacturing a transistor using the same - A method of forming a minute pattern includes forming mold patterns spaced apart from each other on an underlying structure, forming polysilicon spacers on sidewalls of the mold patterns, oxidizing the polysilicon spacers to form oxide layer patterns, and forming the minute pattern in a gap between the oxide layer patterns. | 06-17-2010 |
| 20100184265 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES MINIMIZING UNDER-OXIDE REGROWTH - Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack. | 07-22-2010 |
| 20100184266 | METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films. | 07-22-2010 |
| 20100190309 | METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE - By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions. | 07-29-2010 |
| 20100197102 | FILM DEPOSITION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A film deposition method includes the steps of: coating a solution containing a polysilane compound on a substrate to form a coating film and then carrying out a first thermal treatment in an inert atmosphere, thereby forming the coating film into a silicon film; forming a coating film containing a polysilane compound on the silicon film and then carrying out a second thermal treatment in an inert atmosphere or a reducing atmosphere, thereby forming the coating film into a silicon oxide precursor film; and carrying out a third thermal treatment in an oxidizing atmosphere, thereby forming the silicon oxide precursor film into a silicon oxide film and simultaneously densifying the silicon film. | 08-05-2010 |
| 20100203697 | INTEGRATED SEMICONDUCTOR NONVOLATILE STORAGE DEVICE - An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. | 08-12-2010 |
| 20100216293 | Method for Fabricating Semiconductor Devices - A method for fabricating a semiconductor device includes providing a semiconductor substrate including a memory cell region and peripheral circuit regions. Gate electrodes including gate conductive patterns and capping patterns are formed on the memory cell region and the peripheral circuit regions. An interlayer dielectric covering the gate electrodes is formed. The interlayer dielectric is patterned to form first contact holes exposing the semiconductor substrate along side of the gate electrode in the memory cell region and second contact holes exposing a portion of the capping pattern in the peripheral circuit region such that a bottom surface of the second contact hole is spaced apart from a top surface of the gate conductive pattern. A first plug conductive layer is filled in the first contact holes and a second plug conductive layer is filled in the second contact holes. A planarizing process is performed to expose the capping patterns such that first contact plugs are formed in the memory cell region and second contact plugs are formed in the peripheral circuit region. | 08-26-2010 |
| 20100248440 | NITRIDE REMOVAL WHILE PROTECTING SEMICONDUCTOR SURFACES FOR FORMING SHALLOW JUNCTIONS - A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing. | 09-30-2010 |
| 20110039389 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device, the manufacturing method including forming a first thin film on a substrate; forming a second thin film, which is different from the first thin film, on the first thin film; forming a sacrificial film, which is a film different from the second thin film, on the second thin film; forming a sacrificial film pattern by processing the sacrificial film into a pattern having desired intervals through etching; coating a silicon oxide film on the sacrificial film pattern by intermittently supplying a silicon-containing precursor and an oxygen-containing gas onto the substrate; forming sidewall spacers on the sidewalls of the sacrificial film by etching the silicon oxide film; removing the sacrificial film; and processing the first film and the second film by using the sidewall spacers as a mask. | 02-17-2011 |
| 20110045649 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH Al2O3/NANO-CRYSTALLINE Si LAYER - A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region. The method forms a sidewall structure overlying a side region of the polysilicon gate structure. | 02-24-2011 |
| 20110124172 | METHOD OF FORMING INSULATING LAYER AND METHOD OF MANUFACTURING TRANSISTOR USING THE SAME - Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO | 05-26-2011 |
| 20110143511 | Method of fabricating n-channel metal-oxide semiconductor transistor - A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer. | 06-16-2011 |
| 20110151637 | Method for Improving the Thermal Stability of Silicide - An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer | 06-23-2011 |
| 20110159657 | ENHANCED INTEGRITY OF A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL SPACER FOR CAP REMOVAL - In a process strategy for forming sophisticated high-k metal gate electrode structures in an early manufacturing phase, the dielectric cap material may be removed on the basis of a protective spacer element, thereby ensuring integrity of a silicon nitride sidewall spacer structure, which may preserve integrity of sensitive gate materials and may also determine the lateral offset of a strain-inducing semiconductor material. | 06-30-2011 |
| 20110171805 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 07-14-2011 |
| 20110183487 | Strained Semiconductor Device and Method of Making Same - To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed. | 07-28-2011 |
| 20110201170 | METHOD OF FABRICATING MEMORY - A method of fabricating a memory is provided. A substrate comprising a memory region and a periphery region is provided. A plurality of gates is formed on the substrate and a first spacer is formed on a sidewall of each gate, where a plurality of openings is formed between the gates in the memory region. A first material layer formed on the substrate in the memory region covers the gates in the memory region and fills the openings. A process is performed to the periphery region. The first material layer is partially removed to form a first pattern in each opening respectively. A second material layer formed on the substrate covers the memory region and the periphery region to expose the first patterns. The first patterns are removed to form a plurality of contact openings in the second material layer. The contact plugs are formed in the contact openings. | 08-18-2011 |
| 20110212590 | HIGH TEMPERATURE IMPLANTATION METHOD FOR STRESSOR FORMATION - An integrated circuit device and method of fabricating the integrated circuit device is disclosed. According to one of the broader forms of the invention, a method involves providing a semiconductor substrate. A combination of a pre-amorphous implantation process, a high temperature carbon implantation process, and/or an annealing process are performed on the substrate to form a stressor region. | 09-01-2011 |
| 20110212591 | METHOD FOR FABRICATING TRANSISTOR OF SEMICONDUCTOR DEVICE - A method for fabricating a transistor of a semiconductor device includes: forming a gate pattern over a substrate; forming a junction region by performing an on implantation process onto the substrate at opposite sides of the gate pattern; performing a solid phase epitaxial (SPE) process on the junction region at a temperature approximately ranging from 770° C. to 850° C.; and performing a rapid thermal annealing (RTA) process on the junction region. | 09-01-2011 |
| 20110230030 | STRAIN-PRESERVING ION IMPLANTATION METHODS - An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized. | 09-22-2011 |
| 20110237040 | MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 09-29-2011 |
| 20120009754 | METHOD FOR MAIN SPACER TRIM-BACK - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 01-12-2012 |
| 20120015493 | INTEGRATED METHOD FOR FORMING METAL GATE FinFET DEVICES - Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiN | 01-19-2012 |
| 20120028431 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING A NITROGEN CONTAINING OXIDE LAYER - The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure ( | 02-02-2012 |
| 20120034749 | METHOD FOR MANUFACTURING A STRAINED SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed. | 02-09-2012 |
| 20120064687 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes: forming a gate electrode on a substrate via a gate dielectric film; forming a first insulating film on the gate electrode, the first insulating film having a first groove in a central region of the first insulating film; and forming a halo region in the substrate below a side surface of the gate electrode, by injecting an impurity into the substrate through the first insulating film. | 03-15-2012 |
| 20120070954 | METHODS OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions. | 03-22-2012 |
| 20120100686 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming ultra-shallow lightly doped source/drain (LDD) regions of a CMOS transistor in a surface of a substrate includes the steps of providing a semiconductor substrate, providing a gate stack on the semiconductor substrate, performing a low temperature pocket implantation process on the substrate, performing a low temperature co-implanted ion implantation process on the substrate, and/or performing a low temperature lightly doped source/drain implantation process on the substrate. | 04-26-2012 |
| 20120108027 | IMPROVED SILICIDE METHOD - A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide. | 05-03-2012 |
| 20120164809 | SEMICONDUCTOR DEVICES INCLUDING STRAINED SEMICONDUCTOR REGIONS, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE DEVICES - A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity. | 06-28-2012 |
| 20120171833 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance. | 07-05-2012 |
| 20120178232 | FIELD EFFECT DEVICE STRUCTURE INCLUDING SELF-ALIGNED SPACER SHAPED CONTACT - A semiconductor structure and a method for fabricating the semiconductor structure include or provide a field effect device that includes a spacer shaped contact via. The spacer shaped contact via comprises a spacer shaped annular contact via that is located surrounding and separated from an annular spacer shaped gate electrode at the center of which may be located a non-annular and non-spacer shaped second contact via. The annular gate electrode as well as the annular contact via and the non-annular contact via may be formed sequentially in a self-aligned fashion while using a single sacrificial mandrel layer. | 07-12-2012 |
| 20120196421 | STRESS ADJUSTING METHOD - An stress adjusting method includes the following steps. A substrate is provided. A first gate structure and a second gate structure adjacent to the first gate structure are formed on the substrate. Each of the first gate structure and the second gate structure includes a spacer. A source/drain implantation process is applied to the substrate by using the first gate structure with the spacer and the second gate structure with the spacer as a mask. After the source/drain implantation process, the spacers are thinned so as to increase a distance between the first gate structure and the second gate structure. A stress film is formed. A first annealing process is applied to the substrate having the stress film. | 08-02-2012 |
| 20120225529 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 09-06-2012 |
| 20120238068 | SEMICONDUCTOR DEVICE INCLUDING A STRESS FILM - A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased. | 09-20-2012 |
| 20120322218 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening. | 12-20-2012 |
| 20120329234 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A COBALT SILICIDE - A method includes forming a gate over a substrate having a semiconductor layer comprising silicon. The gate has a sidewall spacer on sides of the gate. The gate has a gate length less than or equal to 50 nanometers. The gate is formed of polysilicon. A cobalt layer is formed on a top of the gate and the sidewall spacer. A titanium nitride layer is formed on the cobalt layer. The titanium nitride layer has a thickness over the gate in a range of 10 to 14 nanometers. An anneal is performed to form a cobalt silicide layer on the top of the gate and leave cobalt on the sidewall spacer. An etchant is applied that etches cobalt and titanium nitride selective to cobalt silicide to the titanium nitride layer. The cobalt is on the sidewall spacer and the cobalt silicide layer. An anneal is performed to increase conductivity of the cobalt silicide layer. | 12-27-2012 |
| 20130017661 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICEAANM WEI; QINGSONGAACI BeijingAACO CNAAGP WEI; QINGSONG Beijing CNAANM He; YONGGENAACI BeijingAACO CNAAGP He; YONGGEN Beijing CNAANM Liu; HUANXINAACI BeijingAACO CNAAGP Liu; HUANXIN Beijing CNAANM Liu; JialeiAACI BeijingAACO CNAAGP Liu; Jialei Beijing CNAANM Li; ChaoweiAACI BeijingAACO CNAAGP Li; Chaowei Beijing CN - A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a Σ shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching. | 01-17-2013 |
| 20130023103 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY USING STRESS MEMORIZATION TECHNIQUE - A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed. | 01-24-2013 |
| 20130034944 | METHOD FOR MAKING A DISILICIDE - Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height. | 02-07-2013 |
| 20130052782 | Implantation of Hydrogen to Improve Gate Insulation Layer-Substrate Interface - Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e | 02-28-2013 |
| 20130052783 | Methods of Forming Stressed Silicon-Carbon Areas in an NMOS Transistor - Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate. | 02-28-2013 |
| 20130078780 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer. | 03-28-2013 |
| 20130078781 | SEMICONDUCTOR FABRICATION - Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics. | 03-28-2013 |
| 20130130461 | EPITAXIAL PROCESS FOR FORMING SEMICONDUCTOR DEVICES - A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate. | 05-23-2013 |
| 20130143377 | STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC - The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region. | 06-06-2013 |
| 20130149830 | METHODS OF FORMING FIELD EFFECT TRANSISTORS HAVING SILICON-GERMANIUM SOURCE/DRAIN REGIONS THEREIN - Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions. | 06-13-2013 |
| 20130171795 | TRENCH SILICIDE CONTACT WITH LOW INTERFACE RESISTANCE - An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. | 07-04-2013 |
| 20130189822 | METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS - Methods are provided for fabricating integrated circuits that include forming first and second spaced apart gate structures overlying a semiconductor substrate, and forming first and second spaced apart source/drain regions in the semiconductor substrate between the gate structures. A first layer of insulating material is deposited overlying the gate structures and the source/drain regions by a process of atomic layer deposition, and a second layer of insulating material is deposited overlying the first layer by a process of chemical vapor deposition. First and second openings are etched through the second layer and the first layer to expose portions of the source/drain regions. The first and second openings are filled with conductive material to form first and second spaced apart contacts, electrically isolated from each other, in electrical contact with the first and second source/drain regions. | 07-25-2013 |
| 20130252393 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure. | 09-26-2013 |
| 20130273706 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer. | 10-17-2013 |
| 20130288446 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 10-31-2013 |
| 20130316511 | SUPERIOR STABILITY OF CHARACTERISTICS OF TRANSISTORS HAVING AN EARLY FORMED HIGH-K METAL GATE - When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies. | 11-28-2013 |
| 20130323898 | METHOD OF LITHOGRAPHY PROCESS WITH AN UNDER ISOLATION MATERIAL LAYER - A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process. | 12-05-2013 |
| 20130323899 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 12-05-2013 |
| 20130344673 | SEMICONDUCTOR DEVICE FABRICATION METHODS - A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure. | 12-26-2013 |
| 20140024194 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced. | 01-23-2014 |
| 20140065783 | OXYGEN SCAVENGING SPACER FOR A GATE ELECTRODE - At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer. | 03-06-2014 |
| 20140141588 | STRAINED TRANSISTOR STRUCTURE - A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor. | 05-22-2014 |
| 20140147982 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a semiconductor device with improved performance and production yield. Insulating films IL | 05-29-2014 |
| 20140162425 | METHOD OF FORMING DIELECTRIC FILMS USING A PLURALITY OF OXIDATION GASES - A method for forming a dielectric film is disclosed. The method includes (a) exposing a substrate to a first gas pulse having a first oxygen-containing gas in a chamber; (b) exposing the substrate to multiple consecutive second gas pulses having a second oxygen-containing gas in the chamber, wherein the first oxygen-containing gas is different from the second oxygen-containing gas; and (c) sequentially after (a) and (b), exposing the substrate to a third gas pulse having a metal-containing gas in the chamber. Steps (a), (b), and (c) may be repeated any number of times to form the dielectric film with a predetermined thickness. | 06-12-2014 |
| 20140242770 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed. | 08-28-2014 |
| 20140273389 | SEMICONDUCTOR DEVICE HAVING CONTROLLED FINAL METAL CRITICAL DIMENSION - An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around). | 09-18-2014 |
| 20140349460 | Method for producing a silicon-germanium film with variable germanium content - The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas. | 11-27-2014 |
| 20140370681 | FIELD-EFFECT TRANSISTOR (FET) WITH SOURCE-DRAIN CONTACT OVER GATE SPACER - A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate. | 12-18-2014 |
| 20150024569 | INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate electrode, forming a diffusion barrier structure in the recess, forming an N-type doped silicon-containing structure over the diffusion barrier structure and thermally annealing the N-type doped silicon-containing structure. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode and the second portion is distant from the gate electrode. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. | 01-22-2015 |
| 20150087128 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE THAT INCLUDES A MISFET - An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes. | 03-26-2015 |
