| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438262000 | Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.) | 7 |
| 20080242025 | 3-DIMENSIONAL FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate. | 10-02-2008 |
| 20080286926 | BIT LINE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same. | 11-20-2008 |
| 20110086482 | APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE CELL WITH INCREASED OVERLAY BETWEEN THE CONTROL GATE AND FLOATING GATE - A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design. | 04-14-2011 |
| 20160172505 | Zero Cost NVM Cell Using High Voltage Devices in Analog Process | 06-16-2016 |
| 438263000 | Tunneling insulator | 3 |
| 20080220577 | SCALABLE HIGH DENSITY NON-VOLATILE MEMORY CELLS IN A CONTACTLESS MEMORY ARRAY - A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer. | 09-11-2008 |
| 20080286927 | NON-VOLATILE MEMORY DEVICE WITH BURIED CONTROL GATE AND METHOD OF FABRICATING THE SAME - In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation. | 11-20-2008 |
| 20120164804 | METHODS OF FORMING REVERSE MODE NON-VOLATILE MEMORY CELL STRUCTURES - Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system. | 06-28-2012 |
