Class / Patent application number | Description | Number of patent applications / Date published |
438258000 | Including additional field effect transistor (e.g., sense or access transistor, etc.) | 39 |
20080254584 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method for manufacturing a flash memory device including providing a semiconductor substrate having a cell region and a periphery region; and then adjusting a threshold voltage of the cell region; and then forming a memory device on the cell region and forming a transistor on the periphery region; and then forming an interlayer dielectric layer on the memory device and the transistor, wherein the height of a first portion of the interlayer dielectric layer at the cell region is greater the height of a second portion of the interlayer dielectric layer at the periphery region; and then removing the height difference between the first portion of the interlayer dielectric layer and the second portion of the interlayer dielectric layer. | 10-16-2008 |
20080268594 | METHOD OF FABRICATING A FLASH MEMORY DEVICE - In a method of fabricating a flash memory device, a lower capping conductive layer of a peri region is patterned. A step formed between a cell gate and a gate for a peri region transistor is decreased by controlling a target etch thickness of a hard mask. Thus, an impurity does not infiltrate into the bottom of the gate for the peri region transistor through a lost portion of a SAC nitride layer. Accordingly, a hump phenomenon of the transistor formed in the peri region can be improved. Furthermore, a leakage current characteristic of the transistor formed in the peri region can be improved. | 10-30-2008 |
20080268595 | NAND flash memory devices and methods of fabricating the same - A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors. | 10-30-2008 |
20090111226 | METHOD FOR INTEGRATING NVM CIRCUITRY WITH LOGIC CIRCUITRY - A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area. | 04-30-2009 |
20100047981 | Method of fabricating EEPROM - There is provided a method of fabricating an EEPROM for forming a memory cell transistor and a selection transistor, the method includes: forming a first source region and a first drain region of the memory cell transistor; forming a first gate oxide film; forming a resist having at least one through hole on the first gate oxide film; adding conductivity type impurities through the through hole; partially removing the first gate oxide film and forming a tunnel oxide film in a region corresponding to the through hole; forming a floating gate electrode and a second gate oxide film formed on the floating gate electrode; forming a control gate electrode and a selection transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and forming a second source region and a second drain region of the selection cell transistor. | 02-25-2010 |
20100068857 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A semiconductor device in which a channel region of MOS transistor is provided not to include a non-flat active region end portion and a manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor device comprising a semiconductor substrate, a device isolation separating active region, wherein at least a portion of the device isolation is provided in the semiconductor substrate, and a memory cell including a memory cell transistor that comprises a channel region separated by a slit and constituted of a flat active region alone, a charge storage layer provided on a gate dielectric on the channel region, and a first gate electrode provided on an inter-electrode dielectric so as to cover the charge storage layer, and a select transistor that comprises a second gate electrode provided on the gate dielectric on the active region and electrically connected to a wiring. | 03-18-2010 |
20100144108 | METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film. | 06-10-2010 |
20100151641 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion, a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion, and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion. | 06-17-2010 |
20100221880 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor. | 09-02-2010 |
20110070706 | Method for forming NAND typed memory device - A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors. | 03-24-2011 |
20110081755 | Methods Of Fabricating An Access Transistor Having A Polysilicon-Comprising Plug On Individual Of Opposing Sides Of Gate Material - Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems including same are also disclosed. | 04-07-2011 |
20110086481 | METHODS OF FORMING NON-VOLATILE MEMORY STRUCTURE WITH CRESTED BARRIER TUNNEL LAYER - Embodiments of methods of forming non-volatile memory structures are provided. In one such embodiment, first and second source/drain regions are formed on a substrate so that the first and second source/drain regions define an intervening channel region. A charge blocking layer is formed over the channel region. A trapping layer is formed over the charge blocking layer. A tunnel layer of two or more sub-layers is formed over the trapping layer, where the two or more sub-layers form a crested barrier tunnel layer. A control gate is formed over the tunnel layer. | 04-14-2011 |
20110092037 | SEMICONDUCTOR DEVICE - In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film. | 04-21-2011 |
20110207274 | METHOD FOR FORMING A SPLIT-GATE MEMORY CELL - A method for forming a semiconductor device includes forming a first semiconductor layer over a substrate, forming a first photoresist layer over the first semiconductor layer, and using only a first single mask patterning the first photoresist layer to form a first patterned photoresist layer. The method further includes using the first patterned photoresist layer etching the first semiconductor layer to form a select gate and forming a charge storage layer over the select gate and a portion of the substrate. The method further includes forming a second semiconductor layer over the charge storage layer, forming a second photoresist layer over the second semiconductor layer, and using only a second single mask patterning the second photoresist layer to form a second patterned photoresist layer. The method further includes forming a control gate by anisotropically etching the second semiconductor layer and then subsequently isotropically etching the second semiconductor layer. | 08-25-2011 |
20110256679 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 10-20-2011 |
20120094451 | Method for Fabricating a Non-volatile Memory Device - A method for fabricating a non-volatile memory device with asymmetric source/drain junctions, wherein a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks. | 04-19-2012 |
20120108022 | SEMICONDUCTOR DEVICE INCLUDING A P-CHANNEL TYPE MOS TRANSMITTER - A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region. | 05-03-2012 |
20120156842 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first conductive type well and a second conductive type well disposed on and/or over a semiconductor substrate; a first gate and a second gate disposed on and/or over the first conductive type well and the second conductive type well, respectively; a second conductive type first ion implantation region disposed in the first conductive type well at one side of the first gate and a second conductive type second ion implantation region disposed in the first conductive type well at the other side of the first gate; a first conductive type first ion implantation region disposed in the second conductive type well at one side of the second gate and a first conductive type second ion implantation region disposed in the second conductive type well at the other side of the second gate; and a line electrically connecting the second conductive type second ion implantation region with the first conductive type first ion implantation region. | 06-21-2012 |
20120178229 | SEMICONDUCTOR MEMORY DEVICE WITH STACKED GATE INCLUDING CHARGE STORAGE LAYER AND CONTROL GATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region. | 07-12-2012 |
20130017655 | DEVICES WITH NANOCRYSTALS AND METHODS OF FORMATION - Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein. | 01-17-2013 |
20130130452 | MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS - Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described. | 05-23-2013 |
20130171785 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate. | 07-04-2013 |
20130178026 | METHOD FOR FABRICATING A FIELD SIDE SUB-BITLINE NOR FLASH ARRAY - Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density. | 07-11-2013 |
20130178027 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer. | 07-11-2013 |
20130267072 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region. | 10-10-2013 |
20140377921 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer above the first region is patterned to form a gate electrode of an MIS-type transistor. | 12-25-2014 |
20150037950 | COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF - A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. | 02-05-2015 |
20150104915 | MEMORY CELL WITH DECOUPLED CHANNELS - A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel. | 04-16-2015 |
20150295056 | METHOD OF MANUFACTURING AN EMBEDDED SPLIT-GATE FLASH MEMORY DEVICE - A method of manufacturing an embedded split-gate flash memory device is provided. The method includes: performing shallow trench isolation and chemical mechanical planarization on a semiconductor substrate comprising a flash memory region and a logic region, wherein a first oxide is formed on the semiconductor substrate and a first nitride is formed on the first oxide; forming a first photoresist over the logic region, and removing the first nitride disposed in the flash memory region; removing the first photoresist, and depositing a floating gate polysilicon material over the semiconductor substrate; performing chemical mechanical planarization on the floating gate polysilicon material; forming a control gate in the flash memory region; etching the floating gate polysilicon material to form a floating gate; forming a second photoresist over the flash memory region, and removing the first oxide and the first nitride disposed in the logic region; and removing the second photoresist. | 10-15-2015 |
20150318300 | METHOD OF MAKING DAMASCENE SELECT GATE IN MEMORY DEVICE - A method of fabricating a memory device includes forming a mask over a top surface of a stack of alternating insulating material layers and control gate electrodes located over a substrate, wherein the stack has a memory opening extending vertically through the stack, a semiconductor channel extends vertically in the memory opening, and a memory film is located in the memory opening between the semiconductor channel and the plurality of control gate electrodes, and the mask covers a first portion of an upper insulating layer of the stack and exposes a second portion of the upper insulating layer adjacent to the memory opening, etching the upper insulating layer through the mask to provide a recess in the second portion of the upper insulating layer, and forming a conductive material within the recess to provide a select gate electrode adjacent to the semiconductor channel in the memory opening. | 11-05-2015 |
20150340374 | MEMORY DEVICE - A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer. | 11-26-2015 |
20160027794 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode. | 01-28-2016 |
20160035734 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed. | 02-04-2016 |
20160086961 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film. | 03-24-2016 |
20160093632 | HIGH VOLTAGE DOUBLE-DIFFUSED MOS (DMOS) DEVICE AND METHOD OF MANUFACTURE - A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell. | 03-31-2016 |
20160133511 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer. | 05-12-2016 |
20160133636 | Embedded Flash Memory Device with Floating Gate Embedded in a Substrate - An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack. | 05-12-2016 |
20160148944 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region. | 05-26-2016 |
20190148391 | Embedded Flash Memory Device with Floating Gate Embedded in a Substrate | 05-16-2019 |