| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438253000 | Stacked capacitor | 28 |
| 20080199994 | Method of Producing Semiconductor Device and Semiconductor Device - A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films is kept thin. | 08-21-2008 |
| 20080213958 | Capacitor structure and fabricating method thereof - Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts. | 09-04-2008 |
| 20080227253 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which includes a first gate wiring layer and a second gate wiring layer adjacent to each other; a first diffused layer provided on a side between the wiring layers; a second diffused layer provided on one side external to the side between the wiring layers; and a third diffused layer provided on the other side external to the side between the wiring layers, the method including: forming a first mask including an opening; implanting a channel impurity for threshold voltage control using the first mask; forming a first diffused layer using the first mask by implanting a first impurity; forming a first gate wiring layer and a second gate wiring layer after removing the first mask; and forming a second diffused layer and a third diffused layer using the first gate wiring layer and the second gate wiring layer as a second mask by implanting a second impurity. | 09-18-2008 |
| 20080261364 | METHOD FOR FORMING STACK CAPACITOR - A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to form a tapered trench in the bottom layer, the BPSG layer and the USG layer; removing the top layer to perform a selective wet etching process to partially remove the BPSG layer; depositing conformally a poly-Si layer and filling the trench with a sacrificial layer; removing the poly-Si layer unmasked by the sacrificial layer; using the bottom layer as a second etching stop layer to perform a wet etching process to remove the USG layer and BPSG layer; performing a static drying process; and depositing a dielectric layer and a conductive material to form the stack capacitor. | 10-23-2008 |
| 20080268592 | Flash memory device and method of fabricating the same - Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer. | 10-30-2008 |
| 20080280408 | SEMICONDUCTOR DEVICE WITH IMPROVED OVERLAY MARGIN AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed. | 11-13-2008 |
| 20080318378 | MIM Capacitors with Improved Reliability - A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. | 12-25-2008 |
| 20090155966 | DRAM WITH NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein. | 06-18-2009 |
| 20090197379 | SELECTIVE EPITAXY VERTICAL INTEGRATED CIRCUIT COMPONENTS AND METHODS - Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. | 08-06-2009 |
| 20090209072 | Methods Of Forming Transistor Gates, Methods Of Forming Memory Cells, And Methods Of Forming DRAM Arrays - Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized. | 08-20-2009 |
| 20100003794 | METHOD FOR DEFECT REDUCTION FOR MEMORY CELL CAPACITORS - A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching process expose the storage nodes. A polysilicon layer and a rugged polysilicon layer are formed overlying the exposed storage nodes. The memory cell region is masked, exposing a peripheral region. A chemical dry etch process removes the rugged polysilicon and the polysilicon layers in the peripheral region. The rugged polysilicon and the polysilicon layers are planarized followed by a dielectric recess. The resulting cylindrical stack capacitor structures are substantially free of defects from rugged polysilicon remaining in the peripheral region thereby improving device yield and process window. | 01-07-2010 |
| 20100144107 | Semiconductor Memory Device - A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced. | 06-10-2010 |
| 20100210082 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises forming a dielectric film, and oxidizing the dielectric film. In oxidizing the dielectric film, an oxidized gas is supplied to the dielectric film at a heat treatment. Supplying the oxidized gas is performed intermittently a plurality of times while the dielectric film is subjected to heat treatment. | 08-19-2010 |
| 20100273303 | Memory Arrays and Methods of Fabricating Memory Arrays - A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays. | 10-28-2010 |
| 20100297820 | Embedded Semiconductor Device Including Planarization Resistance Patterns and Method of Manufacturing the Same - An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the substrate, a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions, first via plugs which vertically penetrate the first ILD layer and are selectively connected to the source/drain regions, capacitors and second via plugs selectively connected to the first via plugs, a second ILD layer that fills the space between the capacitors and the second via plugs, planarization resistance patterns formed on the second ILD layer, a third ILD layer formed on the second ILD layer and the planarization resistant patterns, and third via plugs which vertically penetrate the third ILD layer, and are selectively connected to a top electrode of the capacitors and the second via plugs. | 11-25-2010 |
| 20110092036 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - After forming a first capacitor hole, first mask material is filled in an upper portion of the first capacitor hole. A second capacitor hole is formed so that it is aligned with the first capacitor hole. After removing the first mask material, a lower electrode is formed in the first and second capacitor holes by one film formation step. After that, a capacitor dielectric film and an upper electrode are sequentially formed on the lower electrode. | 04-21-2011 |
| 20110171796 | VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY - A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning. | 07-14-2011 |
| 20120231592 | Methods Of Fabricating A Memory Device - A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced. | 09-13-2012 |
| 20120252178 | PATTERNING A GATE STACK OF A NON-VOLATILE MEMORY (NVM) WITH FORMATION OF A CAPACITOR - A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region. | 10-04-2012 |
| 20130178025 | Methods Of Fabricating A Memory Device - A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced. | 07-11-2013 |
| 20140087533 | METHODS OF FORMING TRANSISTORS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING THE TRANSISTORS - A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess. | 03-27-2014 |
| 20150325579 | DRAM WITH NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein. | 11-12-2015 |
| 20150357377 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING RESERVOIR CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. A first conductive layer is formed on the first insulating layer, and a second insulating layer is formed on the first conductive layer. The second insulating layer is patterned to be left in a portion of the first region. A second conductive layer is formed on the second insulating layer and the first conductive layer. The second conductive layer is etched to expose a partial surface of the first conductive layer in the first region. The second conductive layer and the first conductive layer are etched to form a reservoir capacitor in the first region and form a gate in the second region. | 12-10-2015 |
| 20160086957 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines. | 03-24-2016 |
| 20160087072 | DUMMY BIT LINE MOS CAPACITOR AND DEVICE USING THE SAME - A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line. | 03-24-2016 |
| 20160118388 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first space partitioned by first and second line patters ( | 04-28-2016 |
| 438255000 | Including texturizing storage node layer | 1 |
| 20080268593 | METHODS FOR FABRICATING A CAPACITOR - A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor. | 10-30-2008 |
| 438256000 | Contacts formed by selective growth or deposition | 1 |
| 20100190306 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM - A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan | 07-29-2010 |
