| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438250000 | Planar capacitor | 6 |
| 20080227252 | FABRICATION METHODS OF THIN FILM TRANSISTOR SUBSTRATES - Methods for manufacturing thin film transistor arrays utilizing three steps of lithography and one step of laser ablation while the lithography procedure is used four to five times in conventional processes are disclosed. The use of the disclosed methods assists in improving throughput and saving of manufacturing cost. | 09-18-2008 |
| 20110070704 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is disclosed a semiconductor device including a silicon substrate, provided with a plurality of cell active regions in a call region, an element isolation groove, formed in a portion, between any two of the plurality of cell active region, of the silicon substrate, a capacitor dielectric film, formed in the element isolation groove, a capacitor upper electrode, formed on the capacitor dielectric film, and configuring a capacitor together with the silicon substrate and the capacitor dielectric film. The semiconductor device is characterized in that a dummy active region is provided next to the cell region in the silicon substrate. | 03-24-2011 |
| 20110092035 | Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process - A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer. | 04-21-2011 |
| 20130130451 | Semiconductor Device with Reliable High-Voltage Gate Oxide and Method of Manufacture Thereof - A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material. | 05-23-2013 |
| 438251000 | Including doping of semiconductive region | 2 |
| 20080268591 | Methods of Forming Capacitors - A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated. | 10-30-2008 |
| 20080299723 | METHODS FOR FORMING CAPACITOR STRUCTURES - A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor. | 12-04-2008 |
