| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438234000 | Including bipolar transistor (i.e., BiMOS) | 15 |
| 20080254583 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device includes steps of forming a gate electrode on the surface of a region of a semiconductor substrate provided with a first element, forming an insulating film to cover the surface of the gate electrode and another region of the semiconductor substrate provided with a second element and forming a sidewall insulating film covering the side surface of the gate electrode while leaving the insulating film on the region of the semiconductor substrate provided with the second element by a prescribed thickness by etching the insulating film up to an intermediate portion from the surface thereof. | 10-16-2008 |
| 20090029510 | MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING - A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed. | 01-29-2009 |
| 20090197378 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region. | 08-06-2009 |
| 20090286368 | PROCESS FOR PCM INTEGRATION WITH POLY-EMITTER BJT AS ACCESS DEVICE - Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed. | 11-19-2009 |
| 20110065246 | EMBEDDED PHASE-CHANGE MEMORY AND METHOD OF FABRICATING THE SAME - An embedded memory required for a high performance, multifunction SOC, and a method of fabricating the same are provided. The memory includes a bipolar transistor, a phase-change memory device and a MOS transistor, adjacent and electrically connected, on a substrate. The bipolar transistor includes a base composed of SiGe disposed on a collector. The phase-change memory device has a phase-change material layer which is changed from an amorphous state to a crystalline state by a current, and a heating layer composed of SiGe that contacts the lower surface of the phase-change material layer. | 03-17-2011 |
| 20110097860 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention provides a method of manufacturing a semiconductor device having a MOS transistor, a resistor element, etc on one semiconductor substrate, in which the number of masks and the number of manufacturing steps are decreased. In an NMOS formation region, a channel stopper layer is formed in a P type well by a first ion implantation process. Then a punch-through prevention layer is formed in the P type well by a second ion implantation process. On the other hand, in a first high resistor element formation region and a second high resistor element formation region, utilizing the first and second ion implantation processes, a resistor layer is formed in an N type well. | 04-28-2011 |
| 20120100680 | Low Temperature Implant Scheme to Improve BJT Current Gain - A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region. | 04-26-2012 |
| 20140213024 | PRODUCTION OF MULTIPLE SEMICONDUCTOR DEVICES USING A SEMICONDUCTOR PROCESS - In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device. | 07-31-2014 |
| 20160172245 | Method of forming a Gate Shield in an ED-CMOS Transistor and a base of a bipolar transistor using BICMOS Technologies | 06-16-2016 |
| 438235000 | Heterojunction bipolar transistor | 2 |
| 20110250726 | SEMICONDUCTOR DEVICE HAVING A HETERO-JUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - Method for manufacturing a semiconductor device. A channel layer is formed by epitaxially growing a semiconductor layer, in which an ion species of a first conductivity is implanted on a semiconductor substrate. A source region, a drain region, and an emitter region which are of the first conductivity, are formed by activating, using annealing, a portion of the semiconductor substrate in which the ion species has been implanted. An emitter layer of the first conductivity, a base layer of a second conductivity having a band gap smaller than a band gap of the emitter layer, and a collector layer of the first conductivity or a non-doped collector layer are sequentially and epitaxially grown on the channel layer. | 10-13-2011 |
| 20150056767 | METHODS FOR FORMING TRANSISTORS - A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor. | 02-26-2015 |
| 438236000 | Lateral bipolar transistor | 4 |
| 20100178740 | BIPOLAR TRANSISTORS WITH RESISTORS - Complementary MOS (CMOS) integrated circuits include MOS transistors, resistors and bipolar transistors formed on a common substrate. An emitter region of a bipolar transistor is implanted with a first dopant in an implantation process that implants source/drain regions of an MOS transistor, and is also implanted with a second dopant of same conductivity type in another implantation process that implants a body region of a resistor. The first and second dopants may optionally be the same dopant. The source/drain regions are implanted with the resistor body region covered by a first patterned mask; and the resistor body region is implanted with the MOS transistor source/drain regions covered by a second patterned mask. The implantations of the MOS transistor source/drain regions and of the resistor body region the source/drain regions can occur in any order, with the emitter region implanted during both implantations. | 07-15-2010 |
| 20140127869 | LATERAL BIPOLAR JUNCTION TRANSISTOR - A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process. | 05-08-2014 |
| 20160099240 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) CLAMPING - A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region. | 04-07-2016 |
| 20160111519 | INSULATED GATE BIPOLAR TRANSISTOR WITH A LATERAL GATE STRUCTURE AND GALLIUM NITRIDE SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel. | 04-21-2016 |
