| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438233000 | And contact formation | 14 |
| 20080242020 | METHOD OF MANUFACTURING A MOS TRANSISTOR DEVICE - A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Next, an inert gas treatment is performed to change a stress value of the stressed cap layer. Because the stress value of the stressed cap layer can be adjusted easily by means of the present invention, one stressed cap layer can be applied to both the N-type MOS transistor and the P-type MOS transistor. | 10-02-2008 |
| 20080318376 | Semiconductor Device Manufactured Using a Method to Improve Gate Doping While Maintaining Good Gate Profile - In one aspect, there is provided a method of manufacturing a semiconductor device. This method includes forming gate structures over a substrate, wherein the gate structures include gate electrodes located adjacent source/drain regions. A protective layer is formed over the gate structures and a CMP layer is formed over the protective layer. A portion of the CMP layer and the protective layer is removed to expose a portion of the gate electrodes with remaining portions of the CMP layer and the protective layer remaining over the source/drain regions. The exposed portion of the gate electrodes are doped with an n-type dopant or a p-type dopant, and the remaining portions of the CMP layer and the protective layer located over the source/drain regions are removed subsequent to the doping. | 12-25-2008 |
| 20090087956 | Dummy Contact Fill to Improve Post Contact Chemical Mechanical Polish Topography - State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs. | 04-02-2009 |
| 20090186458 | METHOD FOR MANUFACTURING A CMOS DEVICE HAVING DUAL METAL GATE - A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate. | 07-23-2009 |
| 20090317951 | SEMICONDUCTOR DEVICE - A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode. | 12-24-2009 |
| 20110027953 | Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement - Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed. | 02-03-2011 |
| 20120003799 | Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers - Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film. | 01-05-2012 |
| 20120149159 | STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE - While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices. | 06-14-2012 |
| 20130084683 | LIQUID CRYSTAL DISPLAY DEVICE WITH SHIELD LINES ON DATA LINES AND THIN FILM TRANSISTOR COMPONENTS - A liquid crystal display device includes a p-type driving thin film transistor and an n-type driving thin film transistor in a non-display region, and a pixel thin film transistor connected to a gate line and a data line in a display region. The liquid crystal display device further includes a pixel electrode that covers and directly contacts a third drain electrode of the pixel thin film transistor, a shield pattern that covers and directly contacts each of the first source electrode and the first drain electrode of the p-type driving thin film transistor and the second source electrode and the second drain electrode of the n-type driving thin film transistor, and a shield line that covers and directly contacts the data line and a third source electrode of the pixel thin film transistor. | 04-04-2013 |
| 20130280872 | SEMICONDUCTOR DEVICE INCLUDING WORK FUNCTION ADJUSTING ELEMENT, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode. | 10-24-2013 |
| 20140315363 | 6T SRAM Architecture For Gate-All-Around Nanowire Devices - A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around, (GAA) semiconductor nanowires. First, second, and third field effect transistors (FETs) are formed by the first plurality of semiconductor nanowires. The memory device also includes a second plurality of semiconductor nanowires tethered between landing pads and suspended over the substrate. A second gate electrode surrounds each of the second plurality of semiconductor nanowires, making them GAA semiconductor nanowires. Fourth, fifth, and sixth FETs are formed by the second plurality of semiconductor nanowires. The first gate electrode is aligned with and cross-coupled to a landing pad of the second plurality of semiconductor nanowires, and the second gate electrode is aligned with and cross-coupled to a landing pad of the first plurality of semiconductor nanowires. | 10-23-2014 |
| 20150303114 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE, OPTICAL APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A complementary metal oxide semiconductor (CMOS) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a Group III-V compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate. | 10-22-2015 |
| 20160035629 | METHODS OF FORMING LOW RESISTANCE CONTACTS - Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings. | 02-04-2016 |
| 20160049410 | SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY - An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps. | 02-18-2016 |
