| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438218000 | Including isolation structure | 86 |
| 20080206942 | METHOD FOR FABRICATING STRAINED-SILICON METAL-OXIDE SEMICONDUCTOR TRANSISTORS - A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants. | 08-28-2008 |
| 20080261361 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner - A method for making a semiconductor device is provided which comprises (a) providing a layer stack comprising a semiconductor layer ( | 10-23-2008 |
| 20080268588 | RECESSED GATE CHANNEL WITH LOW Vt CORNER - A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region. The recessed gate FET device suppresses short channel effects and exhibits improved threshold voltage (Vt) characteristics at corners of the trench bottom. | 10-30-2008 |
| 20080268589 | SHALLOW TRENCH DIVOT CONTROL POST - The disclosure provides a method of manufacturing a semiconductor device. The method comprises forming a shallow trench isolation structure, including performing a wet etch process to remove a patterned pad oxide layer located on a semiconductor substrate. The wet etch thereby produces a divot on upper lateral edges of a insulator-filled trench in the semiconductor substrate. Forming the shallow trench isolation structure also includes forming a nitride post on a vertical wall of the divot. Forming the nitride post includes depositing a nitride layer on the insulator, and dry etching the nitride layer. The dry etch is selective towards the nitride located adjacent the vertical wall such that a portion of the nitride layer remains on the vertical wall subsequent to the dry etching. | 10-30-2008 |
| 20080286920 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method includes forming a negative photoresist layer on a semiconductor substrate, forming a photoresist pattern on the negative photoresist layer, forming a well region in the semiconductor substrate, implanting ions into the semiconductor substrate, using the photoresist pattern as a mask, such that the ions are implanted into the well region, removing the photoresist pattern, and forming a gate region and a source/drain region on the semiconductor substrate. | 11-20-2008 |
| 20090011554 | Component With Sensitive Component Structures and Method for the Production Thereof - An electrical component has electrically conducting structures placed on an electrically isolating or semiconductive substrate and component structures sensitive to a voltage or an electrical arcing and galvanically separated from one another. To prevent an arcing between the galvanically separated component structures, the component structures are short-circuited with a shunt line having a smaller cross-section than the remaining electrical conductor tracks. The shunt lines can be burnt through by application of an electrical current at any given time, whereby a galvanic separation of the component structures is effected, if necessary, for the function of the component. | 01-08-2009 |
| 20090011555 | Method of manufacturing CMOS integrated circuit - In a method of manufacturing a CMOS integrated circuit according to the present invention, a PSD step (step of forming P-type source/drain regions) is first carried out, and an NSD step (step of forming N-type source/drain regions) is thereafter carried out, in order to create a mixed structure of a silicide transistor and a non-silicide transistor. Thus, a step of depositing an oxide film on a substrate surface may be carried out only once, the oxide film can be removed by a single step of etching with hydrofluoric acid, and the operating characteristics of formed devices can be excellently maintained. | 01-08-2009 |
| 20090137089 | SEMICONDUCTOR MOS TRANSISTOR DEVICE AND METHOD FOR MAKING THE SAME - A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status. | 05-28-2009 |
| 20090142892 | Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device - A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain. | 06-04-2009 |
| 20090191675 | Method for Forming CMOS Transistors Having FUSI Gate Electrodes and Targeted Work Functions - A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask. The method also includes forming a layer of insulating material and then removing the hardmasks and a portion of the layer of insulating material. A layer of silicidation metal is formed and a first silicide anneal changes the undoped polysilicon gate electrodes into partially silicided gate electrodes. Dopants of a first type and a second type are implanted into the partially silicided gate electrode of the PMOS and NMOS transistors and a second silicide anneal is performed to change the doped partially silicided gate electrodes into fully silicided gate electrodes. | 07-30-2009 |
| 20090221116 | Method for Manufacturing Semiconductor Device - Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is formed by sintering a metal/poly-Si structure. The element characteristics also fluctuate due to element-to-element non-uniformity of the resultant silicide composition. By first forming full silicide having a metal-rich composition, depositing a Si layer thereon, and sintering the combined structure, the metal in the metal-rich silicide diffuses into the Si layer, so that the Si layer is converted into silicide. The entire structure thus is converted into full silicide having a smaller metal composition ratio. | 09-03-2009 |
| 20100035393 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING RADIATION HARDENED INSULATORS - A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate from an SOI wafer and selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device. The method further comprises selectively removing isolation oxide formed between the active regions, and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators. | 02-11-2010 |
| 20100047977 | STRAINED SILICON WITH ELASTIC EDGE RELAXATION - A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations. | 02-25-2010 |
| 20100099228 | METHOD FOR REDUCING POLY-DEPLETION IN DUAL GATE CMOS FABRICATION PROCESS - Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps. | 04-22-2010 |
| 20100197090 | Method of fabricating semiconductor device having transistor - Provided is a method of fabricating a semiconductor device having a transistor. The method includes forming a first gate trench in a first active region of a semiconductor substrate. A first gate layer partially filling the first gate trench is formed. Ions may be implanted in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode. | 08-05-2010 |
| 20100197091 | GATE DIELECTRIC/ISOLATION STRUCTURE FORMATION IN HIGH/LOW VOLTAGE REGIONS OF SEMICONDUCTOR DEVICE - A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr | 08-05-2010 |
| 20100330755 | Semiconductor Device With Localized Stressor - A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors. | 12-30-2010 |
| 20110008938 | THIN FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE THIN FILM - Disclosed is a thin film which is used in the production process of a semiconductor device. The thin film contains germanium, silicon, nitrogen and hydrogen. | 01-13-2011 |
| 20110033993 | METHOD OF FABRICATING CMOS TRANSISTOR - The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required. | 02-10-2011 |
| 20110076814 | METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR - First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region. | 03-31-2011 |
| 20110207272 | Semiconductor device and manufacturing process therefor - A process for manufacturing a semiconductor device includes preparing a semiconductor substrate including an N-type region and a P-type region isolated by an isolation region, forming a gate insulating film including an Hf-containing high-dielectric insulating film at least in an uppermost surface over the semiconductor substrate, forming a silicon layer over the gate insulating film, implanting a dopant into only any one of silicon layers over the P-type region and the N-type region, processing the silicon layers to form a gate pattern including a silicon region extending from a region over the N-type region through a region over the isolation region to a region over the P-type region, forming a gate sidewall on a sidewall of the gate pattern, implanting a dopant into the semiconductor substrate using the gate pattern and the gate sidewall as a mask, activating the dopant in the silicon region and the semiconductor substrate by heating, forming an interlayer insulating film over the gate pattern, removing the interlayer insulating film to expose the gate pattern, and depositing a silicide-formable metal M layer over the exposed gate pattern. | 08-25-2011 |
| 20110269277 | Reduced STI Topography in High-K Metal Gate Transistors by Using a Mask After Channel Semiconductor Alloy Deposition - In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors. | 11-03-2011 |
| 20110294271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof. | 12-01-2011 |
| 20120178227 | REPLACEMENT GATE CMOS - A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method. | 07-12-2012 |
| 20130023094 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid. | 01-24-2013 |
| 20130102117 | Manufacturing Processes for Field Effect Transistors Having Strain-Induced Chanels - One embodiment relates to a method of semiconductor manufacture. In this method, a strain inducing layer is formed over a p-type field effect transistor structure and an n-type field effect transistor structure. The strain inducing layer is removed from over the p-type field effect transistor while the strain inducing layer over the n-type field effect transistor is left in place. A treatment of the strain inducing layer over the n-type field effect transistor is performed after the strain-inducing layer has been removed from over the p-type field effect transistor. | 04-25-2013 |
| 20130157425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a cooling function component including an active region made of an impurity region and formed on a surface of a semiconductor layer, an N-type gate made of a semiconductor including an N-type impurity, a P-type gate made of a semiconductor including a P-type impurity, a first metal wiring connected to the N-type gate, the P-type gate and the active region, a second metal wiring connected to the P-type gate and the N-type gate, and a heat releasing portion connected to the second metal wiring for releasing heat to the outside. | 06-20-2013 |
| 20130189818 | TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION - Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench. | 07-25-2013 |
| 20140113419 | METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL - In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process. | 04-24-2014 |
| 20140141582 | CMOS DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer. | 05-22-2014 |
| 20140315362 | CMOS Transistor With Dual High-k Gate Dielectric - A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V | 10-23-2014 |
| 20140349451 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE HAVING GATE STRUCTURES CONNECTED BY A METAL GATE CONDUCTOR - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 11-27-2014 |
| 20150011060 | DUAL EPI CMOS INTEGRATION FOR PLANAR SUBSTRATES - Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures. | 01-08-2015 |
| 20150111351 | Method for Manufacturing a Field Effect Transistor of a Non-Planar Type - A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench. | 04-23-2015 |
| 20150118807 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF). | 04-30-2015 |
| 20150140749 | SEMICONDUCTOR DEVICE HAVING REDUCED-DAMAGE ACTIVE REGION AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region. | 05-21-2015 |
| 20150348849 | TRANSISTOR WITH EMBEDDED STRESS-INDUCING LAYERS - A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities. | 12-03-2015 |
| 20160005660 | High Efficiency FinFET Diode - Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped. | 01-07-2016 |
| 20160020150 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES BY FORMING SOURCE/DRAIN REGIONS BEFORE GATE ELECTRODE SEPARATION - Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth. | 01-21-2016 |
| 20160035630 | METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES - One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region. | 02-04-2016 |
| 20160049338 | STRUCTURE AND METHOD FOR FINFET DEVICE - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner. | 02-18-2016 |
| 20160111335 | SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS - Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation. | 04-21-2016 |
| 20160118389 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having a high degree of freedom of layout has a first part AR | 04-28-2016 |
| 20160149038 | FACET-FREE STRAINED SILICON TRANSISTOR - The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended. | 05-26-2016 |
| 20160155826 | METHOD FOR FABRICATING FIN FIELD EFFECT TRANSISTORS | 06-02-2016 |
| 438219000 | Total dielectric isolation | 1 |
| 20160126147 | STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY - A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material. | 05-05-2016 |
| 438220000 | Isolation by PN junction only | 3 |
| 20090148988 | METHOD OF REDUCING EMBEDDED SIGE LOSS IN SEMICONDUCTOR DEVICE MANUFACTURING - Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET. | 06-11-2009 |
| 20110086478 | SYSTEMS AND METHODS FOR INTEGRATED CIRCUITS COMPRISING MULTIPLE BODY BIASING DOMAINS - Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material. | 04-14-2011 |
| 20130059421 | METHOD FOR RADIATION HARDENING AN INTEGRATED CIRCUIT - Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity. | 03-07-2013 |
| 438221000 | Dielectric isolation formed by grooving and refilling with dielectric material | 35 |
| 20080233695 | Integration method of inversion oxide (TOXinv) thickness reduction in CMOS flow without added pattern - A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VT | 09-25-2008 |
| 20090246921 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE - A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET. | 10-01-2009 |
| 20090286367 | SYSTEM AND METHOD FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES BY THE IMPLANTATION OF CARBON CLUSTERS - A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C | 11-19-2009 |
| 20100015765 | SHALLOW AND DEEP TRENCH ISOLATION STRUCTURES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion. | 01-21-2010 |
| 20100151640 | Semiconductor Devices with Active Regions of Different Heights - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor. | 06-17-2010 |
| 20100240177 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes, forming an isolation region defining a first region and a second region, injecting a first impurity of a first conductivity type into the first region and the second region, forming a first gate insulating film and a first gate electrode over the first region, forming a second gate insulating film and a second gate electrode over the second region, forming a first mask layer over a first portion of the second region to expose a second portion of the second region and the first region, and injecting a second impurity of the first conductivity type into the semiconductor substrate from a direction diagonal to a surface of the semiconductor substrate. | 09-23-2010 |
| 20100311214 | MASK-SAVING PRODUCTION OF COMPLEMENTARY LATERAL HIGH-VOLTAGE TRANSISTORS WITH A RESURF STRUCTURE - The invention relates to a method for the production of a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complimentary thereto on a substrate, wherein the first and second lateral high-voltage MOS transistors each have a conductivity type opposite a drift region, comprising the steps of providing a substrate of a first conductivity type comprising a first active region for the first lateral high-voltage MOS transistor and a second active region for the second lateral high-voltage MOS transistor, and the producing at least one first doping region of the first conductivity type in the first active region and, on the other hand, in the second active region, a drain extension region of the first conductivity type extending from the substrate surface to the interior of the substrate, which allows a simultaneous implantation of doping material in the first and second active regions through respective mask openings of one and the same mask. | 12-09-2010 |
| 20120322216 | METHOD FOR REDUCING POLY-DEPLETION IN DUAL GATE CMOS FABRICATION PROCESS - Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps. | 12-20-2012 |
| 20130130448 | METHOD FOR FORMING AND CONTROLLING MOLECULAR LEVEL SiO2 INTERFACE LAYER - The present disclosure provides a method for forming and controlling a molecular level SiO | 05-23-2013 |
| 20130149823 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 06-13-2013 |
| 20130267069 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate. | 10-10-2013 |
| 20140295630 | SiGe SRAM BUTTED CONTACT RESISTANCE IMPROVEMENT - The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods. | 10-02-2014 |
| 20140357029 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SACRIFICIAL FINS - A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor. | 12-04-2014 |
| 20150099335 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS - A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region. | 04-09-2015 |
| 20150132904 | Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET. | 05-14-2015 |
| 20150140750 | PROCESS FOR MANUFACTURING INTEGRATED DEVICE INCORPORATING LOW-VOLTAGE COMPONENTS AND POWER COMPONENTS - An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body. | 05-21-2015 |
| 20150318216 | FORMATION OF GERMANIUM-CONTAINING CHANNEL REGION BY THERMAL CONDENSATION UTILIZING AN OXYGEN PERMEABLE MATERIAL - A structure including a first semiconductor material portion and a second semiconductor material portion is provided. An oxygen impermeable hard mask is then formed directly on a surface of the first semiconductor material portion. Next, a silicon germanium layer is epitaxially formed on the second semiconductor material portion, but not the first semiconductor material portion. An oxygen permeable hard mask is then formed over the first and second semiconductor material portions. A thermal condensation process is then performed which converts the second semiconductor material portion into a germanium-containing semiconductor material portion. The oxygen permeable hard mask and the oxygen impermeable hard mask are then removed. A functional gate structure can be formed atop the remaining first semiconductor material portion and the thus formed germanium-containing semiconductor material portion. | 11-05-2015 |
| 20160043005 | METHOD FOR MANUFACTURING CMOS STRUCTURE - The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced. | 02-11-2016 |
| 20160086862 | CMOS Devices with Reduced Leakage and Methods of Forming the Same - A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a ( | 03-24-2016 |
| 20160099339 | NOVEL EMBEDDED SHAPE SIGE FOR STRAINED CHANNEL TRANSISTORS - An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors. | 04-07-2016 |
| 20160254195 | METHODS OF MODULATING STRAIN IN PFET AND NFET FINFET SEMICONDUCTOR DEVICES | 09-01-2016 |
| 20220139785 | FABRICATING METHOD OF DECREASING HEIGHT DIFFERENCE OF STI - A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed. | 05-05-2022 |
| 438222000 | With epitaxial semiconductor layer formation | 7 |
| 20090004792 | METHOD FOR FORMING A DUAL METAL GATE STRUCTURE - A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer. | 01-01-2009 |
| 20090023258 | METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTORS - A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented. | 01-22-2009 |
| 20100035394 | Formation of Active Area Using Semiconductor Growth Process without STI Integration - A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material. | 02-11-2010 |
| 20140073096 | METHOD OF DUAL EPI PROCESS FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material. | 03-13-2014 |
| 20150024561 | METHOD FOR FABRICATING A FINFET IN A LARGE SCALE INTEGRATED CIRCUIT - Systems and methods of fabricating a FinFET in large scale integrated circuit are disclosed. One illustrative method relates to a dummy gate process, wherein the fin structure is only formed in the gate electrode region by performing a photolithography process and an etching of a first dummy gate on a flat STI surface using chemical mechanical polishing, forming drain and source regions, depositing a medium dielectric layer, polishing the medium dielectric layer till the top of the first dummy gate is exposed through the chemical mechanical polishing process again, removing the dummy gate material via a dry etching and a wet etching, and continuously etching the STI dielectric layer with the hard mask formed by the medium dielectric layer, thereafter performing the deposition of real gate dielectric and gate electrode material to complete the device structure. | 01-22-2015 |
| 20160111338 | METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES - A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level. | 04-21-2016 |
| 20160155668 | Germanium FinFETs with Metal Gates and Stressors | 06-02-2016 |
| 438223000 | Having well structure of opposite conductivity type | 6 |
| 20110053325 | Method for producing semiconductor device - The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after the gate electrodes have been formed, a well, and source and drain regions are formed by impurity ion implantations with a common mask pattern in each region of the NMOS and the PMOS, using the gate electrode as a mask, whereby the number of mask steps is reduced. | 03-03-2011 |
| 438224000 | Plural wells | 5 |
| 20080242016 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS - Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression. | 10-02-2008 |
| 20080280407 | CMOS DEVICE WITH DUAL POLYCIDE GATES AND METHOD OF MANUFACTURING THE SAME - A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well and the p+ polycide gate at the N-well are formed. An interlayer dielectric layer is formed on the resultant of the silicon substrate having the n+ polycide gate and the p+ polycide gate. A first bit-line contact hole for exposing the n+ polycide gate is formed, and a second bit-line contact hole for exposing the p+ polycide gate is formed. Bit-lines with a bridge structure on the interlayer dielectric layer is formed. The bit-lines simultaneously contact the n+ polycide gate and the p+ polycide gate through the first and second bit-line contact holes. | 11-13-2008 |
| 20090291539 | METHOD FOR MANUFACTURING AND LCD DRIVER IC - A method of manufacturing an LCD driver chip includes forming a heavily doped P-type well and a heavily doped N-type well over a high voltage region of a substrate; and then forming an oxide layer over the heavily doped P-type well and the heavily doped N-type; and then simultaneously forming a first gate electrode over the heavily doped P-type well and a second gate electrode over the heavily doped N-type well including the oxide layer; and then patterning the oxide layer to form a gate insulating layer under the first and second gate electrodes and an oxide layer portion connected to lateral sides of the gate insulating layers; and then forming an insulating layer over the entire surface of the substrate including the first and second gate electrodes and the oxide layer portion; and then forming spacers on sidewalls of the first and second gate electrodes and then removing the oxide layer portion after forming the spacers; and then forming ion implantations regions over the heavily doped P-type well and the heavily doped N-type well. | 11-26-2009 |
| 20140193956 | TRANSISTOR AND FABRIATION METHOD - Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer. | 07-10-2014 |
| 20150303261 | TENSILE NITRIDE PROFILE SHAPER ETCH TO PROVIDE VOID FREE GAPFILL - A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET. | 10-22-2015 |
| 438225000 | Recessed oxide formed by localized oxidation (i.e., LOCOS) | 2 |
| 20130045577 | Manufacturing method of high voltage device - The present invention discloses a manufacturing method of a high voltage device. The high voltage device is formed in a first conductive type substrate. The high-voltage device includes: a second conductive type buried layer; a first conductive type high voltage well; and a second conductive type body. The high voltage well is formed by the same step for forming a first conductive type well or a first conductive type channel stop layer of a low voltage device formed in the same substrate. The body is formed by the same step for forming a second conductive type well of the low voltage device. | 02-21-2013 |
| 438227000 | Having well structure of opposite conductivity type | 1 |
| 20110136306 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes oxidizing a surface of a semiconductor substrate to form a first insulating film covering a first area, a second area, and a third area of the semiconductor substrate; removing the portions of the first insulating film lying on the first area and the second area; oxidizing the surface of the semiconductor substrate to form a second insulating film covering the first area and the second area and further oxidizing the third area covered with the first insulating film; and removing the portion of the second insulating film lying on from the second area and the portion of the first insulating film lying on the third area. | 06-09-2011 |
