| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438216000 | Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound | 23 |
| 20080233693 | COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) DEVICES INCLUDING A THIN-BODY CHANNEL AND DUAL GATE DIELECTRIC LAYERS AND METHODS OF MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer. | 09-25-2008 |
| 20080233694 | Transistor Device and Method of Manufacture Thereof - A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided. | 09-25-2008 |
| 20090280608 | CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT - A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate. | 11-12-2009 |
| 20090291538 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - After forming a first gate electrode and a second gate electrode on a semiconductor substrate, a silicon oxide film is formed to cover an n-channel MISFET forming region, and a p-channel MISFET forming region is exposed. Subsequently, after a first element supply film made of, for example, an aluminum oxide film is formed on the whole surface of the semiconductor substrate, a heat treatment is performed. By this means, a high-concentration HfAlO film and a low-concentration HfAlO film are formed by diffusing aluminum into the first insulating film just below the second gate electrode. Thereafter, by using a magnesium oxide film as a second element supply film, magnesium is diffused into the first insulating film just below the first gate electrode, thereby forming a high-concentration HfMgO film and a low-concentration HfMgO film. | 11-26-2009 |
| 20090298245 | Low Power Circuit Structure with Metal Gate and High-k Dielectric - FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation. | 12-03-2009 |
| 20100009502 | Semiconductor Fabrication Process Including An SiGe Rework Method - A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C. | 01-14-2010 |
| 20100124805 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS USING NITRIDATION - A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer | 05-20-2010 |
| 20100144105 | METHODS FOR FABRICATING STRESSED MOS DEVICES - Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses. | 06-10-2010 |
| 20100221878 | Hybrid Metal Fully Silicided (FUSI) Gate - A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer. | 09-02-2010 |
| 20110003444 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS - An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region. | 01-06-2011 |
| 20110081753 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal gate electrode. A first Hf-containing insulating film containing Hf, La, and O as a principal component is formed as a high dielectric constant gate insulator for an n-channel MISFET. A second Hf-containing insulating film containing Hf, Al, and O as a principal component is formed as a high dielectric constant gate insulator for a p-channel MISFET. Then, a metal film and a silicon film are formed and patterned by dry etching to thereby form first and second gate electrodes. Thereafter, parts of the first and second Hf-containing insulating films not covered with the first and second gate electrodes are removed by wet etching. At this time, a wet process with an acid solution not containing hydrofluoric acid, and another wet process with an alkaline solution are performed, and then a further wet process with an acid solution containing hydrofluoric acid is performed. | 04-07-2011 |
| 20110086477 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method may include the following processes. A semiconductor substrate is partially removed using a first insulating film having first and second portions as a mask to form first and second pillars of the semiconductor substrate. A second insulating film is formed on side surfaces of the first and second pillars. A silicon film is formed on the first and second insulating films. A first part of the silicon film, which is on upper surfaces of the first and second portions, is removed. A coating film, which covers the upper surfaces of the first and second portions, is formed over the semiconductor substrate. The coating film is partially removed to expose the first insulating film and a second part of the silicon film. The second part is on side surfaces of the first and second portions. The second part is removed by dry etching. | 04-14-2011 |
| 20110195549 | GATE STACK FOR HIGH-K/METAL GATE LAST PROCESS - A method for fabricating an integrated circuit device is disclosed. An exemplary method includes providing a substrate; forming a high-k dielectric layer over the substrate; forming a first capping layer over the high-k dielectric layer; forming a second capping layer over the first capping layer; forming a dummy gate layer over the second capping layer; performing a patterning process to form a gate stack including the high-k dielectric layer, first and second capping layers, and dummy gate layer; removing the dummy gate layer from the gate stack, thereby forming an opening that exposes the second capping layer; and filling the opening with a first metal layer over the exposed second capping layer and a second metal layer over the first metal layer, wherein the first metal layer is different from the second metal layer and has a work function suitable to the semiconductor device. | 08-11-2011 |
| 20110223728 | Transistor Device and Method of Manufacture Thereof - A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided. | 09-15-2011 |
| 20110306171 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH DIFFERENTIALLY NITRIDED GATE INSULATORS - An insulation layer is formed on a substrate having an NMOS region and a PMOS region defined therein. A first conductive layer is formed on the insulation layer in the PMOS region, leaving a portion of the insulation layer in the NMOS region exposed. Nitriding is performed to produce a first nitrogen concentration in the insulation layer in the NMOS region and a second nitrogen concentration less than the first nitrogen concentration in the insulation layer in the PMOS region. A second conductive layer is formed on the insulation layer and the first conductive layer and the first and second conductive layers and the insulation layer are patterned to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively. | 12-15-2011 |
| 20120094447 | METHOD FOR INTEGRATION OF DUAL METAL GATES AND DUAL HIGH-K DIELECTRICS IN CMOS DEVICES - The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy and a large angle for source/drain extensions; forming a second spacer, and performing ion implantation for source/drain regions; performing a thermal annealing so as to adjust of the metal gate work functions for the NMOS and PMOS devices, respectively, in the course when the dopants in the source/drain regions are activated. | 04-19-2012 |
| 20120156837 | Sacrificial Spacer Approach for Differential Source/Drain Implantation Spacers in Transistors Comprising a High-K Metal Gate Electrode Structure - In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor. | 06-21-2012 |
| 20120309144 | METHODS OF FORMING MOSFET DEVICES USING NITROGEN-INJECTED OXIDE LAYERS TO FORM GATE INSULATING LAYERS HAVING DIFFERENT THICKNESSES - In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer. | 12-06-2012 |
| 20130137227 | LOGIC AND NON-VOLATILE MEMORY (NVM) INTEGRATION - A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate. | 05-30-2013 |
| 20130217195 | Transistor Device and Method of Manufacture Thereof - A method of forming transistors and structures thereof A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS device may be doped with either an n type or a p type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided. | 08-22-2013 |
| 20140315361 | Replacement Metal Gate Process for CMOS Integrated Circuits - A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal. | 10-23-2014 |
| 20150011059 | HIGH-K METAL GATE DEVICES WITH A DUAL WORK FUNCTION AND METHODS FOR MAKING THE SAME - A layer of P-metal material having a work function of about 4.3 or 4.4 eV or less is formed over a high-k dielectric layer. Portions of the N-metal layer are converted to P-metal materials by introducing additives such as O, C, N, Si or others to produce a P-metal material having an increased work function of about 4.7 or 4.8 eV or greater. A TaC film may be converted to a material of TaCO, TaCN, or TaCON using this technique. The layer of material including original N-metal portions and converted P-metal portions is then patterned using a single patterning operation to simultaneously form semiconductor devices from both the unconverted N-metal sections and converted P-metal sections. | 01-08-2015 |
| 20150064862 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. | 03-05-2015 |
