| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438213000 | Common active region | 6 |
| 20110059583 | 3-D Single Gate Inverter - A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions. | 03-10-2011 |
| 20110223727 | CMOS Devices with Schottky Source and Drain Regions - A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band. | 09-15-2011 |
| 20120238065 | METHOD OF FABRICATING COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE - A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution. | 09-20-2012 |
| 20140099759 | APPARATUS AND METHODS FOR FORMING A MODULATION DOPED NON-PLANAR TRANSISTOR - Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed. | 04-10-2014 |
| 20140170820 | METHOD OF FABRICATING HYBRID IMPACT-IONIZATION SEMICONDUCTOR DEVICE - A method includes providing a semiconductor substrate having an active region and forming an isolation structure to isolate the active region. First and second gate structures are formed over the active region. First and second doped regions are formed within the active region of the substrate, the first doped region has a first conductivity type, the second doped region has the second conductivity type. The first and second gate structures are interposed between the first and second doped regions. | 06-19-2014 |
| 20140295629 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses. | 10-02-2014 |
