| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438211000 | Having gate surrounded by dielectric (i.e., floating gate) | 12 |
| 20080220573 | Method for manufacturing semiconductor device - On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs. | 09-11-2008 |
| 20080254582 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING SINGLE-ELEMENT TYPE NON-VOLATILE MEMORY ELEMENTS - A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits. | 10-16-2008 |
| 20080286918 | Methods for Fabricating Semiconductor Structures With Backside Stress Layers - Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication with the semiconductor device. A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region. | 11-20-2008 |
| 20080286919 | TUNNEL AND GATE OXIDE COMPRISING NITROGEN FOR USE WITH A SEMICONDUCTOR DEVICE AND A PROCESS FOR FORMING THE DEVICE - A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient which, due to their differences in sizing, results in nitridizing the tunnel oxide in its entirely but only partially nitridizing the gate oxide. Various process embodiments and completed structures are disclosed. | 11-20-2008 |
| 20080318374 | Metal Gated Ultra Short MOSFET Devices - MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal. | 12-25-2008 |
| 20090117696 | Fully logic process compatible non-volatile memory cell with a high coupling ratio and process of making the same - A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second portion above the well. The control gate includes two regions having opposite conductivity types and a third region between the two regions and under the second portion of the floating gate, and thus eliminates the parasitic depletion capacitor in the coupling path of the cell, thereby improving the coupling ratio. | 05-07-2009 |
| 20090117697 | Nonvolatile memory device including nano dot and method of fabricating the same - A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current. | 05-07-2009 |
| 20090280607 | METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY - Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body. | 11-12-2009 |
| 20110014757 | PROCESS INTEGRATION FOR FLASH STORAGE ELEMENT AND DUAL CONDUCTOR COMPLEMENTARY MOSFETS - A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction can be deposited simultaneously with a first metal layer for forming the floating gate of the flash storage element. A second gate metal layer of the PFET having a second workfunction different from the first workfunction can be deposited simultaneously with a second metal layer for forming the control gate of the flash storage element. A semiconductor layer can then be deposited over the first and second metal layers and gate metal layers and patterned to form first, second and third gates. Source and drain regions of the flash storage element, the NFET and the PFET can then be formed adjacent to the first, second and third gates, respectively. | 01-20-2011 |
| 20110070702 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. A high dielectric constant (high-k) layer and a work function metal layer are formed in sequence on a substrate. A hard mask layer is formed on the work function metal layer, where the material of the hard mask layer is lanthanum oxide. The work function metal layer is patterned by using the hard mask layer as a mask. The hard mask layer is then removed. Afterwards, a gate structure is formed on the substrate. | 03-24-2011 |
| 20150017767 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING SGTS - In a method for producing a semiconductor device, Si pillars that include i-layers, N | 01-15-2015 |
| 20150093863 | METHOD OF MAKING A FLOATING GATE NON-VOLATILE MEMORY (NVM) WITH BREAKDOWN PREVENTION - A method of making a semiconductor structure includes patterning a polysilicon layer on a substrate to form a first floating gate over a first active region in the substrate and a second floating gate over a second active region in the substrate. An opening between the first and second floating gates is filled with a dielectric material. The dielectric material is etched back so that a height of a remaining portion of the dielectric material is less than a height of the first and second floating gates. A second polysilicon layer is deposited over the first and second floating gates and the remaining portion of the dielectric material to form a word line for the first and second floating gates. | 04-02-2015 |
