| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438200000 | And additional electrical device | 43 |
| 20080227249 | CMOS Image Sensor White Pixel Performance - Methods and systems for forming a photodiode in a substrate, forming a source/drain region in the substrate and extending over at least a portion of the photodiode, and growing a thermal oxide layer over the photodiode by performing a rapid thermal anneal (RTA) process utilizing an oxidizing environment. | 09-18-2008 |
| 20080242015 | Methods of Forming CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein and Circuits Formed Thereby - Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor. | 10-02-2008 |
| 20080293196 | Method for fabricating multi-resistive state memory devices - A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays. | 11-27-2008 |
| 20090061578 | Method of Manufacturing a Semiconductor Microstructure - A method of manufacturing a semiconductor microstructure comprises: forming a standard CMOS wafer with at least one micro-electro-mechanical structure on a top surface of a silicon substrate, forming at least one sacrificial layer and one resist layer sequentially on the top surface of the CMOS wafer; forming an etching resist layer on a lower rear surface of the silicon substrate, etching the lower rear surface of the silicon base by deep reactive ion etching or wet etching to form a space corresponding to the micro-electro-mechanical structure, and etching the CMOS wafer and the sacrificial layer, respectively, to cause suspension of the micro-electro-mechanical structure. Such arrangements effectively prevent the occurrence of undercut, reduce the exposure and possibility of damage of the micro-electro-mechanical structure, and effectively save the package cost. | 03-05-2009 |
| 20090098694 | CD GATE BIAS REDUCTION AND DIFFERENTIAL N+ POLY DOPING FOR CMOS CIRCUITS - A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices. | 04-16-2009 |
| 20090111225 | CMOS STRUCTURE AND METHOD INCLUDING MULTIPLE CRYSTALLOGRAPHIC PLANES - A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation. | 04-30-2009 |
| 20100173458 | LATERAL DOUBLE DIFFUSED MOSFET TRANSISTOR WITH A LIGHTLY DOPED SOURCE - Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. | 07-08-2010 |
| 20110039378 | METHOD OF FABRICATING ESD DEVICES USING MOSFET AND LDMOS ION IMPLANTATIONS - A method of forming complementary metal-oxide-silicon logic field effect transistors, high power transistors and electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors on the same integrated circuit chip using ion implantations used to fabricate the field effect transistors and high-power transistor to simultaneously fabricate the electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors. | 02-17-2011 |
| 20120115292 | METHOD FOR INTEGRATING SONOS NON-VOLATILE MEMORY INTO A STANDARD CMOS FOUNDRY PROCESS FLOW - An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a conventional complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method only adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM. | 05-10-2012 |
| 20130288439 | Zener Diode Structure and Process - A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier. | 10-31-2013 |
| 20140087531 | Two Step Poly Etch LDMOS Gate Formation - A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material. | 03-27-2014 |
| 20140206160 | Method of Forming A Gated Diode Structure for Eliminating RIE Damage From Cap Removal - A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics. | 07-24-2014 |
| 20140273366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region. | 09-18-2014 |
| 20140335669 | EMBEDDED NON-VOLATILE MEMORY - The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F | 11-13-2014 |
| 20150140748 | INTEGRATED CIRCUIT STRUCTURE TO RESOLVE DEEP-WELL PLASMA CHARGING PROBLEM AND METHOD OF FORMING THE SAME - A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path. | 05-21-2015 |
| 20150357248 | METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 12-10-2015 |
| 20150380312 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed. | 12-31-2015 |
| 20160111340 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 04-21-2016 |
| 20160133527 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included. | 05-12-2016 |
| 438202000 | Including bipolar transistor (i.e., BiCMOS) | 12 |
| 20160163598 | METHOD OF FORMING A BICMOS SEMICONDUCTOR CHIP THAT INCREASES THE BETAS OF THE BIPOLAR TRANSISTORS - The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant. | 06-09-2016 |
| 438203000 | Complementary bipolar transistors | 2 |
| 20080227250 | CMOS device with dual-EPI channels and self-aligned contacts - A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different material than the first epitaxial region, an NMOS device formed on the second epitaxial region, and electrical contacts coupled to the PMOS and NMOS devices, wherein the electrical contacts are self-aligned. | 09-18-2008 |
| 20090117695 | BiCMOS Performance Enhancement by Mechanical Uniaxial Strain and Methods of Manufacture - A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT. | 05-07-2009 |
| 438204000 | Lateral bipolar transistor | 3 |
| 20100173459 | MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING - A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed. | 07-08-2010 |
| 20110300678 | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch - A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal. | 12-08-2011 |
| 20140302647 | SYMMETRIC BLOCKING TRANSIENT VOLTAGE SUPPRESSOR (TVS) USING BIPOLAR NPN AND PNP TRANSISTOR BASE SNATCH - A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal. | 10-09-2014 |
| 438205000 | Plural bipolar transistors of differing electrical characteristics | 1 |
| 20080318373 | Method of fabricating self-aligned bipolar transistor having tapered collector - A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions. | 12-25-2008 |
| 438207000 | Including isolation structure | 5 |
| 20080220572 | SILICON RICH BARRIER LAYERS FOR INTEGRATED CIRCUIT DEVICES - Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided. | 09-11-2008 |
| 20090011553 | THERMALLY STABLE BiCMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRANSISTOR FORMED ACCORDING TO THE METHOD - A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step. | 01-08-2009 |
| 20100022056 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR - The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate ( | 01-28-2010 |
| 20100273301 | THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRNASISTORS FORMED ACCORDING TO THE METHOD - A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step. | 10-28-2010 |
| 20100317165 | HIGH-GAIN BIPOLAR JUNCTION TRANSISTOR COMPATIBLE WITH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) PROCESS AND METHOD FOR FABRICATING THE SAME - A method for forming a bipolar junction transistor comprises forming a first well of a second conductive type for forming a collector region in a substrate including device isolation layers, wherein the substrate comprises a first conductive type, forming a second well of the first conductive type for a metal-oxide-semiconductor transistor of the second conductive type within the first well of the second conductive type, wherein the second well of the first conductive type is formed deeper than the device isolation layers, forming a shallow third well of the first conductive type for a base region within the first well of the second conductive type, wherein the shallow third well of the first conductive type is formed shallower than the device isolation layers, and simultaneously forming an emitter region within the shallow third well of the first conductive type and a plurality of collector contacts within the first well of the second conductive type by performing an ion implantation process for forming source/drain regions of the metal-oxide-semiconductor transistor of the second conductive type. | 12-16-2010 |
| 438210000 | Including passive device (e.g., resistor, capacitor, etc.) | 12 |
| 20080280406 | Semiconductor device and its manufacturing method - A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers. | 11-13-2008 |
| 20090023256 | METHOD FOR FABRICATING EMBEDDED STATIC RANDOM ACCESS MEMORY - The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask. | 01-22-2009 |
| 20090209071 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - First nanowires and second nanowires are alternately disposed and spaced apart on a first substrate in a second direction that is parallel to an adjacent major surface of the first substrate. Each of the first and second nanowires extends in a first direction that is perpendicular to the second direction, and the first and second nanowires are doped with first and second conductive types, respectively. A plurality of gate lines are formed that are at least partially disposed within the first substrate, that are spaced apart in a third direction, that extend in a fourth direction that is perpendicular to the third direction, and that partially enclose the first and second nanowires | 08-20-2009 |
| 20100112764 | Use of Poly Resistor Implant to Dope Poly Gates - A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC. | 05-06-2010 |
| 20110039379 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode. | 02-17-2011 |
| 20110045645 | HIGH-EFFICIENCY FILLER CELL WITH SWITCHABLE, INTEGRATED BUFFER CAPACITANCE FOR HIGH FREQUENCY APPLICATIONS - A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of anopposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor. | 02-24-2011 |
| 20110076813 | Semiconductor Device with both I/O and Core Components and Method of Fabricating Same - A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated. | 03-31-2011 |
| 20120108020 | LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW - A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow. | 05-03-2012 |
| 20140011333 | POLYCRYSTALLINE SILICON EFUSE AND RESISTOR FABRICATION IN A METAL REPLACEMENT GATE PROCESS - A method of fabricating an integrated circuit is disclosed (FIGS. | 01-09-2014 |
| 20140370671 | RELIABLE ELECTRICAL FUSE WITH LOCALIZED PROGRAMMING AND METHOD OF MAKING THE SAME - An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact. | 12-18-2014 |
| 20150132902 | POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature. | 05-14-2015 |
| 20160035720 | COMBINING ZTCR RESISTOR WITH LASER ANNEAL FOR HIGH PERFORMANCE PMOS TRANSISTOR - An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal. | 02-04-2016 |
