| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438198000 | Specified crystallographic orientation | 37 |
| 20080206941 | Method for manufacturing sic semiconductor device - A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer. | 08-28-2008 |
| 20080220571 | HIGH MOBILITY POWER METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS - High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device. | 09-11-2008 |
| 20080286917 | LASER PROCESSING METHOD FOR TRENCH-EDGE-DEFECT-FREE SOLID PHASE EPITAXY IN CONFINED GEOMETRICS - The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt. | 11-20-2008 |
| 20090053864 | METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING HETEROGENEOUS CRYSTALLINE ORIENTATIONS - A method for fabricating a semiconductor structure having heterogeneous crystalline orientations by forming a region including a semiconductor material having a specified crystalline orientation using an epitaxial buffer overlying a semiconductor substrate. The buffer provides a transfer body such that the semiconductor material has a crystalline orientation that differs from the crystalline orientation of a semiconductor region underlying the buffer. The method also includes fabricating a semiconductor structure having a p-type device region and an n-type device region, where a supporting semiconductor substrate is either n-type or p-type and where the semiconductor material is separated from the substrate by a buffer and has a crystalline orientation that differs from the crystalline orientation of the substrate. | 02-26-2009 |
| 20090104740 | Semiconductor device producing method - Disclosed is a producing method of a semiconductor device, including: loading a silicon substrate into a processing chamber, the silicon substrate having a silicon nitride film or a silicon oxide film on at least a portion of a surface thereof and a silicon surface being exposed from the surface; and alternately repeating a first introducing at least a silane-compound gas into the processing chamber and a second introducing at least etching gas a plurality of times to selectively grow an epitaxial film on the silicon surface, wherein the alternate repeating is started with the second introducing prior to the first introducing. | 04-23-2009 |
| 20090291537 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi | 11-26-2009 |
| 20100197088 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: forming a first-conductivity-type semiconductor region on a semiconductor layer; forming a mask member on the first-conductivity-type semiconductor region; selectively forming an opening in the mask member; etching the first-conductivity-type semiconductor region exposed to the opening to form a trench having a larger diameter than the opening and an eaves-like mask projected above the trench and made of the mask member; and forming a second-conductivity-type semiconductor region in the trench below the eaves-like mask by epitaxial growth to form a structure section in which the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region are alternately repeated in a direction generally parallel to a major surface of the semiconductor layer. | 08-05-2010 |
| 20100203689 | finFET TRANSISTOR AND CIRCUIT - A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin. | 08-12-2010 |
| 20100216286 | USE OF IN-SITU HCL ETCH TO ELIMINATE BY OXIDATION RECRYSTALLIZATION BORDER DEFECTS GENERATED DURING SOLID PHASE EPITAXY (SPE) IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DIRECT SILICON BOND SUBSTRATE (DSB) AND HYBRID ORIENTATION TECHNOLOGY (HOT) - A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an anneal and an exposure to hydrochloric acid. The anneal and acid exposure can be performed within an epitaxial reactor chamber to minimize wafer transport. | 08-26-2010 |
| 20100273300 | Semiconductor device and method for manufacturing the same - This disclosure concerns a semiconductor device comprising a convex-shaped semiconductor layer formed on a semiconductor substrate; an insulation film formed on the semiconductor substrate, the insulation film having a film thickness to the extent that a lower part of the semiconductor layer is buried; a gate electrode formed on a set of both opposed side faces via a gate insulation film; and a source region and a drain region formed on a side face side on which the gate electrode is not formed in the semiconductor layer, wherein the semiconductor layer is formed so as to dispose surfaces of a peripheral part excepting a central part on an outer side than surfaces of the central part covered by at least the gate electrode. | 10-28-2010 |
| 20110027951 | SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT - A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device. | 02-03-2011 |
| 20110076812 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors. | 03-31-2011 |
| 20110124165 | Structure and Method for Manufacturing Device with a V-Shape Channel NMosfet - A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer. | 05-26-2011 |
| 20110183481 | PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region. | 07-28-2011 |
| 20120015488 | HIGH-K GATE DIELECTRIC OXIDE - A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide. | 01-19-2012 |
| 20120045873 | Methods of Forming CMOS Transistors Using Tensile Stress Layers and Hydrogen Plasma Treatment - Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma. | 02-23-2012 |
| 20120171825 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE - In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance. | 07-05-2012 |
| 20120289009 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE - A manufacturing method for a semiconductor structure includes providing a substrate having at least a gate structure formed thereon, performing a first wet etching process to etch the substrate at two sides of the gate structure, performing a second wet etching process to etch the substrate to form a recess respectively at two sides of the gate structure, and performing a selective epitaxial growth method to form an epitaxial layer having a diamond shape with a flat bottom respectively in the recess. | 11-15-2012 |
| 20120302018 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING FIELD EFFECT TRANSISTOR - A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall. | 11-29-2012 |
| 20120322215 | COMMUNICATION - An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t | 12-20-2012 |
| 20130084682 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity. | 04-04-2013 |
| 20130115742 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION TECHNIQUE - The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions. | 05-09-2013 |
| 20130157424 | Method for improved mobility using hybrid orientaion technology (HOT) in conjunction with - A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation. | 06-20-2013 |
| 20130323891 | Integrated Circuit Device with Well Controlled Surface Proximity and Method of Manufacturing Same - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 12-05-2013 |
| 20140106520 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method with high productivity is disclosed with improved trade-off relationship between auto-doping and breakdown in alignment mark form. First to sixth epitaxial layers are grown sequentially on Si {100} main surface of an arsenic doped substrate using multilayer epitaxial technology. Epitaxial growth conditions of the first to sixth epitaxial layers are growth at atmospheric pressure and a temperature of 1,150° C. to 1,180° C., with epitaxial growth rate of 2.2 to 2.6 μm/minute. An alignment mark of depressed form whose bottom surface is the Si {100} plane is formed in the arsenic doped substrate. Every time one of the first to sixth epitaxial layers is grown on the main surface of the arsenic doped substrate, an alignment mark of depressed form is formed in the outermost epitaxial layer by a portion above the alignment mark of the layer below being transformed. | 04-17-2014 |
| 20140106521 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface. | 04-17-2014 |
| 20140106522 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 04-17-2014 |
| 20140154848 | N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer. | 06-05-2014 |
| 20140179070 | Anti-Fuses on Semiconductor Fins - A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse. | 06-26-2014 |
| 20140179071 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. | 06-26-2014 |
| 20150087120 | Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer. | 03-26-2015 |
| 20150140747 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface. | 05-21-2015 |
| 20150318382 | Methods for Forming Semiconductor Regions in Trenches - A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6. | 11-05-2015 |
| 20160027902 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., <111> and any other direction) of the semiconductor substrate. | 01-28-2016 |
| 20160064523 | SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS - A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron. | 03-03-2016 |
| 20160111285 | LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR DEVICE FABRICATION - Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures. | 04-21-2016 |
| 20160204224 | TUNNEL FIELD-EFFECT TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND SWITCH ELEMENT | 07-14-2016 |
