| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438172000 |
Having heterojunction (e.g., HEMT, MODFET, etc.)
| 97 |
| 438168000 |
Specified crystallographic orientation | 3 |
| 20110183480 | SEMICONDUCTOR DEVICE WITH GROUP III-V CHANNEL AND GROUP IV SOURCE-DRAIN AND METHOD FOR MANUFACTURING THE SAME - The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element. | 07-28-2011 |
| 20160104791 | METHOD FOR FORMING AN IMPLANTED AREA FOR A HETEROJUNCTION TRANSISTOR THAT IS NORMALLY BLOCKED - The invention relates to a method for manufacturing a heterojunction transistor ( | 04-14-2016 |
| 20160148924 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An electrode ( | 05-26-2016 |
| 438175000 |
Buried channel | 1 |
| 20080286915 | Metal-Oxide-Semiconductor High Electron Mobility Transistors and Methods of Fabrication - A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described. | 11-20-2008 |
| 438176000 |
Plural gate electrodes (e.g., dual gate, etc.) | 1 |
| 20130280870 | FABRICATION OF MOS DEVICE WITH INTEGRATED SCHOTTKY DIODE IN ACTIVE REGION CONTACT TRENCH - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer, having a body top surface and a body bottom surface; forming a source; forming an active region contact trench that extends through the source and the body into the drain, wherein bottom surface of the active region contact trench is formed to include at least a portion that is shallower than the body bottom surface; and disposing a contact electrode within the active region contact trench. | 10-24-2013 |
| 438180000 |
Self-aligned | 1 |
| 20080299715 | Method of Fabricating Self Aligned Schotky Junctions For Semiconductors Devices - A method of fabricating a self-aligned Schottky junction ( | 12-04-2008 |
| 438173000 |
Vertical channel | 1 |
| 20150087119 | COMPOUND SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, POWER SUPPLY DEVICE AND HIGH-FREQUENCY AMPLIFIER - A compound semiconductor device includes a substrate having an opening formed from the rear side thereof; a compound semiconductor layer disposed over the surface of the substrate; a local p-type region in the compound semiconductor layer, partially exposed at the end of the substrate opening; and a rear electrode made of a conductive material, disposed in the substrate opening so as to be connected to the local p-type region. | 03-26-2015 |
| 438170000 |
And bipolar device | 1 |
| 20080299714 | Planar Combined Structure of a Bipolar Junction Transistor and N-type/P-type Metal Semiconductor Field-Effect Transistors and Method for Forming the Same - A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. | 12-04-2008 |
| Entries |
| Document | Title | Date |
|---|
| 20080213955 | Schottky Diode With Minimal Vertical Current Flow - A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region. | 09-04-2008 |
| 20110136304 | Techniques to Enhance Selectivity of Electrical Breakdown of Carbon Nanotubes - Techniques are used to fabricate carbon nanotube devices. These techniques improve the selective removal of undesirable nanotubes such as metallic carbon nanotubes while leaving desirable nanotubes such as semiconducting carbon nanotubes. In a first technique, slot patterning is used to slice or break carbon nanotubes have a greater length than desired. By altering the width and spacing of the slotting, nanotubes have a certain length or greater can be removed. Once the lengths of nanotubes are confined to a certain or expected range, the electrical breakdown approach of removing nanotubes is more effective. In a second technique, a Schottky barrier is created at one electrode (e.g., drain or source). This Schottky barrier helps prevent the inadvertent removal the desirable nanotubes when using the electrical breakdown approach. The first and second techniques can be used individually or in combination with each other. | 06-09-2011 |
| 20130122669 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching. | 05-16-2013 |
| 20140154847 | SPATIAL ORIENTATION OF THE CARBON NANOTUBES IN ELECTROPHORETIC DEPOSITION PROCESS - A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. | 06-05-2014 |
| 20140295628 | MOS P-N JUNCTION SCHOTTKY DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-02-2014 |
