| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438155000 | And additional electrical device on insulating substrate or layer | 52 |
| 20080213949 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE - A method for manufacturing a substrate for a flat panel display device is disclosed. The present method uses photolithography with four masks to manufacture a TFT-LCD. After the third half-tone mask is used, the manufacturing of the TFTs and the defining of the pixel area of the substrate can be completed. The present method can avoid the alignment deviation and the generation of parasitic capacitance happened on the substrate made through the conventional photolithography with five masks. Therefore, the present method can reduce the costs and increase the yield. Moreover, the substrate for the TFT-LCD made by the present method can define a channel region in the semiconductor layer after the second half-tone mask. Hence, the subsequent manufacturing for forming a transparent conductive layer, a source, and a drain can be achieved by wet etching to effectively reduce the non-homogeneous etching for the channel region in the semiconductor layer. | 09-04-2008 |
| 20080286912 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device in which a semiconductor layer of a thin film transistor and a first electrode of a capacitor are formed of amorphous silicon and the whole or a part of source/drain regions of the semiconductor layer and the first electrode of the capacitor are crystallized by a metal induced crystallization method, and a channel region of the semiconductor layer is crystallized by a metal induced lateral crystallization method. | 11-20-2008 |
| 20090011550 | FLAT PANEL DISPLAY DEVICE AND FABRICATING METHOD THEREOF - A flat panel display device (FPD) and fabricating method thereof are disclosed, which reduce the number of masks during fabrication and prevent electro-chemical corrosion problems. In the FPD, a cell area and a pad area are defined on a substrate. A storage electrode traverses an active layer in parallel to a gate line. Source and drain regions of the active layer in the vicinity of both sides of a gate electrode are not formed below the storage electrode. An insulating interlayer over the substrate has first and second contact holes on the source and drain regions, respectively. A source electrode contacts the source region via a first contact hole and a drain electrode contacts the drain region via a second contact hole to directly contact a pixel electrode. A protective layer is disposed over the substrate including the pixel electrode. | 01-08-2009 |
| 20090053861 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is provided. A substrate is provided, and a gate is formed on the substrate. A gate dielectric layer covering the gate is formed on the substrate. A semiconductor layer is formed on the gate dielectric layer. A first shadow mask exposing parts of the semiconductor layer is provided above the semiconductor layer. A laser is irradiated on the semiconductor layer through the first shadow mask to remove parts of semiconductor layer and form a channel layer. A source and a drain are respectively formed on the channel layer at both sides of the gate. A patterned passivation layer which covers the channel layer and exposes the drain is formed. A conductive layer is formed to cover the patterned passivation layer and the drain. The conductive layer is automatically patterned by the patterned passivation layer to form a pixel electrode. | 02-26-2009 |
| 20090053862 | ACTIVE MATRIX ORGANIC EL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An active matrix organic EL display device includes pixels each having an organic EL element ( | 02-26-2009 |
| 20090061571 | Method for Manufacturing a Pixel Structure of a Liquid Crystal Display - A method for manufacturing the pixel structure of a liquid crystal display is provided. In comparison to using seven masks in the conventional lithographic processes for the pixel structure, only four masks are required in the manufacturing method of the present invention. Therefore, the cost of manufacturing is reduced. Furthermore, the unnecessary multilayer structures on the display area can be removed in the manufacturing processes, and thus, enhance the transmittance thereof. | 03-05-2009 |
| 20090075438 | METHOD OF FABRICATING ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - In a method of fabricating organic light emitting diode display, a planarization layer is annealed, cured, provided with an ashing treatment, and surface-treated to reduce roughness of the planarization layer. Therefore, it is possible to improve reduce problems such as a decrease in reflectivity and variation of color coordinates of the organic light emitting diode display due to the roughness of the planarization layer. | 03-19-2009 |
| 20090111223 | SOI DEVICE HAVING A SUBSTRATE DIODE FORMED BY REDUCED IMPLANTATION ENERGY - By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of the implantation process. Thus, enhanced reliability and stability of the substrate diode may be accomplished while also providing a high degree of compatibility with conventional manufacturing techniques. | 04-30-2009 |
| 20090233404 | FABRICATION METHOD OF MULTI-DOMAIN VERTICAL ALIGNMENT PIXEL STRUCTURE - A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively. | 09-17-2009 |
| 20090280606 | METHOD FOR FABRICATING PHOTO SENSOR - A method for fabricating a photo sensor on an amorphous silicon thin film transistor panel includes forming a photo sensor with a bottom electrode, a silicon-rich dielectric layer, and a top electrode, such that the light sensor has a high reliability. The fabrication method is compatible with the fabrication process of a thin film transistor. | 11-12-2009 |
| 20090305472 | DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle. | 12-10-2009 |
| 20100015764 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode. | 01-21-2010 |
| 20100035391 | METHOD FOR MANUFACTURING DIODE-CONNECTED TRANSISTOR AND IMAGE DISPLAY DEVICE USING THE SAME - A method for manufacturing a diode-connected transistor includes forming a silicon layer on a substrate, a first insulation film on the silicon layer, and a gate electrode on the first insulation film. The method also includes forming a source region, a channel region, and a drain region in the silicon layer and forming a second insulation film on the gate electrode. A source electrode and a drain electrode are formed on the second insulation film and are coupled to the source region and the drain region, respectively. The method further includes coupling the drain electrode to the gate electrode through a contact hole that is vertically above the channel region. | 02-11-2010 |
| 20100055850 | METHODS FOR FABRICATING PIXEL STRUCTURE, DISPLAY PANEL AND ELECTRO-OPTICAL APPARATUS - A substrate having a switching device and a storage capacitor thereon is provided. A protective layer is formed on the substrate. A patterned organic material layer is formed on the protective layer, wherein bump patterns are formed on a part of the patterned organic material layer and the patterned organic material layer has first openings to expose the partial protective layer. A reflective layer is formed on the patterned organic material layer and the exposed protective layer. A first patterned photoresist layer is formed on a part of the reflective layer, wherein the first patterned photoresist layer has second openings to expose a part of the reflective layer. The first patterned photoresist layer is used as an etching mask to form a first contact hole and a second contact hole. The first patterned photoresist layer is removed. A pixel electrode is formed on the patterned organic material layer. | 03-04-2010 |
| 20100075472 | TFT array substrate and the fabrication method thereof - A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad. | 03-25-2010 |
| 20100129969 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a highly reliable semiconductor device and a method for manufacturing the semiconductor device, where defects such as a short between a gate electrode layer and a semiconductor layer and a leakage current, which would otherwise be caused due to a coverage defect of the semiconductor layer with an insulating layer, can be prevented. In order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shape semiconductor layers, but instead, element isolation regions, which electrically insulate a plurality of element regions functioning as semiconductor elements, are formed in one semiconductor layer, i.e., a first element isolation region with high resistance and a second element isolation region which has a contact with the element region and has a conductivity type opposite to that of the source and drain regions of the element region. | 05-27-2010 |
| 20100136753 | FABRICATING METHOD OF THIN FILM TRANSISTOR - A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer. | 06-03-2010 |
| 20100159650 | Methods of fabricating semiconductor device having capacitorless one-transistor memory cell - A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern. | 06-24-2010 |
| 20100173457 | Highly scalable thin film transistor - Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels. | 07-08-2010 |
| 20100210078 | Manufacturing Method of Semiconductor Device - A single crystal semiconductor layer is provided over a base substrate with a second insulating film, a first conductive film, and a first insulating film interposed therebetween; an impurity element having one conductivity type is selectively added to the single crystal semiconductor layer, using a first resist mask; the first resist mask is removed; a second conductive film is formed over the single crystal semiconductor layer; a second resist mask having a depression is formed over the second conductive film; a first etching is performed on the first insulating film, the first conductive film, the second insulating film, the single crystal semiconductor layer, and the second conductive film, using the second resist mask; and a second etching with accompanying side-etching is performed on a part of the first conductive film to form a pattern of a gate electrode layer. | 08-19-2010 |
| 20100261320 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps. | 10-14-2010 |
| 20100317163 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof - A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body. The channel-forming region within the isolated castellated-gate MOSFET region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. One or more of the trench isolated regions may contain at least one type or polarity of logic and/or memory computing device. Alternately or additionally, one or more type of Logic and/or memory device may be incorporated within vertically displaced regions above the active body region of the semiconductor wafer, embedded within Interlevel Dielectric Layers. | 12-16-2010 |
| 20110027950 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR - A method is provided for integrating a germanium photodetector with a CMOS circuit. The method comprises: forming first and second isolation regions in a silicon substrate; forming a gate electrode in the first isolation region; implanting source/drain extensions in the silicon substrate adjacent to the gate electrode; forming a first sidewall spacer on the gate electrode; implanting source/drain regions in the silicon substrate; removing the first sidewall spacer from the gate electrode; forming a first protective layer over the first and second isolation regions; removing a portion of the first protective layer to form an opening over the second isolation region; forming a semiconductor material comprising germanium in the opening; forming a second protective layer over the first and second isolation regions; selectively removing the first and second protective layers from the first isolation region; and forming contacts to the transistor and to the semiconductor material. | 02-03-2011 |
| 20110086474 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE - A method of manufacturing a thin film transistor substrate includes a first process in which a gate line pattern including a gate line and a gate electrode is formed with a first conductive material on a substrate using a first mask, a second process in which a first insulating layer is formed on the substrate and a data line pattern including a data line, a source electrode, and a drain electrode is formed with a second conductive material using a second mask, and a third process in which a second insulating layer is formed on the substrate and a pixel electrode connected to the drain electrode is formed on the second insulating layer with a third conductive material. | 04-14-2011 |
| 20110092034 | ZERO CAPACITOR RAM WITH RELIABLE DRAIN VOLTAGE APPLICATION AND METHOD FOR MANUFACTURING THE SAME - The following discloses and describes a zero capacitor RAM as well as a method for manufacturing the same. The zero capacitor RAM includes an SOI substrate. This SOI substrate is composed of a stacked structure of a silicon substrate, an embedded insulation film and a silicon layer. This layer is patterned into line types to constitute active patterns. Moreover, a first insulation layer forms between the active patterns and gates form on the active patterns as well as the first insulation layer to extend perpendicularly to the active patterns. In addition, a source forms in the active pattern on one side of each gate, a drain forms in the active pattern on the other side of each gate which is achieved by filling a metal layer. Continuing, a contact plug forms between the gates on the source and an interlayer dielectric forms on the contact plug in addition to the gates Finally, a bit line forms on the interlayer dielectric to extend perpendicularly to the gates and come into contact with the drain. | 04-21-2011 |
| 20110177660 | DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY - A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device. | 07-21-2011 |
| 20110201161 | METHOD OF FORMING A BURIED PLATE BY ION IMPLANTATION - A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor. | 08-18-2011 |
| 20120171821 | METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES - A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided. | 07-05-2012 |
| 20130011976 | FABRICATING METHOD OF PIXEL STRUCTURE - A fabricating method of a pixel structure is provided. A substrate has an array of pixel areas. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is formed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. The source and the drain is formed on two sides of the semiconductor layer. A passivation layer is formed on the substrate to cover the data line, the source and the drain. A pixel electrode is formed in each of the pixel areas, and the pixel electrode is electrically connected with the drain through the contact window. | 01-10-2013 |
| 20130102115 | METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE - The disclosed method for manufacturing an active matrix substrate includes a step in which a first mask is used to pattern a first conductive layer G, CS, and S, a step in which a second mask is used to pattern a first insulating layer, a step in which a third mask is used to pattern a semiconductor layer, a step in which a fourth mask is used to pattern a second conductive later, a step in which a fifth mask is used to pattern a second insulating layer, and a step in which a sixth mask is used to pattern a third conductive layer. | 04-25-2013 |
| 20130178021 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity. | 07-11-2013 |
| 20130309819 | ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATING METHOD THEREOF - An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to extend in the first direction, a data line formed to extend in a second direction, a thin film transistor formed at an intersection between the gate line and the data line, wherein the thin film transistor includes a gate line, a gate insulating layer, an active layer, a source electrode, and a drain electrode, a passivation film formed on the substrate including the thin film transistor, a pixel electrode formed on the passivation film located on a pixel region defined by the gate line and the data line, the pixel electrode being electrically connected to the drain electrode, a common electrode formed on the passivation film, and a common electrode connection line connected to the common electrode and the common line, wherein the common electrode connection line overlaps with the common line and the drain electrode. | 11-21-2013 |
| 20140080270 | BACKPLANE FOR FLAT PANEL DISPLAY APPARATUS, FLAT PANEL DISPLAY APPARATUS, AND METHOD OF MANUFACTURING THE BACKPLANE - A backplane includes: a substrate, a pixel electrode, which includes a transparent conductive material, on the substrate, a capacitor first electrode formed on the same layer as the pixel electrode, a first protection layer covering the capacitor first electrode and an upper edge of the pixel electrode, a gate electrode of a thin film transistor (TFT) formed on the first protection layer, a capacitor second electrode formed on the same layer as the gate electrode, a first insulating layer that covers the gate electrode and the capacitor second electrode, a semiconductor layer that is formed on the first insulating layer and includes a transparent conductive material, a second insulating layer covering the semiconductor layer, source and drain electrodes of the TFT that are formed on the second insulating layer, and a third insulating layer that covers the source and drain electrodes and exposes the pixel electrode. | 03-20-2014 |
| 20140141574 | FLAT PANEL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A flat panel display device having increased capacitance and a method of manufacturing the flat panel display device are provided. A flat panel display device includes: a plurality of pixel areas, each located at a crossing region of a gate line, a data line, and a common voltage line; a thin film transistor (TFT) located at a region where the gate line and the data line cross each other, the TFT including a gate electrode, a source electrode, and a drain electrode; and a storage capacitor located at a region where the common voltage line and the drain electrode cross each other, the storage capacitor including first, second, and a third storage electrodes. | 05-22-2014 |
| 20140141575 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity. | 05-22-2014 |
| 20140242760 | SEMICONDUCTOR RADIO FREQUENCY SWITCH WITH BODY CONTACT - The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element. | 08-28-2014 |
| 20150056759 | Pixel, a Storage Capacitor, and a Method for Forming the Same - A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer. | 02-26-2015 |
| 20150056760 | SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE - A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough. | 02-26-2015 |
| 20150064853 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region. | 03-05-2015 |
| 20150104910 | TFT FLAT SENSOR AND MANUFACTURING METHOD THEREFOR - A TFT flat sensor comprises pixel units each comprising: a common electrode and a common electrode insulating layer on a substrate, wherein a first via hole is provided in the common electrode insulating layer at a location corresponding to the common electrode; a gate electrode on the common electrode insulating layer; a first conductive film layer on the common electrode and the gate electrode wherein the first conductive film layer contacts the common electrode through a first via hole; a gate insulating layer, an active layer, a drain electrode and a source electrode, a second conductive film layer, a protection layer and a third conductive film layer on the first conductive film layer; a second via hole is provided in the protection layer at a location corresponding to the source electrode through which the third conductive film layer contacts the source electrode. | 04-16-2015 |
| 20150118804 | NON-VOLATILE MEMORY DEVICE AND PRODUCTION METHOD THEREOF - A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced. | 04-30-2015 |
| 20150294869 | METHOD FOR MANUFACTURING LOW-TEMPERATURE POLYSILICON THIN FILM TRANSISTOR AND ARRAY SUBSTRATE - The present invention discloses a method for manufacturing a low-temperature polysilicon thin film transistor and an array substrate, which is used for simplifying manufacturing process procedures of the thin film transistor. The method includes steps of: forming an a-Si layer on a substrate; forming an impurity film on the a-Si layer, positions of the impurity film corresponding to a source doping layer to be formed and a drain doping layer to be formed respectively; and converting the a-Si layer into a polysilicon layer, and during the conversion from the a-Si layer into the polysilicon layer, ions in the impurity film being implanted into regions in the polysilicon layer contacting with the impurity film to form the source doping layer and the drain doping layer. In particular, an excimer laser annealing process is performed on the a-Si layer and the impurity film, so that the source doping layer is formed in a region corresponding to the source doping layer to be formed, the drain doping layer is formed in a region corresponding to the drain doping layer to be formed and the polysilicon layer is formed in regions except the source doping layer and the drain doping layer. | 10-15-2015 |
| 20150311318 | THIN-FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING SAME, AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS INCLUDING THIN-FILM TRANSISTOR SUBSTRATE - A thin film transistor (TFT) substrate, an organic light-emitting display apparatus including the TFT substrate, and a method of manufacturing the TFT substrate that enable simple manufacturing processes and a decrease in the interference between a capacitor and other interconnections are disclosed. The TFT substrate may include a substrate, a TFT arranged on the substrate, the TFT including an active layer, a gate electrode, a source electrode, and a drain electrode, a pixel electrode electrically connected to one of the source electrode and the drain electrode, and a capacitor including a lower capacitor electrode and an upper capacitor electrode, the lower capacitor electrode formed from the same material as the active layer and arranged on the same layer as the active layer, and the upper capacitor electrode formed from the same material as the pixel electrode. | 10-29-2015 |
| 20150340407 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided The semiconductor device includes a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround a side and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer, a source region formed in the active region connected to the semiconductor substrate, and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures. | 11-26-2015 |
| 20160013220 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE AND METHOD FOR FORMING THROUGH HOLE | 01-14-2016 |
| 20160056249 | BACKSIDE SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type. | 02-25-2016 |
| 20160064418 | ARRAY SUBSTRATE AND METHOD FOR FABRICATING ARRAY SUBSTRATE, AND DISPLAY DEVICE - The present invention discloses an array substrate, a method for fabricating an array substrate, and a display device, the array substrate includes: a base substrate; a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact with the active layer through a first via hole and a second via hole passing through the gate isolation layer and the second insulating layer, respectively; the pixel electrode is in contact with the drain electrode. | 03-03-2016 |
| 20160064426 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode. | 03-03-2016 |
| 20160099249 | INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR - At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure. | 04-07-2016 |
| 20160197018 | INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH DIFFERENT VOLTAGE THRESHOLDS | 07-07-2016 |
| 20160197106 | PHOTO MASK AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME | 07-07-2016 |
| 20170236850 | PATTERNING LAYER STACKS FOR ELECTRONIC DEVICES | 08-17-2017 |
