| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438150000 | Specified crystallographic orientation | 16 |
| 20080227241 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a <110> direction. These wafers are surface-bonded together so that the <110>directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in <110> direction to the upper wafer, and the other of which is equal in <110> direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained. | 09-18-2008 |
| 20080242010 | At least penta-sided-channel type of finfet transistor - An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator. | 10-02-2008 |
| 20080248615 | CMOS STRUCTURE FOR BODY TIES IN ULTRA-THIN SOI (UTSOI) SUBSTRATES - The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in the UTSOI region and at least one second device located in the bulk-Si region. The UTSOI region has an SOI layer atop an insulating layer, wherein the SOI layer has a thickness of less than about 40 nm. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. | 10-09-2008 |
| 20080261354 | STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES - The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention. | 10-23-2008 |
| 20080311708 | HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES - A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation. | 12-18-2008 |
| 20090035897 | HYBRID ORIENTATION CMOS WITH PARTIAL INSULATION PROCESS - The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain diffusion regions of the device in an epitiaxial semiconductor material such that they are situated on a buried insulating layer that extends partially underneath the body of the second semiconductor device. The second semiconductor device, together with the first semiconductor device, is both located atop the buried insulating layer. Unlike the first semiconductor device in which the body thereof is floating, the second semiconductor device is not floating. Rather, it is in contact with an underlying first semiconducting layer. | 02-05-2009 |
| 20090075436 | METHOD OF MANUFACTURING A THIN-FILM TRANSISTOR - A method of manufacturing a thin-film transistor (TFT) includes forming an amorphous silicon layer on a substrate, crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a laser beam, and selectively etching a protrusion formed at a grain boundary in the polycrystalline silicon layer using a hydroxide etchant. | 03-19-2009 |
| 20090130803 | STRESSED FIELD EFFECT TRANSISTOR AND METHODS FOR ITS FABRICATION - A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate. | 05-21-2009 |
| 20090258464 | METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER - Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer. | 10-15-2009 |
| 20100112763 | Semiconductor device including gate stack formed on inclined surface and method of fabricating the same - A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction. | 05-06-2010 |
| 20100317161 | METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER - To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H | 12-16-2010 |
| 20110165738 | Field effect transistor and method for manufacturing the same - A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode. | 07-07-2011 |
| 20110223724 | Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same - A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes. | 09-15-2011 |
| 20160155707 | RF SOI SWITCH WITH BACKSIDE CAVITY AND THE METHOD TO FORM IT | 06-02-2016 |
| 20160181114 | Method for Fabricating Multiple Layers of Ultra Narrow Silicon Wires | 06-23-2016 |
| 20170236902 | GROWING GROUPS III-V LATERAL NANOWIRE CHANNELS | 08-17-2017 |
