| Entries |
| Document | Title | Date |
|---|
| 20080227226 | Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device - A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line. | 09-18-2008 |
| 20080248599 | Rapid Thermal Anneal Equipment and Method Using Sichrome Film - A method of determining the degree of calibration of an RTP chamber ( | 10-09-2008 |
| 20090042321 | APPARATUS AND METHOD FOR PLASMA DOPING - Gas supplied to gas flow passages of a top plate from a gas supply device by gas supply lines forms flow along a vertical direction along a central axis of a substrate, so that the gas blown from gas blow holes can be made to be uniform, and a sheet resistance distribution is rotationally symmetric around a substrate center. | 02-12-2009 |
| 20090053836 | Method of wafer level transient sensing, threshold comparison and arc flag generation/deactivation - A method for processing a semiconductor wafer in a plasma reactor comprises sensing transient voltages or currents on a conductor coupled to the wafer and providing a first comparator for comparing the transient voltages or currents with a threshold level stored in the comparator. The method further includes transmitting from the comparator an arc flag signal whenever a transient voltage or current is sensed that exceeds the threshold level, and deactivating the power generator in response to the arc flag signal. | 02-26-2009 |
| 20090061541 | SEMICONDUCTOR FABRICATION SYSTEM, AND FLOW RATE CORRECTION METHOD AND PROGRAM FOR SEMICONDUCTOR FABRICATION SYSTEM - Zero point shift based on thermal siphon effect occurring actually when a substrate is processed is detected accurately and corrected suitably. The semiconductor fabrication system comprises a gas supply passage ( | 03-05-2009 |
| 20090061542 | Method and apparatus for diagnosing status of parts in real time in plasma processing equipment - Apparatus and methods for diagnosing status of a consumable part of a plasma reaction chamber, the consumable part including at least one conductive element embedded therein. The method includes the steps of: coupling the conductive element to a power supply so that a bias potential relative to the ground is applied to the conductive element; exposing the consumable part to plasma erosion until the conductive element draws a current from the plasma upon exposure of the conductive element to the plasma; measuring the current; and evaluating a degree of erosion of the consumable part due to the plasma based on the measured current. | 03-05-2009 |
| 20090068769 | Method and Apparatus for Plasma Processing - An object of the invention is to provide a method and an apparatus for plasma processing which can accurately monitor an ion current applied to the surface of a sample. | 03-12-2009 |
| 20090081816 | LIGHT EMITTING DEVICE AND PRODUCTION SYSTEM OF THE SAME - To provide a light emitting device without nonuniformity of luminance, a correcting circuit for correcting a video signal supplied to each pixel to a light emitting device. The correcting circuit is stored with data of a dispersion of a characteristic of a driving TFT among pixels and data of a change over time of luminance of a light emitting element. Further, by correcting a video signal inputted to the light emitting device in conformity with a characteristic of the driving TFT of each pixel and a degree of a deterioration of the light emitting element based on the over-described two data, nonuniformity of luminance caused by a deterioration of an electroluminescent layer and nonuniformity of luminance caused by dispersion of a characteristic of the driving TFT are restrained. | 03-26-2009 |
| 20090130783 | METHOD OF FABRICATING AN ULTRA-SMALL CONDENSER MICROPHONE - In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced. | 05-21-2009 |
| 20090142860 | SYSTEM AND METHOD FOR ENHANCED CONTROL OF COPPER TRENCH SHEET RESISTANCE UNIFORMITY - A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches. | 06-04-2009 |
| 20090162953 | PREDICTING DOSE REPEATABILITY IN AN ION IMPLANTATION - An approach for predicting dose repeatability in an ion implantation is described. In one embodiment, an ion source is tuned to generate an ion beam with desired beam current. Beam current measurements are obtained from the tuned ion beam. The dose repeatability is predicted for the ion implantation as a function of the beam current measurements. | 06-25-2009 |
| 20090215202 | CONTROLLED EDGE RESISTIVITY IN A SILICON WAFER - An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer. | 08-27-2009 |
| 20090325322 | Non-Destructive Laser Optical Integrated Circuit Package Marking - A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface. | 12-31-2009 |
| 20090325323 | AQUEOUS DISPERSION FOR CHEMICAL MECHANICAL POLISHING, PRODUCTION METHOD THEREOF, AND CHEMICAL MECHANICAL POLISHING METHOD - There is provided an aqueous dispersion for chemical mechanical polishing that comprises abrasives comprising:
| 12-31-2009 |
| 20100093113 | SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor manufacturing apparatus includes: an ion source and a beam line for introducing an ion beam into a target film which is formed over a wafer with an insulating film interposed therebetween; a flood gun for supplying the target film with electrons for neutralizing charges contained in the ion beam; a rotating disk for subjecting the target film to mechanical scanning of the ion beam in two directions composed of r-θ directions; a rear Faraday cage for measuring the current density produced by the ion beam; a disk-rotational-speed controller and a disk-scanning-speed controller for changing the scanning speed of the target film; and a beam current/current density measuring instrument for controlling, according to the current density, the scanning speed of the target film. | 04-15-2010 |
| 20100151596 | METHOD FOR ALIGNING OPTICAL PACKAGES - A method is given for aligning an optical package comprising a laser, a wavelength conversion device, at least one adjustable optical component and at least one actuator. The adjustable optical component may be moved to a command position by applying a pulse width modulated signal to the actuator. The command position represents an optimized alignment of the laser and wavelength conversion device. The actual position of the adjustable may be measured by measuring an output of a position measuring circuit, which may measure the voltage amplitude of an oscillation in a resonator tank circuit during an “off” period of the pulse-width modulated signal. The resonator tank circuit may comprise a capacitive element electrically coupled to the electrically conductive coil. The pulse-width modulated signal may then be adjusted to compensate for any difference in the actual position and the command position of the adjustable optical component. Additional embodiments are disclosed and claimed. | 06-17-2010 |
| 20100178717 | METHOD OF MANUFACTURING MEMS DEVICE - A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside. | 07-15-2010 |
| 20100190273 | METHOD FOR MANUFACTURING HIGH-FREQUENCY SIGNAL TRANSMISSION CIRCUIT AND HIGH-FREQUENCY SIGNAL TRANSMISSION CIRCUIT DEVICE - A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region. | 07-29-2010 |
| 20100216260 | PLASMA ETCHING METHOD AND APPARATUS, AND METHOD OF MANUFACTURING LIQUID EJECTION HEAD - The plasma etching method includes: an etching step of placing, on a stage in a chamber, a substrate in which a prescribed mask pattern is formed by a protective film on a surface of a material to be etched, generating a plasma in the chamber while supplying processing gas to the chamber, and etching a portion of the material corresponding to an opening portion in the mask pattern; a voltage measurement step of, during the etching in the etching step, measuring a voltage at the surface of the material on a side where the mask pattern is formed, through a conductive member that is placed in contact with the surface of the material on the side where the mask pattern is formed; and a control step of controlling an etching condition in the etching step in accordance with a measurement result obtained in the voltage measurement step. | 08-26-2010 |
| 20100227420 | INDUCTIVELY COUPLED PLASMA REACTOR HAVING RF PHASE CONTROL AND METHODS OF USE THEREOF - Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the RF phase difference between the ICP source (a first RF source) and the substrate bias (a second RF source) for plasma processing reactors used in the semiconductor industry. Control of the RF phase difference provides a powerful knob for fine process tuning. For example, control of the RF phase difference may be used to control one or more of average etch rate, etch rate uniformity, etch rate skew, critical dimension (CD) uniformity, and CD skew, CD range, self DC bias control, and chamber matching. | 09-09-2010 |
| 20110117682 | APPARATUS AND METHOD FOR PLASMA PROCESSING - Disclosed is an apparatus and method for plasma processing, which facilitates to constantly control a RF voltage supplied to a substrate supporting member by precisely detecting an inductive RF voltage induced to the substrate supporting member for a plasma, the apparatus comprising: a substrate supporting member for supporting a substrate, installed in a reaction room of a processing chamber; a RF generator for supplying a RF voltage to the substrate supporting member so as to form plasma in the reaction room; and a matching device for matching impedance of the RF voltage to be supplied to the substrate supporting member from the RF generator, wherein the matching device comprises: a matching unit for matching the impedance of RF voltage; and an inductive RF detecting unit which an inductive RF detecting voltage by removing noise frequency elements except a waveform of the RF voltage from a waveform of an inductive RF voltage induced to the substrate supporting member, and supplies the detected inductive RF detecting voltage to the RF generator so as to control the RF voltage. | 05-19-2011 |
| 20110136270 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, the semiconductor device including an integrated circuit having plural connection terminals arranged on a predetermined local region of the integrated circuit, plural metal bumps, and a wiring layer connected to at least a portion of the connection terminals via the plural metal bumps, the method includes the steps of a) measuring an impedance value of the predetermined local region of the integrated circuit, b) determining whether the measured impedance value matches a predetermined impedance value, c) determining positions of the plural metal bumps in accordance with the determination result of step b), d) forming the plural metal bumps on the positions determined in step c), and e) forming the wiring layer on the plural metal bumps. | 06-09-2011 |
| 20110281377 | METHOD FOR SEPARATING AND TRANSFERRING IC CHIPS - [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. | 11-17-2011 |
| 20110306153 | METHOD OF MANUFACTURING MEMS DEVICE - A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside. | 12-15-2011 |
| 20120003760 | GLITCH CONTROL DURING IMPLANTATION - An ion implantation system and method are disclosed in which glitches in voltage are minimized by modifications to the power system of the implanter. These power supply modifications include faster response time, output filtering, improved glitch detection and removal of voltage blanking. By minimizing glitches, it is possible to produce solar cells with acceptable dose uniformity without having to pause the scan each time a voltage glitch is detected. For example, by shortening the duration of a voltage to about 20-40 milliseconds, dose uniformity within about 3% can be maintained. | 01-05-2012 |
| 20120009691 | METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DISPLAY - A pixel includes an organic light emitting diode, a first transistor having a source coupled to a first power source, a control gate coupled to a first node, and a drain coupled to a second node, wherein the first transistor includes a floating gate and an insulating layer between the floating gate and the control gate, a second transistor having a source coupled to a data line, a drain coupled to the first node, and a gate coupled to a scan line, a third transistor having a source coupled to the second node, a drain coupled to the organic light emitting diode, and a gate coupled to one of a light emitting control line and the scan line, and a capacitor coupled between the first power source and the first node. | 01-12-2012 |
| 20120083051 | APPARATUS AND METHODS FOR ELECTRICAL MEASUREMENTS IN A PLASMA ETCHER - Apparatus and methods for plasma etching are disclosed. In one embodiment, an apparatus for etching a plurality of features on a wafer comprises a chamber, a feature plate disposed in the chamber for holding the wafer, a gas channel configured to receive a plasma source gas, an anode disposed above the feature plate, a cathode disposed below the feature plate, a radio frequency power source configured to provide a radio frequency voltage between the anode and the cathode so as to generate plasma ions from the plasma source gas, a pump configured to remove gases and etch particulates from the chamber, and a clamp configured to clamp the wafer against the feature plate. The clamp includes at least one measurement hole for passing a portion of the plasma ions to measure a DC bias of the feature plate. | 04-05-2012 |
| 20120083052 | Flexible Packaging for Chip-on-Chip and Package-on-Package Technologies - In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size. | 04-05-2012 |
| 20120115257 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition. | 05-10-2012 |
| 20120129277 | METHODS AND APPARATUSES FOR DETERMINING THICKNESS OF A CONDUCTIVE LAYER - Methods and apparatuses for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of impedance. The calibration curve may be an analytic function having infinite number terms, such as trigonometric, hyperbolic, and logarithmic, or a continuous plurality of functions, such as lines. High accuracy allows the omission of optical sensors, and use of eddy current sensors for endpoint detection, transition call detection, and closed loop control in which a process parameter is changed based on the measured magnetic flux density change in one or more processing zones. | 05-24-2012 |
| 20120196386 | METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A method of manufacturing a semiconductor module is provided. The method includes forming semiconductor chips on a bare substrate, performing a burn-in process on the bare substrate including the semiconductor chips, sorting semiconductor chips that exceed a predetermined level of operability determined by testing electrical driving in the semiconductor chips on the burned-in bare substrate, separating the semiconductor chips from one another by cutting the bare substrate, and directly mounting the module semiconductor chips on a module substrate. | 08-02-2012 |
| 20120244645 | ELECTROSTATIC POST EXPOSURE BAKE APPARATUS AND METHOD - An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP. | 09-27-2012 |
| 20120276661 | HIGH SENSITIVITY EDDY CURRENT MONITORING SYSTEM - A method of chemical mechanical polishing a substrate includes polishing a metal layer on the substrate at a polishing station, monitoring thickness of the metal layer during polishing at the polishing station with an eddy current monitoring system, and controlling pressures applied by a carrier head to the substrate during polishing of the metal layer at the polishing station based on thickness measurements of the metal layer from the eddy current monitoring system to reduce differences between an expected thickness profile of the metal layer and a target profile, wherein the metal layer has a resistivity greater than 700 ohm Angstroms. | 11-01-2012 |
| 20120276662 | EDDY CURRENT MONITORING OF METAL FEATURES - A method of chemical mechanical polishing a substrate includes polishing a plurality of discrete separated metal features of a layer on the substrate at a polishing station, using an eddy current monitoring system to monitor thickness of the metal features in the layer, and controlling pressures applied by a carrier head to the substrate during polishing of the layer at the polishing station based on thickness measurements of the metal features from the eddy current monitoring system to reduce differences between an expected thickness profile of the metal feature and a target profile. | 11-01-2012 |
| 20120309117 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device wherein a semiconductor element is sealed with mold resin, a MOS structure is on an upper side of the semiconductor chip, and a PN junction region is on a back side of the semiconductor chip, comprises: obtaining an in-plane distribution of impurity concentration of the PN junction region in the semiconductor chip before encapsulation so that an in-plane distribution of breakdown voltage and leakage current of the semiconductor chip become uniform after encapsulation; forming the PN junction region having the obtained in-plane distribution of impurity concentration on the back side of the semiconductor chip; and sealing the semiconductor chip with the resin after forming the PN junction region. | 12-06-2012 |
| 20120315711 | Adjusting Capacitance of Capacitors without Affecting Die Area - According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor. | 12-13-2012 |
| 20120329179 | Capacitance modification without affecting die area - According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor. | 12-27-2012 |
| 20130084656 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - An automatic analyzer detects voltage applied across electrodes, and judges whether voltage value falls within set voltage range. When the detected voltage value is lower than minimum value of set voltage range, the analyzer calculates the deficient amount of base solution based on the detected voltage value, controls a valve to supply the deficient amount of base solution, then, performs operation control of the valve so as to keep the prescribed amount of plating solution in plating solution tank, and discharges plating solution. When the detected voltage value is higher than maximum value of set voltage range, the analyzer calculates the excess amount of base solution based on the detected voltage value, controls a valve, and supplies pure water into the tank so that the base solution concentration falls within prescribed range to dilute plating solution, then controls a valve, and discharges plating solution so as to keep prescribed amount. | 04-04-2013 |
| 20130210173 | Multiple Zone Temperature Control for CMP - To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed. | 08-15-2013 |
| 20130236992 | TESTING METHOD, TESTING DEVICE, AND MANUFACTURING METHOD FOR LASER DIODE - In a testing method for an LD, an LD die is held. Then, electric current increasing with a fixed increment and having a sequence of current values is supplied to the LD die to drive the LD die to emit light and a sequence of voltage values across the LD die and corresponding to the sequence of current values, respectively, is metered. A sequence of power values corresponding to the sequence of current values, respectively, is also metered. Next, an electro-optical property of the LD die is determined according to the sequence of current values, the sequence of voltage values, and the sequence of power values. Finally, if the LD die is determined to be qualified based upon the electro-optical property of the LD die, the LD die is packaged into the LD. | 09-12-2013 |
| 20130244348 | FINE TUNING HIGHLY RESISTIVE SUBSTRATE RESISTIVITY AND STRUCTURES THEREOF - Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity. | 09-19-2013 |
| 20130344626 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND FILM FORMATION DEVICE - A semiconductor substrate having a surface is prepared. An electrical conductor film is formed on a region including the surface of the semiconductor substrate. The step of forming the electrical conductor film includes the steps of measuring, at a point of time when the electrical conductor film is partially formed, a characteristic related to at least one of alternating current loss and alternating current electrical conductivity of the electrical conductor film partially formed, and adjusting a film formation condition for forming the electrical conductor film based on the characteristic. Thereby, a surface roughness of the film being formed can be fed back to the film formation condition. | 12-26-2013 |
| 20140017821 | On-SOI integrated circuit comprising a triac for protection against electrostatic discharges - An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well. | 01-16-2014 |
| 20140030826 | POLISHING METHOD - A method of polishing a wafer having a Ru film and a Ta film or TaN film beneath the Ru film is provided. This polishing method includes: polishing the Ru film by bringing the wafer into sliding contact with a polishing pad; measuring a thickness of the Ru film by a film thickness sensor while polishing the Ru film; calculating a derivative value of an output value of the film thickness sensor; detecting a predetermined point of change in the derivative value; and determining a removal point of the Ru film from a point of time when the point of change is detected. | 01-30-2014 |
| 20140038317 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number. | 02-06-2014 |
| 20140242732 | ION IMPLANTATION APPARATUS AND METHOD OF DETERMINING STATE OF ION IMPLANTATION APPARATUS - An ion implantation apparatus according to an embodiment includes an ion implantation unit, a position detection unit, a charge supply unit, a current value detection unit, and a determination unit. The ion implantation unit scans the surface of a substrate with an ion beam containing positively charged ions and implants the ions into the substrate. The position detection unit detects the scan position of the ion beam on the substrate. The charge supply unit generates a plasma, emits electrons contained in the plasma, and supplies the electrons to the substrate. The current value detection unit detects a current value that changes in accordance with the amount of electrons emitted by the charge supply unit. The determination unit determines the charge build-up state of the substrate based on a change in the current value, the change being accompanied by a change in the scan position. | 08-28-2014 |
| 20140273298 | Techniques for Quantifying Fin-Thickness Variation in FINFET Technology - Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices. | 09-18-2014 |
| 20140329339 | DEFECT DETECTION AND CORRECTION OF PIXEL CIRCUITS FOR AMOLED DISPLAYS - A method of testing an array-based semiconductor device for defects during fabrication of the semiconductor device detects defects in said entities forming the semiconductor device at an intermediate stage in the fabrication of multiple types of entities forming the semiconductor device; determines whether the detected defects exceed preselected thresholds for the types of entities in which said detects are detected; if the detected defects do not exceed said preselected thresholds, continues the fabrication of the semiconductor device; and if the detected defects exceed said preselected thresholds, identifies the types of defects detected, repairs the identified defects, and continues the fabrication of the semiconductor device. | 11-06-2014 |
| 20140329340 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS - After a substrate implanted with impurities is heated to a preheating temperature, the front surface of the substrate is heated to a target temperature by irradiating the front surface of the substrate with a flash of light. Further, the flash irradiation is continued to maintain the temperature of the front surface near the target temperature for a predetermined time period. At this time, a flash irradiation time period in the flash heating step is made longer than a heat conduction time period required for heat conduction from the front surface of the substrate to the back surface thereof, and a difference in temperature between the front and back surfaces of the substrate is controlled to be always not more than one-half of an increased temperature from the preheating temperature to the target temperature during the flash irradiation. This alleviates the concentration of stresses resulting from a difference in thermal expansion between the front and back surfaces of the substrate to thereby prevent the cracking of the substrate. | 11-06-2014 |
| 20140342472 | Substrate Processing Based On Resistivity Measurements - The resistivity of a silicon boule may vary along its length, thereby making a uniform ion implantation process sub-optimal. A system and method for measuring a resistivity of a substrate, and processing the substrate based on that measured resistivity is disclosed. The system includes a resistivity measurement system, a controller and an ion implanting system, where the controller configures the ion implantation process based on the measured resistivity of the substrate. | 11-20-2014 |
| 20150017746 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error. | 01-15-2015 |
| 20150050754 | METHOD FOR POSTDOPING A SEMICONDUCTOR WAFER - A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and adapting the basic doping of the semiconductor wafer by postdoping. The postdoping includes at least one of the following methods: a proton implantation and a subsequent thermal process for producing hydrogen induced donors, and a neutron irradiation. In this case, at least one of the following parameters is dependent on the determined doping concentration of the basic doping: an implantation dose of the proton implantation, a temperature of the thermal process, and an irradiation dose of the neutron irradiation. | 02-19-2015 |
| 20150064811 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE, AND BURN-IN APPARATUS - A method of manufacturing a nitride semiconductor device, the nitride semiconductor device having an input terminal, a drain terminal, a gate terminal, and an output terminal, includes a burn-in step in which the nitride semiconductor device is heated while inputting an RF signal to the input terminal, applying a drain voltage to the drain terminal, and applying a gate voltage to the gate terminal. The burn-in step is continued until the nitride semiconductor device exhibits a decrease in gate current. | 03-05-2015 |
| 20150072446 | METHODS FOR TAILORING ELECTRODE WORK FUNCTION USING INTERFACIAL MODIFIERS FOR USE IN ORGANIC ELECTRONICS - The present invention is directed to methods for tailoring the work function of electrodes in organic electronics using interfacial modifiers comprising functionalized semiconducting polymers and/or small molecules. | 03-12-2015 |
| 20150118765 | DETERMINATION OF GAIN FOR EDDY CURRENT SENSOR - In one aspect, a method of controlling polishing includes receiving a measurement of an initial thickness of a conductive film on a first substrate prior to polishing the first substrate from an in-line or stand-alone monitoring system, polishing one or more substrates in a polishing system, the one or more substrates including the first substrate, during polishing of the one or more substrates, monitoring the one or more substrates with an eddy current monitoring system to generate a first signal, determining a starting value of the first signal for a start of polishing of the first substrate, determining a gain based on the starting value and the measurement of the initial thickness, for at least a portion of the first signal collected during polishing of at least one substrate of the one or more substrates, and calculating a second signal based on the first signal and the gain. | 04-30-2015 |
| 20150118766 | DETERMINATION OF GAIN FOR EDDY CURRENT SENSOR - A method of controlling polishing includes polishing a substrate at a first polishing station, monitoring the substrate with a first eddy current monitoring system to generate a first signal, determining an ending value of the first signal for an end of polishing of the substrate at the first polishing station, determining a first temperature at the first polishing station, polishing the substrate at a second polishing station, monitoring the substrate with a second eddy current monitoring system to generate a second signal, determining a starting value of the second signal for a start of polishing of the substrate at the second polishing station, determining a gain for the second polishing station based on the ending value, the starting value and the first temperature, and calculating a third signal based on the second signal and the gain. | 04-30-2015 |
| 20150318223 | METHOD FOR CONTROLLING A PLASMA CHAMBER - An system and method for controlling a plasma chamber includes operably coupling an RF generator to the plasma chamber, the RF generator providing an RF signal to a chamber input of the plasma chamber; measuring a parameter at the chamber input; determining a rate of change based on the measured parameter; detecting an excessive rate of change condition comprising the rate of change exceeding a reference rate of change; detecting a repetitive change condition comprising a predetermined number of the excessive rate of change conditions in a predetermined time; upon detection of the repetitive change condition, decreasing a power of the RF signal provided to the chamber input. | 11-05-2015 |
| 20150348854 | MULTI-STATION PLASMA REACTOR WITH RF BALANCING - Methods and apparatus for multi-station semiconductor deposition operations with RF power frequency tuning are disclosed. The RF power frequency may be tuned according to a measured impedance of a plasma during the semiconductor deposition operation. In certain implementations of the methods and apparatus, a RF power parameter may be adjusted during or prior to the deposition operation. Certain other implementations of the semiconductor deposition operations may include multiple different deposition processes with corresponding different recipes. The recipes may include different RF power parameters for each respective recipe. The respective recipes may adjust the RF power parameter prior to each deposition process. RF power frequency tuning may be utilized during each deposition process. | 12-03-2015 |
| 20150364533 | METHODS OF MANUFACTURING POLYRESISTORS WITH SELECTED TCR - Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR. | 12-17-2015 |
| 20160005619 | SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTO-CURRENT DETECTION - A method includes performing a chemical-mechanical planarization (CMP) on an article, providing a polishing fluid capable of transferring charges to the article, and detecting a current generated in response to the charges transferred to the article. An apparatus that is capable of performing the method and a system that includes the apparatus are also disclosed. | 01-07-2016 |
| 20160013110 | LESS-SECURE PROCESSORS, INTEGRATED CIRCUITS, WIRELESS COMMUNICATIONS APPARATUS, METHODS AND PROCESSES OF MAKING | 01-14-2016 |
| 20160020157 | POLISHING WITH EDDY CURRENT FEED MEAUREMENT PRIOR TO DEPOSITION OF CONDUCTIVE LAYER - A method of controlling polishing includes storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of a conductive layer over the at least one layer, after deposition of the conductive layer over the at least one layer and during polishing of the conductive layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ eddy current monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements. | 01-21-2016 |
| 20160035634 | IMPROVED ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS PERFORMING THE SAME - The present invention provides an improved ion implantation method and an ion implantation apparatus for performing the improved ion implantation method, belongs to the field of ion implantation technology, which can solve the problem of the poor stability and uniformity of the ion beam of the existing ion implantation apparatus. The improved ion implantation method of the invention comprises steps of: step S | 02-04-2016 |
| 20160049382 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE AND WIRE BONDING APPARATUS FOR PERFORMING THE SAME - In a method of manufacturing a semiconductor package, a first semiconductor chip is adhered to a package substrate. An end portion of a wire is bonded to a first bonding pad of the first semiconductor chip by using a capillary. An operating voltage of the first semiconductor chip is applied to the first bonding pad through the wire to detect a leakage current. A second end portion of the wire is bonded to the first connection pad by using the capillary, according to a result of the detection. | 02-18-2016 |
| 20160065207 | HIGH VOLTAGE CONTROL CIRCUIT FOR AN ELECTRONIC SWITCH - In one embodiment, the invention can be a control circuit for an electronic switch, the control circuit including a first power switch comprising a first optocoupler, the first power switch configured to (a) receive a common input signal and a first voltage, and (b) switchably connect the first voltage to a common output in response to the common input signal; and a second power switch comprising a first transistor coupled to the common output, and a second transistor connected in series between the first transistor and a second voltage source providing a second voltage, the second power switch configured to (a) receive the common input signal and the second voltage, and (b) switchably connect the second voltage to the common output in response to the common input signal. | 03-03-2016 |
| 20160079131 | DEVICE AND METHOD FOR ALIGNMENT OF VERTICALLY STACKED WAFERS AND DIE - A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively. | 03-17-2016 |
| 20160099186 | METHOD FOR POSTDOPING A SEMICONDUCTOR WAFER - A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and adapting the basic doping of the semiconductor wafer by postdoping. The postdoping includes at least one of the following methods: a proton implantation and a subsequent thermal process for producing hydrogen induced donors. In this case, at least one of the following parameters is dependent on the determined doping concentration of the basic doping: an implantation dose of the proton implantation, and a temperature of the thermal process. | 04-07-2016 |
| 20160111261 | System and Method for Detecting a Process Point in Multi-Mode Pulse Processes - A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point. | 04-21-2016 |
| 20160133530 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus includes a processing chamber configured to perform a plasma processing on a sample, a first radio frequency power supply configured to generate a plasma, a sample stage configured to place the sample thereon, a second radio frequency power supply configured to supply a radio frequency power to the sample stage, a mass flow controller configured to supply a gas into the processing chamber, and a control device configured to change the radio frequency power supplied from the first radio frequency power supply or the second radio frequency power supply based on a change of plasma impedance after a first gas is switched to a second gas. | 05-12-2016 |
| 20160167960 | Method for Producing a Microelectromechanical Transducer | 06-16-2016 |
| 20160203958 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD | 07-14-2016 |
| 20160252765 | METHOD FOR CONTROLLING MIS STRUCTURE DESIGN IN TFT AND SYSTEM THEREOF | 09-01-2016 |
| 20170237009 | METHOD OF FABRICATING DISPLAY DEVICE | 08-17-2017 |
| 20190148191 | SYSTEM AND METHOD FOR MONITORING OPERATION CONDITIONS OF SEMICONDUCTOR MANUFACTURING APPARATUS | 05-16-2019 |
