| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 377039000 | Comparing counts | 7 |
| 20110311017 | CLOCK GLITCH DETECTION - A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay. | 12-22-2011 |
| 20110317802 | CLOCK GLITCH DETECTION CIRCUIT - In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment. A comparator determines the difference between the first count and the second count, or determines whether the first count and the second count differ. The synchronous circuit may comprise the first circuit. A second circuit for detecting clock glitches in a clock signal is also provided. The second circuit is intended to be integrated in the synchronous circuit. | 12-29-2011 |
| 20120002779 | STATE DETECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A state detection circuit comprises: a first counter circuit that counts a series of first command signals indicative of start of an operation control; a second counter circuit that counts a series of second command signals indicative of completion of the operation control; a count coincidence detection circuit that detects coincidence between a count in the first counter circuit and a count in the second counter circuit; and a state storing circuit that is set by the series of first command signals and reset when coincidence is detected by the count coincidence detection circuit. The first and second counter circuits each comprise a binary counter. | 01-05-2012 |
| 20120140870 | INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal. | 06-07-2012 |
| 20130077733 | Circuit Configuration And Method For Distributing Pulses Within A Time Interval - A circuit configuration for generating pulses within a time interval on the basis of an input signal includes a counting unit, a comparator unit and a first adder circuit; the time interval being predicted on the basis of at least two defined changes in input signals; the circuit configuration being configured for triggering at the beginning of the time interval by the first adder circuit on the basis of clock pulses, for generating and outputting pulses; for counting a number of generated and output pulses using the counting unit; | 03-28-2013 |
| 20140105350 | METHOD AND APPARATUS TO MONITOR GAIN OF A PROPORTIONAL COUNTER - A method and apparatus in accordance with the present disclosure relate to monitoring gain of a proportional counter. The method includes generating a pulse height spectrum of the proportional counter, defining a first window and a second window within the pulse height spectrum, counting electrical pulses outputted by the proportional counter within the first window of the pulse height spectrum, thereby defining a first window count, counting electrical pulses outputted by the proportional counter within the second window of the pulse height spectrum, thereby defining a second window count, and determining a difference between the first window count and the second window count. | 04-17-2014 |
| 20140270048 | Digital Period Divider - A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter. | 09-18-2014 |
