| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 377047000 |
Pulse multiplication or division
| 40 |
| 377054000 |
Using shift register
| 13 |
| 377039000 |
Comparing counts
| 7 |
| 377028000 |
Identifying or correcting improper counter operation (e.g., error checking, monitoring; preventing or correcting improper counter operation) | 5 |
| 20150358023 | COUNTER - A counter including a state determination unit and a counter reset unit is provided. The state determination unit is for receiving a current count value to calculate a next count value. The counter reset unit compares a reset counter value and a delay cycle value to determine using a first comparator or a second comparator, and compares the reset counter value and the current count value to output a counter reset signal to the state determination unit to reset the current count value, wherein a bit number of the first comparator is smaller than a bit number of the second comparator. | 12-10-2015 |
| 20080247500 | If Counting Method - In order to provide an IF counting method for realizing an IF counter with a smaller circuit configuration, an IF counter comprises a countdown IF counting unit | 10-09-2008 |
| 20090238323 | REAL TIME CLOCK - A real time clock comprises a counter which stores a count value, the count value representing a time signal. The counter may be written, for example by a host processor (not shown), such that the time signal can be set to any desired value. The real time clock comprises a check register that stores a check value. The content of the check register (i.e. the check value) is modified each time a write operation is performed on the counter. For example, the content of the check register can be updated by a control signal each time a write operation is performed on the counter. The check value stored in the check register is used for determining whether a write operation performed on the counter is an authorized write operation or an unauthorized write operation. The check value may be incremented each time a write operation is performed, replaced with a new random number each time a write operation is performed, or a combination of both. | 09-24-2009 |
| 20110293062 | Method and Apparatus for Rapid Synchronization of Shift Register Related Symbol Sequences - A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism. | 12-01-2011 |
| 20140098927 | METHOD AND APPARATUS FOR DETECTING CUT-OFF FREQUENCY OF PULSE SIGNAL - Disclosed is a apparatus and method for detecting a cut-off frequency of a pulse signal, the apparatus including an input processor configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor configured to reset the counter at every predetermined (set) period, and a detector configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period. | 04-10-2014 |
| 377055000 |
Particular input circuit | 4 |
| 20080292044 | Signal Detection Circuit - A signal detection circuit comprising: a differential amplifier to which an output voltage of a detection coil of a magnetic sensor is to be applied; a comparator to output a digital signal being at one logic level in a period between two spike-shaped voltages adjacent to each other in the output voltage of the differential amplifier; and a count circuit to perform a count operation in a period during which the comparator outputs the digital signal of the one logic level, the count circuit including a first counter to count a first clock having a predetermined frequency, a second counter to count a second clock being equal in frequency to and different in phase from the first clock, the second counter having the same number of bits as the number of bits of the first counter, and an adder to add count values of the first and the second counter. | 11-27-2008 |
| 20130142302 | INPUT CIRCUIT IN HIGH SPEED COUNTER MODULE IN PLC - An input circuit in high speed counter module for PLC is provided, the input circuit being configured such that various types of pulse signals are changed to a single type of pulse signal and transmitted to an MPU, whereby the type of input pulse is checked or an operation of checking addition/deduction is omitted to increase an interrupt process speed. | 06-06-2013 |
| 20130156147 | HIGH SPEED COUNTER APPARATUS - Disclosed is a high speed counter apparatus. The high speed counter apparatus includes a first counter configured to perform a count on the lower bits of the final output signal in response to a first clock signal, a second counter configured to perform a count on the upper bits of the final output signal in response to a second clock signal, and a clock signal generator configured to generate the second clock signal from the first clock signal. In accordance with the present invention, power consumption and a bottleneck phenomenon in an upper bit counter can be reduced because a second clock signal for operating the upper bit counter is synchronized with a first clock signal for operating the lower bit counter at a frequency lower than that of the clock signal for operating the lower bit counter. | 06-20-2013 |
| 20160126958 | PLC HIGH SPEED COUNTER AND OPERATING METHOD THEREOF - Disclosed herein are a PLC high speed counter and an operating method thereof. The PLC high speed counter includes: an input circuit configured to convert and output a high-speed pulse train input from an encoder into a CMOS level; a micro processor unit configured to receive the pulse train from the input circuit, generate a count value by counting the pulse train in a linear count manner and calculate a current ring count value based on the count value; and a buffer configured to receive the count value from the micro processor unit and store the same as a current linear count value, wherein, when a current value request is received from an external device, the micro processor unit determines an operation mode and transmits, if the operation mode is a ring counter mode, the current ring count value. | 05-05-2016 |
| 377049000 |
Counter includes circuit for performing an arithmetic function | 4 |
| 20100027735 | RAM BASED IMPLEMENTATION FOR SCALABLE, RELIABLE HIGH SPEED EVENT COUNTERS - There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter. | 02-04-2010 |
| 20110176652 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - Noise in a semiconductor device including a photo sensor is reduced. The semiconductor device includes an analog/digital converter and a photo sensor including a photodiode. The analog/digital converter includes an oscillation circuit and a counter circuit. A first signal output from the photo sensor is input to the oscillation circuit. The oscillation circuit has a function of outputting a second signal obtained by a change in oscillation frequency of the first signal. The counter circuit has a count function by which addition or subtraction is performed by a control signal with the second signal used as a clock signal. The counter circuit performs subtraction during the reset operation of the photo sensor. The counter circuit performs addition during the selection operation of the photo sensor. Thus, the output value of the analog/digital converter can be corrected. | 07-21-2011 |
| 20130089175 | ARITHMETIC COUNTER CIRCUIT, CONFIGURATION AND APPLICATION FOR HIGH PERFORMANCE CMOS IMAGE SENSORS - An arithmetic counter circuit for high performance CMOS image sensors includes a plurality of flip-flops of a plurality of counter stages and a plurality of multiplexers of the plurality of counter stages being coupled to the plurality of flip-flops. Each of the plurality of multiplexers coupled to receive control signals including at least one of a toggle signal, a keep signal, a shift enable signal, or a mode signal. The control signals select the output of each of the plurality of multiplexers. Each of the plurality of flip-flops is coupled to be in one of a toggle state, a keep state, a reset state or a set state based on inputs received from the plurality of multiplexers. Other embodiments are described. | 04-11-2013 |
| 20130170605 | RAM Based Implementation for Scalable, Reliable High Speed Event Counters - There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter. | 07-04-2013 |
| 377051000 |
Including structure for detecting or indicating overflow condition | 4 |
| 20090086881 | Counter with overflow prevention capability - A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value. | 04-02-2009 |
| 20090154638 | Method and Apparatus for Digital I/O Expander Chip with Multi-Function Timer Cells - A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. | 06-18-2009 |
| 20130223583 | DIGITAL COUNTER AND METHOD FOR MEASURING A PERIOD OF TIME - A method for measuring a period of time between a first event and a second event via a hardware counter | 08-29-2013 |
| 20160065219 | DYNAMIC PRESCALING FOR PERFORMANCE COUNTERS - A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate. | 03-03-2016 |
| 377052000 |
With programmable counter (i.e., with variable base) | 3 |
| 20100046694 | COUNTER CIRCUIT AND METHOD OF OPERATING THE SAME - A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals. | 02-25-2010 |
| 20100080336 | CIRCUIT DEVICE TO GENERATE A HIGH PRECISION CONTROL SIGNAL - In an embodiment, a circuit device includes a first counter responsive to a clock signal and to a first control word having a first precision. The counter produces a first control signal related to the first control word at a first output. The circuit device farther includes a second counter responsive to the clock signal and to a second control word having the first precision. The second counter produces a second control signal related to the second control word at a second output. The circuit device also includes a filtering circuit responsive to the first output and the second output to receive the first and second control words. The filtering circuit is adapted to produce an output control signal related to the first and second control words, where the output control signal has a second precision that is greater than the first precision. | 04-01-2010 |
| 20140270049 | FREQUENCY SCALING COUNTER - A counter is provided, where, as the number of events that occur increases, the frequency in which the events are counted is scaled. | 09-18-2014 |
| 377042000 |
Converting input or output signal from or to an analogue signal | 3 |
| 20090060118 | Method of operating ripple counter, image sensor having ripple counter, method of operating image sensor, and analog-to-digital converter of image sensor - An example embodiment of an image sensor may include a controller and a plurality of up/down ripple counters. The controller may generate a first control signal and a second control signal. Each of the up/down ripple counters may perform a stop operation or a count operation in response to a corresponding one of a plurality of operation control signals generated based on at least in part on the first control signal. The count operation may be an up-count operation or a down-count operation based on the second control signal. The image sensor may also include a plurality of memory chains. Each of the memory chains may receive a count value output from the up/down counters and may shift the received count value in response to a third control signal and a fourth control signal output from the controller. | 03-05-2009 |
| 20130243147 | IMAGE SENSOR USING OFFSET CODE FOR COUNTING - An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n-1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n-1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code. | 09-19-2013 |
| 20130343506 | COUNTER, COUNTING METHOD, AD CONVERTER, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE - A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit. | 12-26-2013 |
| 377044000 |
Counter controlled counter | 3 |
| 20120121060 | NON-VOLATILE MEMORY COUNTER - A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts. | 05-17-2012 |
| 20130114782 | DISPLAY PANEL DRIVE DEVICE - A display panel drive device includes: a ring counter circuit that includes a first ring counter having a plurality of flipflops connected in cascade, configured to operate in synchronization with a first clock signal with a first-stage one of the plurality of flipflops being set by an initial signal, and outputs signals using outputs of the plurality of flipflops; a shift register having a plurality of flipflops connected in cascade, configured to operate in synchronization with a second clock signal lower in frequency than the first clock signal with a first-stage one of the plurality of flipflops being set by the initial signal; and an output section configured to perform a logical operation between one of outputs of the ring counter circuit and one of outputs of the shift register, to generate a scanning line drive signal for a display panel. | 05-09-2013 |
| 20140086378 | DYNAMIC PRESCALING COUNTERS - A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register. | 03-27-2014 |
| 377033000 |
Using particular code or particular counting sequence | 3 |
| 20150023463 | MODULAR GRAY CODE COUNTER - A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state. | 01-22-2015 |
| 20090285351 | COUNTER OF SEMICONDUCTOR DEVICE - The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. | 11-19-2009 |
| 20130142301 | FLOATING-POINT EVENT COUNTERS WITH AUTOMATIC PRESCALING - Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts. | 06-06-2013 |
| 377037000 |
Sequential readout of plural counters or sequential sampling of inputs to a counter | 1 |
| 20140093026 | NON-VOLATILE MEMORY COUNTER - A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially. | 04-03-2014 |
| 377046000 |
Including ring counter | 1 |
| 20130077734 | Initializing A Ring Counter - A technique includes driving a node of a stage of a ring counter to a predetermined signal state; and clocking the ring counter to cause the signal state to propagate to at least one additional stage of the ring counter to initialize the ring counter with a reset sequence. | 03-28-2013 |
| 377053000 |
With photoelectric sensor | 1 |
| 20150124926 | COUNTER CIRCUIT AND IMAGE SENSOR INCLUDING THE SAME - An integrated circuit counter includes a cascaded chain of bit counters, which are collectively configured to count a number of first edges of a counter input signal received at an input thereof and output the count as a counter output signal. The cascaded chain includes at least two bit counters, which are: (i) configured to support both counter and buffer modes of operation, and (ii) responsive to respective bypass control bit signals having values that specify whether a corresponding one of the at least two bit counters is disposed in the counter or buffer mode of operation. | 05-07-2015 |
