Class / Patent application number | Description | Number of patent applications / Date published |
365228000 | Data preservation | 71 |
20080316850 | System for retaining state data of an integrated circuit - According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles. | 12-25-2008 |
20090027991 | Information processing apparatus, memory unit erroneous write preventing method, and information processing system - To make it possible to reliably halt writing processing while restraining erroneous writing to the memory unit, present apparatus has a memory unit to which data is written for each write request; a voltage converting unit which converts a first power source voltage into a first operable voltage with which a write request issuing unit is operable, and supplies the first operable voltage to the write request issuing unit; a voltage monitoring unit, which outputs an issuance restraining signal which restrains issuance of the write request, when the first power source voltage becomes lower than a reference voltage; and an issuance restrain controlling unit which receives the issuance restrain signal, and then after completion of writing for each of the write request to write memory unit, which restrains the issuance of the write request by the write request issuance unit. | 01-29-2009 |
20090034354 | METHOD, SYSTEM, AND APPARATUS FOR VOLTAGE SENSING AND REPORTING - A method, apparatus and system are disclosed for sensing and reporting voltage levels in a semiconductor device. One such voltage sensor and reporting device is configured to sense and compare a reference voltage and an operating voltage. In one or more embodiments we voltage sensor is also configured to generate an alarm signal if the difference between the operating voltage and the reference voltage indicates the operating voltage is outside of a normal operating range. | 02-05-2009 |
20090046532 | Supply Voltage for Memory Device - A device is provided including a memory cell, a first supply voltage generator, passively coupled to the memory cell, to provide the memory cell with a first supply voltage, and a second supply voltage generator, coupled to the memory cell, to provide the memory cell with a second supply voltage. | 02-19-2009 |
20090067275 | PROJECTION DISPLAY APPARATUS - A projector | 03-12-2009 |
20090073795 | DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR - A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. | 03-19-2009 |
20090109786 | DATA MANAGEMENT METHOD FOR NON-VOLATILE MEMORY DEVICE - A method of operating a non-volatile data storage device includes determining the type of the previous power off event when the non-volatile data storage device is rebooted; and selecting and performing a reboot sequence based upon the determined type of the power off event. Determining the type of the previous power off event may be performed by analyzing one or more metadata groups stored in the non-volatile data storage device. During normal operation of the data storage device a preamble (indicating that an operation of a data storage device started) and a postamble (indicating that an operation of the data storage device ended) are written in each group of metadata. If the power off event is a sudden (abnormal) power off event during a write operation, the postamble is not written, and its absence indicates that the power off event was a sudden (abnormal) power off event. | 04-30-2009 |
20090147613 | DEVICE FOR PROTECTING SRAM DATA - A device for protecting data stored in a static random access memory (SRAM) is provided. More particularly, a device for protecting SRAM data including an SRAM data erasing circuit, which erases memory stored in an SRAM at once when illegal separation from a system is detected. The device for protecting SRAM data includes: a power switching circuit for outputting electrical power supplied from an external power supply or a back-up battery power supply depending on whether the external power supply is supplying the electrical power or not; and an SRAM data erasing circuit for supplying the electrical power output from the power switching circuit to a power input terminal of a SRAM or grounding the power input terminal of the SRAM, in response to a connecter connection signal. The device can prevent illegal leakage of SRAM data by erasing the data stored in the SRAM when the SRAM is illegally separated from a system according to the switch setting of the SRAM data erasing circuit. | 06-11-2009 |
20090190428 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a semiconductor device equipped with a nonvolatile memory, using a simple configuration, a write operation and the like are reliably made feasible even when stability of power supply from an external component is inhibited. The semiconductor device includes a nonvolatile memory core including a nonvolatile memory and a switch for switching a power supply mode for supplying power to the nonvolatile memory core between a first mode in which power is supplied from an external power supply and a second mode in which power is supplied from an accumulation device used as a back-up power supply. The nonvolatile memory core outputs a status signal indicating an operation state of the nonvolatile memory core, and the switch switches the power supply mode according to an operation state of the nonvolatile memory core that the status signal indicates. | 07-30-2009 |
20100008174 | Adaptive training and adjustment to changing capacitor values based upon age and usage behavior - An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop. | 01-14-2010 |
20100202236 | RAPID SAFEGUARDING OF NVS DATA DURING POWER LOSS EVENT - A method, system, and computer program product for safeguarding nonvolatile storage (NVS) data by a processor in communication with a memory device following a power loss event is provided. A first portion of the NVS data is encrypted using a first buffer module. Subsequently the first portion of the NVS data is transferred to at least one shared storage device, while a second portion of the NVS data is simultaneously encrypted using a second buffer module. The second portion of the NVS data is subsequently transferred to the at least one shared storage device. | 08-12-2010 |
20100202237 | FLASH BACKED DRAM MODULE WITH A SELECTABLE NUMBER OF FLASH CHIPS - A memory device for use with a primary power source and a backup power source, includes: volatile memory; an interface for connecting to a backup power source; a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip; a plurality of interfaces, each of which is for communicating through a different corresponding one of the plurality of ports with any non-volatile memory connected to that port; a controller that is programmed to activate a selectable set of the plurality of interfaces depending on which ports are to receive non-volatile memory chips, wherein said controller is also programmed to react to a loss of power from the primary power source by moving data from the volatile memory through the selected interfaces to whatever non-volatile memory is connected to the selectable set of interfaces. | 08-12-2010 |
20100202238 | FLASH BACKED DRAM MODULE INCLUDING LOGIC FOR ISOLATING THE DRAM - A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory. | 08-12-2010 |
20100214863 | MEMORY POWER GATING CIRCUIT AND METHODS - A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage. | 08-26-2010 |
20100309743 | POWER DETECTING CIRCUIT, PORTABLE DEVICE AND METHOD FOR PREVENTING DATA LOSS | 12-09-2010 |
20110080798 | Digital Retention Voltage Generation - A first embodiment of the present invention is a system for generating a voltage comprising a comparator operable to compare an operation voltage to a reference voltage, control logic operable to selectively output as a control signal an incremented signal or a decremented signal based on a comparison of the operation voltage to the reference voltage by the comparator, and a device module operable to increase or decrease the operation voltage based on the control signal. | 04-07-2011 |
20110141839 | DEVICE AND METHOD FOR PROTECTING DATA IN NON-VOLATILE MEMORY - Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device ( | 06-16-2011 |
20120063255 | STORAGE DEVICE, ELECTRONIC DEVICE, AND STORAGE DEVICE CONTROL METHOD - According to one embodiment, a storage device includes a volatile memory, an auxiliary power source, a nonvolatile memory, a write module, and an inhibition module. The volatile memory stores user data. The auxiliary power source supplies power to the volatile memory when power from a main power source is cut off. The nonvolatile memory is written with the user data, write incomplete information indicating the user data, and power off information indicating that power from the main power source is cut off. While supplied with power from the auxiliary power source when power from the main power source is cut off, the write module writes the write incomplete information, the user data, and the power off information to the nonvolatile memory. The inhibition module inhibits reading of the user data if the power off information is not written in the nonvolatile memory when the volatile memory is supplied with power. | 03-15-2012 |
20120140585 | Retention voltage generation - An integrated circuit and method are provided, the integrated circuit comprising retention voltage generation circuitry which receives a supply voltage from a supply voltage node and provides a retention voltage at a retention voltage node. Functional circuitry is connected between the retention voltage node and a reference voltage node, the functional circuitry being held in a data retention state when at least a minimum voltage is provided between the retention voltage node and the reference voltage node. Each of the functional circuitry and the retention voltage generation circuitry comprise at least one p-type threshold device and at least one n-type threshold device, the p-type threshold devices and the n-type threshold devices respectively having a characteristic threshold voltage and the at least one p-type threshold device and the at least one n-type threshold device in the retention voltage generation circuitry being connected in parallel between the supply voltage node and the retention voltage node. A variation in the characteristic threshold voltage of either the at least one p-type threshold device or the at least one n-type threshold device in the functional circuitry is accompanied by a corresponding variation in the characteristic threshold voltage of either the at least one p-type threshold device or the at least one n-type threshold device respectively in the retention voltage generation circuitry, thus maintaining at least the minimum voltage between the retention voltage node and the reference voltage node and thus keeping the functional circuitry in the data retention state. | 06-07-2012 |
20130039141 | APPARATUS, SYSTEM, AND METHOD FOR POWER REDUCTION MANAGEMENT IN A STORAGE DEVICE - An apparatus, system, and method are disclosed for power reduction management. The method includes determining that a power source has failed to supply electric power above a predefined threshold. The method includes terminating one or more non-essential in-process operations on a nonvolatile memory device during a power hold-up time. The method includes executing one or more essential in-process operations on the nonvolatile memory device within the power hold-up time. | 02-14-2013 |
20130070551 | Percolation Tamper Protection Circuit for Electronic Devices - An integrated circuit employing a percolation tamper protection device includes a circuit housing with a die disposed in circuit housing. The die includes a volatile memory. A percolation tamper protection device that is connected to the volatile memory and also disposed in the circuit housing. The percolation tamper protection device includes a percolation gate which is biased in a conductive state. The percolation gate includes a first terminal that is connected to the volatile memory and a second terminal configured to be connected to a power supply. The percolation gate has a conductivity that varies proportional to pressure. | 03-21-2013 |
20130170311 | Power Supply, Associated Management Unit and Method - The present invention discloses a power supply. The power supply may comprise an input power terminal, a capacitor module, a first converter module and a second converter module. The first converter module may have a first terminal and a second terminal, wherein the first terminal is coupled to the input power terminal and the second terminal is coupled to the capacitor module. The second converter module may comprise an input and an output, wherein the input of the second converter module is coupled to the input power terminal, and the output of the second converter module is configured to supply a load. | 07-04-2013 |
20130188437 | HARDWARE WRITE-PROTECTION - A system for providing write-protection functionality to a memory device includes: a memory device including configurable registers controlling write and erase operations in the memory device; a system interface; a filter logic device in electrical communication with the memory device and further in communication with the system interface; and a power on reset circuit in communication with the system interface and the filter logic device, wherein the power on reset circuit asserts a reset signal to the system interface on startup of the system, further wherein, while the reset signal is asserted to the system interface, the filter logic device modifies the configurable registers to prevent all further write and erase operations to the memory device and then the power on reset circuit de-asserts the reset signal to the system interface enabling communication between the system interface and the memory device. | 07-25-2013 |
20130223175 | VOLTAGE GENERATORS ADAPTIVE TO LOW EXTERNAL POWER SUPPLY VOLTAGE - Voltage generators may generate a level of a high target voltage with respect to a low external power supply voltage. A reference voltage generator includes a clamp regulator which is driven by a first power supply voltage supplied from an external source and receives a first voltage to generate a clamp voltage, and a level amplifier which is driven by a second power supply voltage that is higher than the first power supply voltage and receives the clamp voltage to generate a reference voltage. The clamp voltage may be set to have a voltage level which results in a successful restore operation with respect to a memory cell array in a dynamic random access memory (DRAM). | 08-29-2013 |
20130235690 | Device and Method for Protecting Data in Non-Volatile Memory - Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device that is used for protecting non-volatile memory data when a power is shut down in a system, may include a signal delay unit to delay a drop in voltage of an input/output line, a power shutdown sensor to sense power shutdown of a system, and a controller to control the signal delay unit in response to whether the system is shut down. | 09-12-2013 |
20130265841 | Immunity Against Temporary and Short Power Drops in Non-Volatile Memory - A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations. | 10-10-2013 |
20130301373 | Memory Chip Power Management - A power supply voltage for a memory chip is compared with a plurality of threshold voltages that correspond to voltages below which classes of memory operations can no longer be guaranteed. When the power supply voltage drops below a threshold voltage, appropriate action is taken, which may include generating an indicator such as a flag, proceeding with the operations in some modified manner, or disabling operations that are no longer guaranteed, either permanently or until power is restored, or until some other appropriate time. | 11-14-2013 |
20130315021 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A semiconductor device capable of simply performing power gating and a driving method thereof are provided. Power gating is started passively (automatically in the case of satisfying predetermined conditions). Specifically, the semiconductor device includes a transistor for selecting whether a power source voltage is supplied or not to a functional circuit. The power gating is started by turning off the transistor in the case where a voltage between a source and a drain is less than or equal to a predetermined voltage. Therefore, complicated operation is not needed at the time of starting power gating. Specifically, it is possible to start power gating without a process for predicting the timing at which an arithmetic operation performed in the functional circuit is terminated. As a result, it is possible to start power gating easily. | 11-28-2013 |
20130336081 | STATE-MONITORING MEMORY ELEMENT - Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage. | 12-19-2013 |
20140016426 | SYSTEMS AND METHODS FOR PREVENTING DATA REMANENCE IN MEMORY - A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory. The memory includes a plurality of bits configured to electronically store data. | 01-16-2014 |
20140064011 | System and Method for Providing Voltage Supply Protection in a Memory Device - The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element. | 03-06-2014 |
20140204696 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor. | 07-24-2014 |
20140247682 | Method and Apparatus to Boost Mass Memory Performance Given Power Supply Availability - Reliability of a power supply is assessed, such as for example considering one or more of the following: whether a host device is experiencing fast acceleration; whether a portable power supply has sufficient energy to meet current needs; whether a battery or removable memory cover is in place; and whether a software failure within the host device is imminent. In dependence on the assessed reliability, there is a selection made between a first mode and a second mode for operating a mass memory. The first mode comprises better data retention than the second mode for the case that the power supply is interrupted, and the second mode comprises faster data transfer than the first mode for the case that the power supply is not interrupted. In one embodiment the first and second mode buffers write data utilizing respective non-volatile (flash) and volatile (DRAM) memory. | 09-04-2014 |
20140376322 | RETENTION OF DATA DURING STAND-BY MODE - An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is configured to selectively alter the voltage provided at each said storage array node during stand-by mode. The storage device may further comprise a storage array operatively coupled to said Rail to Rail voltage adjustor and a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during stand-by mode. | 12-25-2014 |
20150043296 | SERIAL ADVANCED TECHNOLOGY ATTACHMENT DUAL IN-LINE MEMORY MODULE DEVICE - When a measured current of a resistor is less than a preset current value after a device is inserted into a memory slot, a control chip and a storage chip does not receive voltages. When the measured current is not less than the preset current value and a count time reaches a preset time value, the control chip and the storage chip receive voltages, to read or write data. When measured current of the resistor is not less than the preset current value after the device is removed from the memory slot, the control chip and the storage chip receive voltages, to backup data. When the measured current is less than the preset current value and the count time reaches the preset time value, the control chip and the storage chip do not receive voltages. | 02-12-2015 |
20150357005 | Auxiliary Power Supply Devices and Nonvolatile Memory Systems Including the Same - An auxiliary power supply device can include a first power storage unit, a first charging circuit to receive input power and charge the first power storage unit, a second power storage unit having lower power supply speed than the first power storage unit and longer power supply time than the first power storage unit, a second charge circuit to receive input power and charge the second power storage unit, and a switching unit to supply the stored power of the first power storage unit to external devices for a predetermined time when a sudden power-off occurs and supply stored power of the second power storage unit to the external devices after the predetermined time elapses. | 12-10-2015 |
20160141004 | POWER MANAGEMENT IN AN ELECTRONIC SYSTEM THROUGH REDUCING ENERGY USAGE OF A BATTERY AND/OR CONTROLLING AN OUTPUT POWER OF AN AMPLIFIER THEREOF - A method includes automatically charging a capacitor coupled to a battery configured to power a memory through a charge switch that is closed whenever a voltage of the battery exceeds a recovery trip voltage or exceeds a shutdown trip voltage but is less than the recovery trip voltage and opened whenever the voltage of the battery drops below the shutdown trip voltage such that a minimum voltage of the shutdown trip voltage is maintained on the battery, thereby enabling the memory to retain information therein. The method also includes rendering a stored energy of the capacitor available to all circuitry coupled to the battery following the charging thereof through coupling the capacitor in parallel with the battery based on closure of a discharge switch following the charging of the capacitor. | 05-19-2016 |
20160141006 | POWER MANAGEMENT IN AN ELECTRONIC SYSTEM THROUGH REDUCING ENERGY USAGE OF A BATTERY AND/OR CONTROLLING AN OUTPUT POWER OF AN AMPLIFIER THEREOF - A method includes configuring a battery and a voltage regulator configured to regulate an output voltage of the battery to supply power to a memory of an electronic circuit also comprising non-memory circuitry. The method also includes switching the supply of power between the battery and the voltage regulator such that: the memory is powered from the battery when the non-memory circuitry is inactive, the memory is powered from a combination of voltage from the battery and the voltage regulator when the memory is about to communicate with the non-memory circuitry during a transition of the non-memory circuitry into an active state thereof, and the memory and the non-memory circuitry are powered from the voltage regulator during the active state of the non-memory circuitry. Thus, minimal current is drawn from the battery while a state of the memory of the electronic circuit is preserved. | 05-19-2016 |
365229000 | Standby power | 33 |
20080198679 | SRAM WITH SWITCHABLE POWER SUPPLY SETS OF VOLTAGES - A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself. | 08-21-2008 |
20080239859 | ACCESS DEVICE - P-type multi gate field effect transistor access devices are adapted to be coupled to a memory cell to provide access to the memory cell. A method is described that uses a power switch to switch off address decoding circuitry allowing word lines to float toward a high supply voltage, turning off the p-type multi gate field effect transistor access devices. | 10-02-2008 |
20090003116 | CONTROL CIRCUIT FOR REFRESHING VOLTAGES IN A NON-VOLATILE MEMORY DURING A STANDBY MODE AND A METHOD THEREOF - Disclosed is a method for refreshing voltages in a non volatile memory during a standby mode. The method comprises generating a first node voltage and a second node voltage through a resistance ladder, storing the voltages in a pair of capacitors, comparing the voltages by a comparator, generating an output electrical signal by the comparator upon comparing the voltages, latching the output electrical signal by a flip flop, generating an electrical refresh pulse by a refresh pulse generator upon receiving the output electrical signal from the flip flop, the electrical refresh pulse being supplied to a refresh node of a plurality of refresh nodes in the non volatile memory and generating an electrical sample pulse by a sample pulse generator, the electrical sample pulse along with the electrical refresh pulse setting the flip flop, thereby causing the flip flop to latch a new output electrical signal. | 01-01-2009 |
20090040859 | Backup for Volatile State Retention in the Absence of Primary Circuit Power - A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power of any of these circuits. An example of such a volatile circuit is a memory circuit having volatile memory cells such as employed in dynamic memory core, in particular, a random access memory (RAM) in CMOS circuitry. | 02-12-2009 |
20100008175 | BATTERY-LESS CACHE MEMORY MODULE WITH INTEGRATED BACKUP - A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level. | 01-14-2010 |
20100142307 | TEMPERATURE PROTECTION FOR POWER CAPACITOR - An apparatus includes a capacitor and logic to adjust an operating temperature of the capacitor according to a charge on the capacitor, and/or to adjust a charge of the capacitor according to the operating temperature of the capacitor to improve the useful life of the capacitor and increase its reliability. | 06-10-2010 |
20100202239 | STAGED-BACKUP FLASH BACKED DRAM MODULE - A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state. | 08-12-2010 |
20100202240 | STATE OF HEALTH MONITORED FLASH BACKED DRAM MODULE - A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile memory; and a backup power supply providing temporary power to the controller and the volatile memory upon the loss of power of the primary power source, including: a capacitor bank with an output terminal; a connection to a voltage source that charges the capacitor bank to a normal operating voltage; and a state-of-health monitor that is programmed to generate a failure signal based on a voltage at the output terminal of the capacitor bank. | 08-12-2010 |
20100226194 | POWER-FAILURE PROTECTION CIRCUIT FOR NON-VOLATILE SEMICONDUCTOR STORAGE DEVICES AND METHOD FOR PREVENTING UNEXPECTED POWER-FAILURE USING THE SAME - A power failure protection circuit ( | 09-09-2010 |
20100238753 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage. | 09-23-2010 |
20100238754 | CLOCK AND POWER FAULT DETECTION FOR MEMORY MODULES - A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module. | 09-23-2010 |
20100265785 | Protection Circuit and Power Supply System for Flash Memory - A protection circuit, applied to a flash memory including a power supply pin, includes a capacitor and a switch. A power supply provides a reference voltage. The capacitor is electrically connected to the power supply pin and a ground point. The switch is electrically connected between the power supply pin and the power supply. When the reference voltage is higher than a threshold voltage, the switch is turned on, such that the reference voltage is inputted into the power pin via the switch. When the reference voltage is lower than the threshold voltage, the switch is turned off. | 10-21-2010 |
20100284235 | Method and Control Unit for Operating a Volatile Memory, Circuit Arrangement, and Trip Recorder - A method for operating a volatile memory supplied with a supply signal arranged either as a first supply signal of a first supply signal source or a second supply signal of a second supply signal source. If an available first supply signal is present it is used otherwise the second supply signal is used. The supply signal is supplied, based on a switch position of a switching element to the volatile memory. During a detected interrupted first supply signal, the switch position of the switching element is for a predetermined period of time such that the supply signal is supplied to the volatile memory. After expiry of the predetermined period of time, the switch position of the switching element is predetermined such that the volatile memory is decoupled electrically from the supply signal. | 11-11-2010 |
20100329064 | SYSTEMS, METHODS AND DEVICES FOR MONITORING CAPACITIVE ELEMENTS IN DEVICES STORING SENSITIVE DATA - Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data storage device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the memory control circuit with access to a set of common data. A power-reservoir circuit includes two or more capacitor cells that respectively hold charge to provide operating power to the data storage device to permit transfer of the data from the volatile memory circuit to the solid-state memory circuit in the event of a power loss. A detection circuit is connected to a center tap between the capacitor cells and uses the tap to detect characteristics of the cells relative to one another, and to provide an output that can be used to characterize the cells' electrical characteristics relative to one another. | 12-30-2010 |
20100329065 | SYSTEMS, METHODS AND DEVICES FOR POWER CONTROL IN MASS STORAGE DEVICES - Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage circuit is powered using a variable voltage controlled to limit the current draw from a power supply, to charge the energy storage circuit for providing backup power to a solid state drive (SSD) type of data storage arrangement. Certain applications involve controlling the power draw from the power supply, in response to feedback and/or power drawn from other circuits, as may be applicable to an initial startup of the energy storage circuit and/or the initial startup of a larger system in which the energy storage circuit is employed. | 12-30-2010 |
20110058440 | APPARATUS, SYSTEM, AND METHOD FOR POWER REDUCTION MANAGEMENT IN A STORAGE DEVICE - An apparatus, system, and method are disclosed for power loss management in a nonvolatile data storage device. A monitor module initiates a power loss mode in the nonvolatile data storage device in response to a primary power source failing to supply electric power above a predefined threshold to the nonvolatile data storage device. A secondary power source supplies electric power to the nonvolatile data storage device for at least a power hold-up time during the power loss mode. A power loss module adjusts execution of in-process operations on the nonvolatile data storage device during the power loss mode so that essential in-process operations execute within the power hold-up time. | 03-10-2011 |
20110069575 | ELECTRONIC DEVICE AND METHOD FOR PREVENTING DATA LOSS IN MEMORY STORAGE DEVICE AND ELECTRONIC DEVICE ASSEMBLY - An electronic device includes a memory storage device, a storing unit, and a voltage increasing unit. The storing unit is used for receiving the supply voltage to store energy and releasing energy to generate an standby voltage when the power supply stops providing the supply voltage. The voltage increasing unit is used for receiving the standby voltage, increasing the standby voltage, and providing the increased standby voltage to the memory storage device for preventing data loss in the memory storage device. A related method for preventing data loss in a memory storage device and an electronic device assembly are also provided. | 03-24-2011 |
20120147688 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage. | 06-14-2012 |
20120224445 | Apparatus and method to measure energy capacity of a backup power supply without compromising power delivery - A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's stored potential is created above an upper predetermined operating potential of the capacitor. Measurements of a capacitor's output voltage are obtained during the transient elevation of the capacitor's stored potential. A capacitance of the capacitor is determined from the measurements. | 09-06-2012 |
20120224446 | Capacitor Charge Balance System - “A circuit includes a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, the series arrangement configured such that each capacitor stage receives charge current via a common charging terminal. A controller is configured to separately measure a stored potential of each capacitor stage in the series arrangement. The circuit includes logic to selectively remove a controlled amount of charge from each capacitor stage individually (discharge logic), and logic to operate the discharge logic to maintain each capacitor stage in the series arrangement at a substantially equal stored potential (balancing logic).” | 09-06-2012 |
20130128685 | MEMORY MANAGEMENT SYSTEM WITH POWER SOURCE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level. | 05-23-2013 |
20130142001 | BATTERY-LESS CACHE MEMORY MODULE WITH INTEGRATED BACKUP - A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level. | 06-06-2013 |
20130148457 | FAST STARTUP HYBRID MEMORY MODULE - A memory device is provided comprising: a volatile memory device, a non-volatile memory device, a memory control circuit volatile memory controller coupled to the volatile memory device and non-volatile memory device, and a backup power source. The backup power source may be arranged to temporarily power the volatile memory devices and the memory control circuit upon a loss of power from the external power source. Additionally, a switch may serve to selectively couple: (a) a host memory bus to either the volatile memory device or non-volatile memory device; and (b) the volatile memory device to the non-volatile memory device. Upon reestablishment of power by an external power source from a power loss event, the memory control circuit is configured to restore data from the non-volatile memory device to the volatile memory device prior to a host system, to which the memory device is coupled, completes boot-up. | 06-13-2013 |
20130155800 | Secondary Memory Units and Systems Including the Same - A secondary memory unit and a system including the same, the secondary memory unit including: a first substrate on which one or more non-volatile memory units to which power is supplied from an external device, are mounted; a second substrate on which one or more energy storage and supply mediums are mounted; and an energy transfer medium for electrically connecting the first substrate and the second substrate, wherein, when power from the external device to the one or more non-volatile memory units is cut off, the one or more energy storage and supply mediums are configured to supply power to the one or more non-volatile memory units. The secondary memory unit and the system including the same have high reliability and improved stability, and their product development and maintenance are convenient. | 06-20-2013 |
20130170312 | CAPACITOR POWER SOURCE TAMPER PROTECTION AND RELIABILITY TEST - A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”). | 07-04-2013 |
20140133257 | BACK-UP POWER MANAGEMENT FOR EFFICIENT BATTERY USAGE - Battery backup devices and methods of performing a backup operation using the same are provided. A battery backup device can include a partial battery power controller configured to shut off power to components to be backed up one by one as data backup is completed on each device. The battery backup devices and methods provided can efficiently utilize battery power such that power consumption and charging time can be reduced. | 05-15-2014 |
20140133258 | SECONDARY MEMORY DEVICE AND ELECTRONIC SYSTEM EMPLOYING THE SAME - A secondary memory device includes a substrate configured to receive power from an external power source, at least one of non-volatile memory devices mounted on the substrate, a control device mounted on the substrate to control the non-volatile memory devices, and a secondary battery electrically connected to the substrate and configured to supply second power to the substrate when a power supply from the external power source is abnormally stopped. | 05-15-2014 |
20150016206 | APPARATUS AND METHOD TO MEASURE ENERGY CAPACITY OF A BACKUP POWER SUPPLY WITHOUT COMPROMISING POWER DELIVERY - A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's stored potential is created above an upper predetermined operating potential of the capacitor. Measurements of a capacitor's output voltage are obtained during the transient elevation of the capacitor's stored potential. A capacitance of the capacitor is determined from the measurements. | 01-15-2015 |
20150016207 | Systems and Methods for Reducing Standby Power in Floating Body Memory Devices - Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. | 01-15-2015 |
20150138906 | SYSTEMS AND METHODS FOR NON-VOLATILE MEMORY - A self powered memory system is disclosed. The system includes a volatile supply component, a battery component, a switch component, and a volatile memory component. The volatile supply component is configured to provide a time varying supply. The battery component is configured to generate a non-volatile supply. The switch component is configured to generate a persistent supply from the time varying supply and the non-volatile supply. The volatile memory component is configured to maintain data by using the persistent supply. | 05-21-2015 |
20150318027 | Continuous Capacitor Health Monitoring and Power Supply System - An electronic device includes a subsystem, a plurality of energy storage elements coupled to the subsystem through one or more switches, and a charging and monitoring apparatus for concurrently charging the plurality of energy storage elements and monitoring operability of the energy storage elements. A first subset of the energy storage elements is coupled to a first node and a second subset of the energy storage elements is coupled to a second node of a bridge circuit. A power supply provides a DC charging voltage and an AC test voltage to both the first and second subsets of the energy storage elements. A monitoring circuit produces a predefined fault signal if a predefined electrical characteristic of the first subset of the energy storage elements differs from a same predefined electrical characteristic of the second subset of the energy storage elements by more than a predefined amount. | 11-05-2015 |
20160148674 | Systems and Methods for Reducing Standby Power in Floating Body Memory Devices - Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. | 05-26-2016 |
20160155488 | METHOD OF OPERATING A VOLTAGE REGULATOR | 06-02-2016 |