| Entries |
| Document | Title | Date |
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| 20080198677 | Internal voltage detection circuit and internal voltage generation device using the same - An internal voltage detection circuit and an internal voltage generation device using the same are disclosed. The internal voltage detection circuit includes a first detect signal generator for generating a first detect signal to detect a level of an internal voltage corresponding to an operating temperature of a memory cell, a second detect signal generator for generating a second detect signal to detect a specific level of the internal voltage corresponding to a preset temperature, and a detect signal clamp unit for comparing a level of the first detect signal and a level of the second detect signal with each other and clamping the first detect signal according to a result of the comparison. | 08-21-2008 |
| 20080198678 | PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES - A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements. | 08-21-2008 |
| 20080205184 | SEMICONDUCTOR MEMORY DEVICE - This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage. | 08-28-2008 |
| 20080212389 | SDRAM with Reset Function - A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes a low voltage MOS input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRS | 09-04-2008 |
| 20080212390 | Bulk bias voltage level detector in semiconductor memory device - There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage. | 09-04-2008 |
| 20080219076 | SEMICONDUCTOR CIRCUITS - Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection signal, a frequency detector detects frequency of a main clock to generate a frequency detection signal, and a signal adjustment unit receives a first signal and selects one of a plurality of different adjusting parameters to adjust the first signal according to the voltage detection signal and the frequency detection signal. | 09-11-2008 |
| 20080219077 | INTERNAL VOLTAGE GENERATION CIRCUIT AND METHOD FOR SEMICONDUCTOR DEVICE - An internal voltage generation circuit for a semiconductor device and method therefor includes a voltage generator configured to generate voltages with different levels by using an external voltage. A code storing unit is configured to store a selection code to select an internal voltage out of the plurality of voltages. A decoding unit selects the internal voltage from among the plurality of voltages in response to the selection code in a normal mode, and selects the internal voltage out of the plurality of voltages in response to a test selection code set in a test mode. The interval voltage selected in the normal mode is used as an initial value that is a reference of the selection in the test mode. | 09-11-2008 |
| 20080219078 | MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME - One aspect in accordance with the present invention provides a memory system receiving a power supply from a host device. The memory system includes a non-volatile semiconductor memory and a controller for controlling writing and reading data to and from the semiconductor memory. The controller operates in such a manner that an amount of each of n currents is deducted from an amount of a current supplied from the power supply, the n currents having n values that gradually increase from the first to n-th. | 09-11-2008 |
| 20080219079 | SEMICONDUCTOR MEMORY DEVICE AND OUTPUT DRIVE CIRCUIT THEREOF - An apparatus for supplying current to a semiconductor memory device. A current supply circuit supplies current to an input/output (I/O) drive circuit responsive to a pattern of data input to the I/O drive circuit. The current supply circuit configured to supply current generated by an external voltage to the I/O drive circuit responsive to a first pattern of data input to the I/O drive circuit, and to prevent the current generated by the external voltage from being supplied to the I/O drive circuit responsive to a second pattern of data input to the I/O drive circuit. | 09-11-2008 |
| 20080239856 | Method for Load-Based Voltage Generation - Method and device for providing voltage generation with load-based control are disclosed. The voltage generation can be provided within an electronic device, such as a memory system that provides data storage. In one embodiment, an electrical load imposed on a generated voltage can be monitored and used to dynamically control strength of the generated voltage. For example, for greater electrical loads, the generated voltage can be provided with a greater strength, and for lesser electrical loads, the generated voltage can be provided with a lesser strength. By compensating the generated voltage for the nature of the imposed electrical load, the generated voltage can be provided in a stable manner across a significant range of loads. In the case of a memory system, stability in the generated voltage provides for reduced voltage ripple and thus improved sensing margins. The voltage generation is well suited for use in portable memory products (e.g., memory cards) to generate one or more internal voltages. | 10-02-2008 |
| 20080259710 | SYSTEM AND METHOD FOR POWER MANAGEMENT OF STORAGE RESOURCES - A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response to the detection of the occurrence of the event. A system may include a storage resource and a power management module communicatively coupled to the storage resource. The storage resource may be disposed in an array of storage resources. The power management module may be operable to detect an occurrence of an event associated with the storage resource, and may be operable to transition the storage resource into a specified power state in response to the detection of the occurrence of the event. | 10-23-2008 |
| 20080259711 | Print Engine Having Authentication Device For Preventing Multi-Word Memory Writing Upon Power Drop - A print engine comprising at least one print controller and at least one associated authentication device is provided. Each authentication device has a processor, non-volatile memory, an input for receiving power from a power supply and a power detection unit. Each authentication device is configured to enable multi-word writes to the non-volatile memory under control of the associated print controller. The processor is configured to control and trim the amount of power supplied to the input to predetermine a threshold at which operation of the authentication device is established. The power detection unit is configured to monitor a voltage level of the power supplied to the input, and in the event the voltage level drops below the predetermined threshold, preventing subsequent words in any multi-word write currently being performed from being written to the memory. | 10-23-2008 |
| 20080266995 | METHOD OF SELECTIVELY POWERING MEMORY DEVICE - An approach to selectively powering a memory device is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various methods are provided to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state. | 10-30-2008 |
| 20080266996 | MEMORY POWER SUPPLY CIRCUIT - A memory power supply circuit configured for supplying power to two types of memories slots of a motherboard includes a slot detecting terminal configured to connect with a detecting pin of the motherboard which is used to detect the memory slots, an electrical switch element, a first resistor, a second resistor, a third resistor, and a voltage output terminal connected to power input pins of the two types of memories slots. The second resistor and third resistor are connected in series between a first power supply and ground. The slot detecting terminal is connected to a first terminal of the electrical switch element. A second terminal of the electrical switch element is grounded. A third terminal of the electrical switch element is connected to the voltage output terminal via the first resistor and connected to a node between the second and third resistors. | 10-30-2008 |
| 20080266997 | VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS - Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level. | 10-30-2008 |
| 20080273412 | MEMORY DEVICE WITH SPLIT POWER SWITCH - A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state. | 11-06-2008 |
| 20080273413 | SEMICONDUCTOR DEVICE - A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode. | 11-06-2008 |
| 20080279029 | LOW VOLTAGE DATA PATH IN MEMORY ARRAY - A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch. | 11-13-2008 |
| 20080279030 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage stabilization circuit includes a control signal generating unit not generating a control signal that is enabled when a supply voltage is unstable and a voltage level maintaining unit for selectively controlling total capacitance of a plurality of capacitors to stabilize the supply voltage in response to the control signal. | 11-13-2008 |
| 20080298155 | SEMICONDUCTOR MEMORY DEVICE COMPENSATING LEAKAGE CURRENT - A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage current compensating circuit comprises a plurality of MOSFETs. Each MOSFET has the same conduction type as a MOSFET whose output node is directly connected to the bit line in the memory cell. Each MOSFET of the leakage current compensating circuit has a gate electrode connected to a first voltage node and a source electrode connected to a second voltage node, and thereby, being biased so that the MOSFET turns off. | 12-04-2008 |
| 20080298156 | SEMICONDUCTOR DEVICE UNDERGOING DEFECT DETECTION TEST - A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode. | 12-04-2008 |
| 20080304349 | VOLTAGE SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY - A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit. | 12-11-2008 |
| 20090003112 | REDUCED SIGNAL LEVEL SUPPORT FOR MEMORY DEVICES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to provide a driver signal to the memory device. In some embodiments, the driver signal is substantially symmetrical around the controllable voltage reference. | 01-01-2009 |
| 20090003113 | Block-by-Block Leakage Control and Interface - In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts a local clock if the sub-array is addressed. The method includes the act of asserting a sleep signal while addressing a given one of the sub-arrays such that only the given one of the sub-arrays is placed into the sleep mode. | 01-01-2009 |
| 20090016137 | Memory Controller with Programmable Regression Model for Power Control - A memory controller uses a throttling mechanism which estimates a throttling delay for achieving a target power consumption, and periodically blocks all memory commands for a number of clock cycles corresponding to the throttling delay. Idle memory ranks of the memory device are powered down while the memory commands are blocked. A regression model bases the throttling delay on a plurality of operating factors and a plurality of regression coefficients for the operating factors. In the illustrative implementation the operating factors include power consumption, a current number of bank conflicts, a current number of read commands, and a current number of write commands. Different sets of regression coefficients can be programmably stored for use with different system configurations. | 01-15-2009 |
| 20090016138 | MEMORY CELLS WITH POWER SWITCH CIRCUIT FOR IMPROVED LOW VOLTAGE OPERATION - Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions. | 01-15-2009 |
| 20090016139 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line. | 01-15-2009 |
| 20090027990 | ADAPTIVE VOLTAGE CONTROL FOR SRAM - The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage. | 01-29-2009 |
| 20090034352 | METHOD AND CIRCUIT FOR PREVENTING HIGH VOLTAGE MEMORY DISTURB - A circuit and method reduces disturb in a memory array resulting from one of two supply voltages dropping below a predetermined value. Memory control logic is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in response to an oscillator oscillating. The higher voltages are used to operate the memory array. Operation of the oscillator is controlled with the memory control logic when the logic power domain is at least at a first level or value. The oscillator is disabled when the logic power domain is below the first level. The disabling of the oscillator has the effect of preventing generation of the higher voltages. This facilitates preventing the higher voltages from reaching the memory array when they may not be properly controlled. | 02-05-2009 |
| 20090034353 | Semiconductor memory device - A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is supplied from an external power source. The power-supply lines extend in a given direction in an area in which the multiple mats are formed and the other end of each line of the multiple power-supply lines is connected in common on the edge mat. | 02-05-2009 |
| 20090040857 | INTEGRATED CIRCUIT INCLUDING DECOUPLING CAPACITORS THAT CAN BE DISABLED - An integrated circuit includes a decoupling capacitor configured to be enabled in response to the decoupling capacitor not increasing a standby current of the integrated circuit and disabled in response to the decoupling capacitor increasing the standby current of the integrated circuit. | 02-12-2009 |
| 20090059705 | SRAM HAVING ACTIVE WRITE ASSIST FOR IMPROVED OPERATIONAL MARGINS - A static random access memory (SRAM) is provided which includes a plurality of columns and a plurality of cells arranged therein. A voltage control circuit can be used to temporarily reduce a voltage at which power is supplied to cells belonging to a column selected for a write operation. The voltage control circuit may include a first p-type field effect transistor (PFET) and a second PFET. The first PFET may have a conduction path connected between a power supply and the cells belonging to the selected column. The second PFET may have a conduction path connected between the cells belonging to the selected column and ground. Such voltage control circuit may operate in a self-limited manner that avoids overshooting the reduced voltage level. In a variation thereof, a voltage control circuit having first and second NFETs (n-type field effect transistors) can be used to temporarily raise the voltage of a low voltage reference provided to cells of the SRAM. | 03-05-2009 |
| 20090059706 | SRAM ACTIVE WRITE ASSIST METHOD FOR IMPROVED OPERATIONAL MARGINS - A method is provided for controlling a voltage level supplied to a static random access memory (“SRAM”). In such method, when a column of the SRAM is selected for writing, a first p-type field effect transistor (“PFET”) and a second PFET can be operated to supply the power at a lower voltage level to cells belonging to a selected column, the lower voltage level being lower than the power supply voltage level. The first PFET can have a conduction path connected between a power supply and the cells belonging to the selected column. The second PFET may have a conduction path connected between the cells belonging to the selected column and ground. While supplying the power at the lower voltage level, a cell belonging to the selected column may be written. When the column is no longer selected for writing, the first and second PFETs can be operated to supply the power at the power supply voltage level again to the cells belonging to the selected column. | 03-05-2009 |
| 20090080279 | STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP - Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage. | 03-26-2009 |
| 20090086561 | MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORIES - An exemplary motherboard includes a driving module, a first slot module arranged for mounting a first type of memory and connected to the driving module via a first channel, a second slot module arranged for mounting a second type of memory and connected to the driving module via a second channel, and a voltage regulator electronically connected to the first slot module and the second slot module. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly. | 04-02-2009 |
| 20090103385 | MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORIES - An exemplary motherboard includes a driving module, at least two first slots arranged for mounting two first type of memories, at least two second slots arranged for mounting two second type of memories, and a voltage regulator. The driving module is electronically connected to the at least two first slots, the at least two second slots, and the voltage regulator in turn via a channel. The first type of memories and the second type of memories are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of memory mounted on the motherboard accordingly. | 04-23-2009 |
| 20090109785 | MEMORY HAVING CIRCUITRY CONTROLLING THE VOLTAGE DIFFERENTIAL BETWEEN THE WORD LINE AND ARRAY SUPPLY VOLTAGE - An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage differential generating circuit is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage. | 04-30-2009 |
| 20090116328 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period. | 05-07-2009 |
| 20090116329 | INTERNAL-VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An internal-voltage generating circuit includes a plurality of generating units connected in cascade, out of the plurality of generating units, a generating unit of relatively lower level is activated by an output of a generating unit of relatively higher level. According to the present invention, because the plural voltage generating units are connected in cascade, the voltage generating unit of lower level is not activated unless the voltage generating unit of higher level is activated. Therefore, at least the voltage generating unit of the second level and the subsequent voltage generating units consume very small power during the standby time. Consequently, total power consumption of the internal-voltage generating circuit can be reduced. | 05-07-2009 |
| 20090122633 | INTEGRATED CIRCUIT WITH CONTROLLED POWER SUPPLY - An integrated circuit comprises a main circuit, a supply circuit configured to provide a supply current to the main circuit, a sensing circuit configured to sense the supply current, and a control circuit configured to control the supply circuit based on the sensed current. | 05-14-2009 |
| 20090122634 | CIRCUIT AND METHOD FOR SUPPLYING A REFERENCE VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS - A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator in a test mode. | 05-14-2009 |
| 20090129191 | Structure for SRAM voltage control for improved operational margins - A design structure including a static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes voltage control circuits corresponding to respective ones of the plurality of columns of the array, each coupled to an output of a power supply. Each voltage control circuit temporarily reduces a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The power supply voltage to the selected column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column. | 05-21-2009 |
| 20090129192 | DESIGN STRUCTURE FOR LOW OVERHEAD SWITCHED HEADER POWER SAVINGS APPARATUS - A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode. | 05-21-2009 |
| 20090141579 | Power Up/Down Sequence Scheme for Memory Devices - A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected. | 06-04-2009 |
| 20090147610 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second memory circuits that are disposed in different power source blocks and operate in synchronization with a clock, first and second delay circuits that are connected between output terminals of one memory circuits and input terminals of the other memory circuits, and a determination circuit that determines whether it is a situation that can cause malfunction based on an input signal and an output signal in the memory circuits and outputs a determination result as an error detection signal. To the first and second memory circuits, different initial values are given, and it is monitored whether a signal is sent and received between the memory circuits in a toggle state or not. Thus, occurrence of a situation that can cause malfunction can be simply and quickly detected. | 06-11-2009 |
| 20090147611 | BULK VOLTAGE DETECTOR - A bulk voltage detector comprises a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased within a predetermined voltage range around the target level, and an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first detection signal. | 06-11-2009 |
| 20090154280 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously. | 06-18-2009 |
| 20090161471 | Power supply device - A power supply device is provided according to the present invention. The power supply device is applicable to electronic device, which has a non-volatile memory and a power supply circuit that provides power to the non-volatile memory. The power supply device includes: a power consuming unit for providing the non-volatile memory with a power release path; a control unit electrically connected to the power supply circuit, the non-volatile memory, and the power consuming unit, has and having a first connection end, a switching end, and a second connection end for being selectively electrically connected to the first connection end or the second connection end via the switching end. When the switching end is electrically connected to the first connection end, the power release path between the power consuming unit and the non-volatile memory is disenabled to allow the non-volatile memory to operate normally, and when the switching end is electrically connected to the second connection end, the power release path between the power consuming unit and the non-volatile memory is enabled, thereby executing discharging process of the non-volatile memory via the power consuming unit, and solving many disadvantages of prior art. | 06-25-2009 |
| 20090161472 | MEMORY VOLTAGE CONTROL CIRCUIT - A memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals. The memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot. | 06-25-2009 |
| 20090161473 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 06-25-2009 |
| 20090168582 | Internal voltage generating circuit and semiconductor memory device using the same - Disclosed is an internal voltage generating circuit. The internal voltage generating circuit comprises a voltage divider for generating a level signal by voltage-dividing first internal voltage, a pull-down signal generator for generating a pull-down signal, which has a level adjusted according to a temperature, in response to the level signal, a pull-up signal generator for generating a pull-up signal, which has a level adjusted according to the temperature, in response to the level signal, and a driving unit for driving second internal voltage in response to the pull-down signal and the pull-up signal. Driving force of the driving unit for driving the second internal voltage is changed according to the temperature. | 07-02-2009 |
| 20090168583 | Internal voltage generator of semiconductor memory device - An internal voltage generator of a semiconductor memory device generates pumping voltages (VPP, VBB, etc.) as internal voltages, which is capable of improving a charge pumping scheme. The internal voltage generator includes a plurality of charge pumping units for generating a pumping voltage by performing a charge pumping operation according to a plurality of pumping enable signals, and a pumping controller for controlling a number of the pumping enable signals to be activated according to a level of a fed-back pumping voltage. | 07-02-2009 |
| 20090168584 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode. | 07-02-2009 |
| 20090168585 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal. | 07-02-2009 |
| 20090168586 | CIRCUIT TO CONTROL VOLTAGE RAMP RATE - A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability. | 07-02-2009 |
| 20090175112 | Table lookup voltage compensation for memory cells - Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell. | 07-09-2009 |
| 20090175113 | CHARACTERIZATION OF BITS IN A FUNCTIONAL MEMORY - Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports, an array of memory cells organized in rows and columns and a word line controlled by a word line driver that provides row access to a memory cell of the array. Additionally, the functional memory also includes a bit line controlled by a direct bit line access circuit that provides direct bit line access to the memory cell through a bit line analog access port and an independent voltage supply port. | 07-09-2009 |
| 20090180345 | VOLTAGE BOOSTER BY ISOLATION AND DELAYED SEQUENTIAL DISCHARGE - Systems and methods for improving efficiency of a voltage booster for read mode operations of memory cells and discharging a boosted supply voltage safely are disclosed. The system contains a plurality of boosting stages coupled in series including a plurality of boosting capacitors, a plurality of isolators. The isolator can be used to prevent boosting of one capacitor from negatively affecting a charge of the other adjacent capacitor to improve the efficiency of the voltage booster. A voltage booster circuit can accurately boost a supply voltage with a suitable number of boosting stages depending on a level of the supply voltage being provided. Since boosters contain a suitable number of boosting stages, the boosters can discharge a boosted voltage sequentially. With this sequential discharge method, memory cells can not have a hot switching problem. | 07-16-2009 |
| 20090180346 | PORTABLE DATA STORAGE APPARATUS - A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory. | 07-16-2009 |
| 20090196115 | SEMICONDUCTOR DEVICE FOR PREVENTING ERRONEOUS WRITE TO MEMORY CELL IN SWITCHING OPERATIONAL MODE BETWEEN NORMAL MODE AND STANDBY MODE - When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state. | 08-06-2009 |
| 20090213676 | Memory Device - A nonvolatile memory device contains at least one nonvolatile memory module and an electrical buffer for buffering a supply voltage for the at least one nonvolatile memory module. A microprocessor may be connected in parallel or serial fashion to the memory device, or may contain the memory device. | 08-27-2009 |
| 20090213677 | Memory Cell Array - A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level. | 08-27-2009 |
| 20090213678 | High yielding, voltage, temperature, and process insensitive lateral poly fuse memory - The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding, voltage, temperature, and process insensitive lateral poly fuse memory. In one embodiment, a fusible link memory circuit includes a fusible link memory element and a programming circuit. The programming circuit includes a replica of the fusible link memory element and a programming current source for producing a known current density in the fusible link memory element in spite of variations including at least process variations. | 08-27-2009 |
| 20090219777 | MULTI-CHIP ASSEMBLY AND METHOD FOR DRIVING THE SAME - Disclosed are a multi-chip assembly and a method for driving the same. The multi-chip assembly includes a first chip designed with a first device driven by a first power source and a second chip designed with a second device driven by a second power source. A power applying section applies first power to the first device of the first chip and a power converting section converts the first power to second power upon receiving the first power from the power applying section and applies the second power to the second device of the second chip. It is possible to provide the multi-chip assembly in the form of a package fabricated by stacking chips designed with mutually different devices driven through a single power source. | 09-03-2009 |
| 20090231940 | MEMORY AND VOLTAGE MONITORING DEVICE THEREOF - A memory and a voltage monitoring device thereof are provided. the voltage monitoring device of the memory includes a system voltage detector, a charge pump circuit and a data output unit. The system voltage detector is coupled to the charge pump circuit and the data output unit for detecting a system voltage and thereby producing control signals. The charge pump circuit can produce a word line voltage according to the above-mentioned control signals. The data output unit decides outputting the above-mentioned control signals or the output data of the memory according to a special command, wherein the control signals correspond to the word line voltages. Therefore, the control signals and the word line voltages may be easily monitored. | 09-17-2009 |
| 20090231941 | Memory System with Low Current Consumption and Method for the Same - A memory system includes: a high-voltage-supply booster circuit for driving an access control circuit from a low voltage for memory access to a high voltage for memory access by supplying electric charge that is stored in advance to an access control circuit in response to an access start request for a memory cell array; and a low-voltage-supply booster circuit for absorbing excess electric charge when the access control circuit is switched from the high voltage to the low voltage in response to an access end request for the memory cell array. | 09-17-2009 |
| 20090238023 | MEMORY SYSTEM - A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error. | 09-24-2009 |
| 20090245007 | SELECTIVELY CONTROLLED MEMORY - Embodiments of methods, apparatuses, and systems that enable power conservation in data buffering components are disclosed. Other embodiments may also be disclosed. | 10-01-2009 |
| 20090251983 | SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF REDUCING GROUND NOISE - An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level. | 10-08-2009 |
| 20090251984 | Static memory device and static random access memory device - A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group. | 10-08-2009 |
| 20090251985 | SEMICONDUCTOR MEMORY APPARATUS - A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals. | 10-08-2009 |
| 20090257301 | Voltage Level Comparison Circuit of Semiconductor Memory Apparatus, Voltage Adjustment Circuit Using Voltage Level Comparison Circuit, and Semiconductor Memory Apparatus Using the Same - A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage. | 10-15-2009 |
| 20090257302 | Semiconductor memory apparatus capable of reducing ground noise - An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level. | 10-15-2009 |
| 20090262594 | MEMORY CELLS WITH POWER SWITCH CIRCUIT FOR IMPROVED LOW VOLTAGE OPERATION - Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions. | 10-22-2009 |
| 20090268540 | Systems and Methods for Dynamic Power Savings in Electronic Memory Operation - Power reduction is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control address selection with respect to segments beyond a first segment. The latch repeaters are, in one embodiment, allowed to remain in their operated/non-operated state at the completion of a memory read/write cycle. This then avoids successive enabling pulses when the same segment is accessed on successive cycles. | 10-29-2009 |
| 20090268541 | DESIGN STRUCTURE FOR ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH, METHOD OF ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH AND CIRCUIT THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals or exceeds a value of the threshold register. Also provided is a method of predicting and/or estimating a power cycle duration in order to save a state in non-volatile memory and a circuit. The method includes setting a threshold value; determining that the threshold value has been equaled or exceeded; and saving the state in the non-volatile memory at a first checkpoint based on the threshold value being equaled or exceeded. | 10-29-2009 |
| 20090274000 | SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP - Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory. | 11-05-2009 |
| 20090279374 | SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE - The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines. | 11-12-2009 |
| 20090279375 | VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY - A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array. | 11-12-2009 |
| 20090279376 | METHOD AND SYSTEM FOR SELECTIVELY LIMITING PEAK POWER CONSUMPTION DURING PROGRAMMING OR ERASE OF NON-VOLATILE MEMORY DEVICES - A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array. | 11-12-2009 |
| 20090323451 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply voltage pad for a data strobe signal output circuit. The first power mesh connects first power supply voltage pads to one another. The second power supply voltage pad is electrically separated from the first power mesh. | 12-31-2009 |
| 20100002531 | Multi-Port Memory Devices Having Clipping Circuits Therein that Inhibit Data Errors During Overlapping Write and Read Operations - An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line. | 01-07-2010 |
| 20100014375 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode. | 01-21-2010 |
| 20100020628 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value. | 01-28-2010 |
| 20100027365 | NON-VOLATILE MEMORY DEVICE CAPABLE OF SUPPLYING POWER - A non-volatile memory device capable of supplying power is provided. The non-volatile memory device includes an electrical storage device for supplying a stored power, a charging control circuit coupled to the electrical storage device, a non-volatile memory, an input/output (I/O) interface, and a power control circuit. The I/O interface connects an electronic apparatus for transmitting an external power output from the electronic apparatus to the non-volatile memory and the charging control circuit, such that the charging control circuit could control a charging current and a charging voltage of the electrical storage device. The power control circuit converts the stored power into a backup power, and monitors whether a voltage value of the external power is less than a predetermined value. If the result is positive, the power control circuit controls the charging control circuit to stop charging the electrical storage device, and outputs the backup power through the I/O interface. | 02-04-2010 |
| 20100027366 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The discharge transistors receive mutually independent discharge control signals which are generated and outputted from a DS decoder driver at the respective gates thereof. To the bit line which applies the ground voltage to the memory cell, the ground voltage can be set using the discharge transistor. | 02-04-2010 |
| 20100034042 | POWER CONSUMPTION-ORIENTED MANAGEMENT OF A STORAGE SYSTEM - A method of managing operation of a plurality of devices that includes receiving operational information that pertains to each of a plurality of device and managing operation of at least one of the plurality of devices. Each of the plurality of devices is configured to perform operations, the operations including sub-operations. The operation management includes associating parameters for a given sub-operation of a device based on 1) operational information pertaining to at least one of the plurality of devices and on 2) a maximum allowable current consumption level. Also provided is a system that includes a plurality of devices and a controller that is operationally connected to each of the plurality of devices for setting values for parameters of a device for a given sub-operation based on 1) operational information pertaining to at least one of the devices and on 2) a maximum allowable current consumption level of the system. | 02-11-2010 |
| 20100034043 | SEMICONDUCTOR IC DEVICE HAVING POWER-SHARING AND METHOD OF POWER-SHARING THEREOF - A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals. | 02-11-2010 |
| 20100034044 | SEMICONDUCTOR DEVICE - A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches. | 02-11-2010 |
| 20100054071 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided which has a memory cell region in which a plurality of memory cells are arranged in a matrix. The memory cell region is divided into a plurality of sectors each including a predetermined number of rows. Main bit lines extending in a column direction have an intersecting region between the sectors in which the main bit lines intersect at one or more points. The semiconductor memory device is configured to be able to supply different voltages to neighbor ones of the main bit lines in each of the sectors. | 03-04-2010 |
| 20100061174 | Y-DECODER AND DECODING METHOD THEREOF - AY-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage. | 03-11-2010 |
| 20100061175 | CIRCUIT AND METHOD FOR DRIVING WORD LINE - A method for activating a word line inactivated with a negative voltage includes applying an intermediate voltage to the word line; and applying an activation voltage to the word line, wherein the intermediate voltage has a voltage level between the activation voltage and the negative voltage. A circuit and a method for driving a word line, and the circuit for driving the word line includes a first driving device for driving the word line with an activation voltage; a second driving device for driving the word line with an inactivation voltage; and a third driving device for driving the word line with a voltage between the activation voltage and the inactivation voltage. | 03-11-2010 |
| 20100061176 | Semiconductor Memory Device and Method of Operating the Same - A semiconductor memory device includes a plurality of word lines, a plurality of pairs of bit lines and complementary bit lines that cross the word lines, and a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a bit line and a complementary bit line cross each other. A voltage control unit includes a plurality of elements connected in series between a power voltage source and the memory cells and are switched on/off in response to a control signal that controls an operation of the plurality of memory cells. The voltage control unit controls the voltage of the power voltage source to a predetermined level, thereby obtaining a controlled voltage to be supplied to the memory cells. | 03-11-2010 |
| 20100074043 | SEMICONDUCTOR DEVICE - A semiconductor device includes an internal circuit configured to receive a first power supply voltage applied via a first power input terminal through a first power supply path and receive an internal power supply voltage to perform a predetermined circuit operation and an internal power supply voltage generator configured to receive a second power supply voltage for a power circuit applied via a second power input terminal through a second power supply path and generate the internal power supply voltage, wherein the second power supply path is separated from the first power supply path. | 03-25-2010 |
| 20100085828 | Method for Reducing Leakage Current of a Memory and Related Device - A method for reducing leakage current of a memory device includes supplying a first voltage to a main wordline driver, supplying a second voltage greater than the first voltage to a local wordline driver, and employing a transistor in the local wordline driver with a threshold voltage greater than a specific value. | 04-08-2010 |
| 20100085829 | Internal voltage generation circuit - An internal voltage generation circuit includes a temperature detection unit which detects an internal temperature of a semiconductor memory device and generates a temperature signal, a driving control signal generation unit which receives the temperature signal and generates first and second driving control signals, and an internal voltage generation unit which receives the first and second driving control signals and generates an internal voltage. | 04-08-2010 |
| 20100091597 | SEMICONDUCTOR DEVICE - A semiconductor device includes an internal voltage generating circuit which includes a first voltage generating circuit, a second voltage generating circuit having a higher current supply capability than the first voltage generating circuit, and a control circuit that controls switching between activation and inactivation of the second voltage generating circuit, using a first internal signal of the first voltage generating circuit. | 04-15-2010 |
| 20100097875 | Enhanced Power Distribution in an Integrated Circuit - An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells. | 04-22-2010 |
| 20100097876 | APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY - A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator. | 04-22-2010 |
| 20100097877 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal. | 04-22-2010 |
| 20100103759 | POWER LINE DECODING METHOD FOR AN MEMORY ARRAY - A method for selectively providing power supply voltage to a memory device. The method provides an integrated circuit memory device including a first plurality of memory cells. Each memory cell includes a power terminal and a ground terminal. The method includes selecting a second plurality of memory cells from the first plurality of memory cells. The method provides a first power voltage to the power terminal of each of the selected memory cells and a second power voltage to the power terminal of each of the unselected memory cells. The second power voltage is lower than the first power voltage. In an embodiment, the method applies a first ground voltage to the ground terminal of each of the selected memory cells and applies a second ground voltage to the ground terminal of each of the unselected memory cells. The second ground voltage is higher than the first ground voltage. | 04-29-2010 |
| 20100110819 | Apparatus and Method for Placement of Boosting Cell With Adaptive Booster Scheme - A memory is provided. The memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pass gate voltage provided to the gates of pass line transistor in a sector decoders and/or an array decoder for the memory cells being accessed. The boost converter circuitry includes at least two boost converters, and a switch. When one of the memory arrays is accessed, the switch either couples the boost converters together or does not couple the boost converters together based on the distance of the memory array being accessed from the boost converters. | 05-06-2010 |
| 20100118637 | Circuts and methods for reducing minimum supply for register file cells - A register file employing a shared supply structure to improve the minimum supply voltage. | 05-13-2010 |
| 20100118638 | SEMICONDUCTOR MEMORY APPARATUS HAVING DECREASED LEAKAGE CURRENT - A semiconductor memory apparatus includes a MOS transistor configured to be supplied with a first voltage through a bulk terminal thereof. The semiconductor memory apparatus also includes a current control unit configured to be connected to a source terminal of the MOS transistor, receive a power down mode enable signal and a self refresh mode enable signal, apply a second voltage to the source terminal during a power down mode or a self refresh mode, and apply the first voltage to the source terminal during modes other than the power down mode and the self refresh mode. | 05-13-2010 |
| 20100124140 | POWER SUPPLY CIRCUIT AND NAND-TYPE FLASH MEMORY - A power supply circuit has a control circuit. The control circuit outputs a control clock signal so as to cause a first booster circuit to compulsorily perform boosting operation with a first boosting capability in response to an output signal of a second comparison amplifier after a lapse of a prescribed period since the first booster circuit is started to perform boosting operation with the first boosting capability in response to a first activation signal of a first comparison amplifier. | 05-20-2010 |
| 20100128549 | Memory Circuit Having Reduced Power Consumption - A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered. | 05-27-2010 |
| 20100128550 | LOCAL POWER DOMAINS FOR MEMORY SECTIONS OF AN ARRAY OF MEMORY - Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses. | 05-27-2010 |
| 20100128551 | ADJUSTABLE VOLTAGE REGULATOR FOR PROVIDING A REGULATED OUTPUT VOLTAGE - Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator circuit, a driver circuit, an impedance circuit, and a modulation circuit. The comparator circuit generates an output voltage according to a difference between a reference voltage and a feedback voltage. The driver circuit is coupled to an output of the comparator circuit and drives the regulated output voltage at an output node according to the output voltage from the comparator circuit. The impedance circuit is coupled to the comparator circuit and provides the feedback voltage to the comparator circuit in response to a detection current from the output node. The modulation circuit is coupled to the impedance circuit and adjusts a modulation current component of the detection current to adjust the regulated output voltage. | 05-27-2010 |
| 20100128552 | HIGH-VOLTAGE SAWTOOTH CURRENT DRIVING CIRCUIT AND MEMORY DEVICE INCLUDING SAME - A high-voltage sawtooth current driving circuit and a memory device including the same are described. In the high-voltage sawtooth current driving circuit includes a charge pump circuit configured to output a first voltage, a regulating circuit configured to regulate a second voltage using the first voltage output from the charge pump circuit, and a sawtooth current driver configured to generate a sawtooth current in response to the second voltage regulated by the regulating circuit. | 05-27-2010 |
| 20100135097 | System and Method for Supporting Standard and Voltage Optimized DIMMs - A device includes a dynamic random access memory and a voltage regulator. The dynamic random access memory has a first input terminal connected to a first plurality of dual in-line memory module voltage pins, and a second input terminal. The dynamic random access memory is configured to receive a first voltage on the first input terminal. The voltage regulator has an input terminal connected to a second plurality of dual in-line memory module voltage pins, and an output terminal connected to the second input terminal of the dynamic random access memory. The voltage regulator is adapted to receive a second voltage, and configured to provide a third voltage to the second input terminal of the dynamic random access memory. | 06-03-2010 |
| 20100135098 | Power control circuit and semiconductor memory device using the same - A semiconductor memory device comprises a power control circuit for outputting a power voltage in a read operation period and a write operation period, and an internal circuit operating by the power voltage supplied thereto. | 06-03-2010 |
| 20100135099 | POWER-ON DETECTOR, OPERATING METHOD OF POWER-ON DETECTOR AND MEMORY DEVICE INCLUDING THE SAME - A power-on detector supplied with a power supply voltage from an external source and detects a variation of the power supply voltage. The operating method of the power-on detector comprises calculating the slope of the rise of power supply voltage from a first voltage to a second voltage higher than the first voltage; and calculating the expected time for the power supply voltage to reach a target voltage level, based on the calculated slope. | 06-03-2010 |
| 20100142305 | Source control circuit and semiconductor memory device using the same - A source control circuit comprises a control signal generating unit for generating a standby signal which is enabled in a standby condition, and a switching unit connected between a power line for supplying power to an internal circuit and an external power and controlling the supply of the external power in response to the standby signal. | 06-10-2010 |
| 20100149899 | TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS - Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell. | 06-17-2010 |
| 20100165776 | SEMICONDUCTOR DEVICE - A semiconductor device capable of reducing power consumption is provided. When a power to an internal circuit is interrupted, e.g., in a standby mode, a switch is turned off, and a pseudo-ground line is charged with a leak current of the internal circuit to raise a potential thereof. After the switch is turned off, a switch connected to a charge supply unit is turned on while the potential is rising, so that the charge supply unit is electrically coupled to the pseudo-ground line. Thereby, charges accumulated in the charge supply unit are discharged to the pseudo-ground line. The switch is turned off to decouple electrically the charge supply unit from the pseudo-ground line. Thereby, when the power supply is interrupted, a part of the charges for raising the potential of the pseudo-ground line is supplemented with the charges of the charge supply unit. | 07-01-2010 |
| 20100165777 | CIRCUIT FOR VOLTAGE PUMP AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage pump circuit includes a pumping unit configured to include a plurality of pumps and perform voltage pumping and a pumping control unit configured to generate control signals for selectively driving the pumps in response to a mode determination signal. | 07-01-2010 |
| 20100172201 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF OPERATION MODES - A semiconductor device includes: a first level detecting circuit for detecting a voltage level at a control terminal after a prescribed time period from when a power supply voltage is supplied to a power supply terminal, a control unit for selecting in which operation mode among a plurality of operation modes the semiconductor device operates, based on a result of detection by the first level detecting circuit; and a regulator for generating an internal power supply voltage based on the power supply voltage supplied to the power supply terminal. The first level detecting circuit and the control unit receive the internal power supply voltage as an operating power supply voltage. In an operation mode, among the plurality of operation modes, where a power supply voltage having a level different from that of a power supply voltage in other operation modes is supplied to the power supply terminal, the control unit performs data processing by using the power supply voltage supplied to the power supply terminal. | 07-08-2010 |
| 20100177584 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks; a peripheral circuit configured to send data to and receive data from the plurality of banks; and data lines configured to connect the plurality of banks and the peripheral circuit, wherein the plurality of banks are disposed such that a sum of lengths of data transfer paths of the data lines connecting the peripheral circuit and at least two banks, among the plurality of banks, activated at a same time is uniformly maintained. | 07-15-2010 |
| 20100182865 | Negative-Voltage Generator with Power Tracking for Improved SRAM Write Ability - An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-line connected to the SRAM cell. A negative-voltage generator is coupled to, and configured to output a negative voltage to, the bit-line, wherein the negative-voltage generator is so configured that the negative voltage decreases in response to a decrease in the first positive power supply voltage and increases in response to an increase in the first positive supply voltage. | 07-22-2010 |
| 20100182866 | SEMICONDUCTOR MEMORY DEVICE FOR COMPENSATING FOR OPERATING VOLTAGE DIFFERENCE BETWEEN NEAR CELL AND FAR CELL IN CONSIDERATION OF CELL POSITION, AND MEMORY CARD AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including a matrix of memory cells; a plurality of local bit lines divided into at least two local bit line groups arranged to be alternately connected with at least two global bit lines and coupled with the memory cells; a plurality of bit line selection drivers respectively connected to the local bit lines; an internal boosted voltage generator configured to generate at least two internal boosted voltages having different levels; and a power transmitter configured to respectively transmit the at least two internal boosted voltages to at least two bit line selection driver groups, into which the plurality of bit line selection drivers are classified according to arrangement of the local bit lines. Accordingly, repair efficiency can be increased and near-far compensation can be more correctly performed. | 07-22-2010 |
| 20100182867 | INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - An internal voltage generating circuit of a semiconductor memory device includes a driving current generator that controls the magnitude of a driving current and supplies a controlled driving current in response to signals activated according to an operational mode. A comparison voltage generator receives a reference voltage and an internal power supply voltage, outputs a differentially amplified comparison voltage in response to a voltage difference between the reference voltage and the internal power supply voltage, and operates according to the driving current. A bulk bias controller receives at least two voltages and selectively outputs a voltage as a bulk bias voltage in response to a power-down enable signal, a normal enable signal, and an operating enable signal. An internal voltage driver controls a threshold voltage in response to the bulk bias voltage, controls a current amount in response to the comparison voltage, and outputs the internal power supply voltage. | 07-22-2010 |
| 20100188916 | Setting Memory Controller Driver to Memory Device Termination Value in a Communication Bus - A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is modified to yield improvements in timing margins. | 07-29-2010 |
| 20100188917 | Setting Memory Device Termination in a Memory Device and Memory Controller Interface in a Communication Bus - A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues. | 07-29-2010 |
| 20100188918 | Setting Controller VREF in a Memory Controller and Memory Device Interface in a Communication Bus - A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the controller. | 07-29-2010 |
| 20100188919 | Calibration of Memory Driver With Offset in a Memory Controller and Memory Device Interface in a Communication Bus - A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears to be the reference voltage value to the memory device. A current driven to the memory device is varied in small increments while impedance training is rerun until a desired value is achieved to set the 0 level voltage on the data net. | 07-29-2010 |
| 20100188920 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the first internal power supply voltage from the external power supply voltage in a standby state. The memory circuit includes a cell array containing a nonvolatile memory cell and a sense amplifier detecting data read from the cell array. The sense amplifier is supplied with a voltage generated by the internal step-down power generation circuit as an internal power supply voltage. | 07-29-2010 |
| 20100188921 | VOLTAGE PROTECTION CIRCUIT FOR THIN OXIDE TRANSISTORS, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Devices, reference voltage generators, systems and methods are disclosed, including an embodiment of a voltage regulator output transistor using a thin gate insulator to provide a low output impedance despite having a semiconductor channel width that is relatively small. The output transistor is protected from damage by a clamping circuit provided to limit the gate-to-source voltage of the transistor such that damage to the output transistor should be reduced or prevented. One such clamping circuit includes a clamp transistor that receives a reference voltage at its gate. The magnitude of the reference voltage limits to voltage to which the gate of the transistor can be driven. A voltage reference circuit provides the reference voltage so that it compensates for process and temperature variations of the output transistor. | 07-29-2010 |
| 20100195430 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 08-05-2010 |
| 20100202234 | POWER-ON MANAGEMENT CIRCUIT FOR MEMORY - A power-on management circuit for a memory device is provided. The power-on management circuit comprises a first external power-on voltage detector, a second external power-on voltage detector, a delay unit, a logic circuit, an internal power-on voltage detector, a voltage control circuit, a plurality of first electric pumps and a second electric pump. The first external power-on voltage detector has a first voltage threshold, receives a first external voltage, and generates a first control signal when the first external voltage is higher than the first voltage threshold. The second external power-on voltage detector has a second voltage threshold, receives a second external voltage, and generates a second control signal when the second external voltage is higher than the second voltage threshold. | 08-12-2010 |
| 20100202235 | DEVICE AND METHOD FOR STATE RETENTION POWER GATING - A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of at least one non-reset-state circuit of the group of circuits. | 08-12-2010 |
| 20100214862 | Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same - A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. | 08-26-2010 |
| 20100220539 | MEMORY CIRCUITS, SYSTEMS, AND OPERATING METHODS THEREOF - A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. The memory circuit includes a means for providing a bit line reference voltage VBL | 09-02-2010 |
| 20100220540 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS - A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit. | 09-02-2010 |
| 20100220541 | SWITCHED-CAPACITOR CHARGE PUMPS - A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors. | 09-02-2010 |
| 20100238751 | Method and Apparatus for Increasing Yield in a Memory Device - An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level. | 09-23-2010 |
| 20100238752 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first region configured to operate at a specified first voltage, a second region configured to operate at a varying second voltage, and a memory device formed between the first region and the second region so as to straddle the first and second regions, wherein the memory device comprises a first port driven at the first voltage to transmit an output signal to and receive an input signal from the first region, a second port driven at the second voltage to transmit an output signal to and receive an input signal from the second region, and a memory cell accessed by the first and second ports. | 09-23-2010 |
| 20100246305 | REGULATORS REGULATING CHARGE PUMP AND MEMORY CIRCUITS THEREOF - A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage V | 09-30-2010 |
| 20100246306 | START-UP CIRCUIT OF INTERNAL POWER SUPPLY OF SEMICONDUCTOR MEMORY - There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to an internal power supply circuit, and a discharge unit that is connected to an output side of an inverter at an odd-numbered stage and discharges charges remaining at the connection point between the inverter at the odd-numbered stage and the inverter at the stage immediately thereafter, after supply of power to operate the inverters is stopped. | 09-30-2010 |
| 20100254209 | Ultra-Low Leakage Memory Architecture - An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro. | 10-07-2010 |
| 20100278000 | MEMORY DEVICE CONTROL FOR SELF-REFRESH MODE - In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off. | 11-04-2010 |
| 20100278001 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory core; a charge pump circuit providing a high voltage to the memory core; and a charge pump control circuit operating the charge pump circuit by a standby mode and measuring an operation time value of the standby mode. The charge pump control circuit controls the standby mode of the charge pump circuit using the time value. | 11-04-2010 |
| 20100278002 | CIRCUIT AND METHOD OF PROVIDING CURRENT COMPENSATION - Some embodiments regard a method comprising: during a leakage sampling phase, recognizing a voltage level dropped due to a leakage current associated with a signal linestoring the voltage level; and during a reading phase, using the voltage level to provide an amount of compensation current to the signal line. | 11-04-2010 |
| 20100290304 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal. | 11-18-2010 |
| 20100302891 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device includes a power-up operation unit configured to perform a power-up operation in response to a power-up enable signal and to output a powered-up control signal, and configured to output a power-up completion signal after the power-up operation is completed, an internal circuit configured to operate in response to the powered-up control signal, and a power-up detection unit configured to output a power-up flag signal in response to the power-up completion signal. | 12-02-2010 |
| 20100302892 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase. | 12-02-2010 |
| 20100309742 | METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY - Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports. | 12-09-2010 |
| 20100329062 | Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. | 12-30-2010 |
| 20100329063 | DYNAMICALLY CONTROLLED VOLTAGE REGULATOR FOR A MEMORY - A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM. | 12-30-2010 |
| 20110007596 | Low-Leakage Power Supply Architecture for an SRAM Array - A method of forming an integrated circuit structure includes providing a chip; forming a static random access memory (SRAM) cell including a transistor on the chip; and forming a bias transistor configured to gate a power supply voltage provided to the SRAM cell on the chip. The bias transistor and the transistor of the SRAM cell are formed simultaneously. | 01-13-2011 |
| 20110026354 | CURRENT LEAKAGE REDUCTION - An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks. | 02-03-2011 |
| 20110032783 | SEMICONDUCTOR STORAGE APPARATUS, AND METHOD AND SYSTEM FOR BOOSTING WORD LINES - A semiconductor storage apparatus includes: a word line coupled to a cell transistor; a first capacitor having a first end coupled to the word line; a boost driver coupled to a second end of the first capacitor; a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and a boost-drive circuit configured to boost a voltage at the second end from the second voltage to the first voltage. | 02-10-2011 |
| 20110063937 | SYSTEM AND METHOD TO COMPENSATE FOR PROCESS AND ENVIRONMENTAL VARIATIONS IN SEMICONDUCTOR DEVICES - An integrated circuit (IC) including a controller integrally formed on a shared die with the IC and method of operating the same to compensate for process and environmental variations in the IC are provided. In one embodiment the IC is comprised of device and sub-circuits, and the method includes: receiving in the IC electrical power and information on at least one of one or more operational parameters of the IC; and adjusting one or more operating characteristics of at least one of the devices and sub-circuits in the IC based on the received information using a controller integrally formed on a shared die with the IC. Other embodiments are also disclosed. | 03-17-2011 |
| 20110069574 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, a word line driver, and a bit line booster. The memory cell array has multiple word lines WL, multiple bit line pairs BL, and multiple memory cells MC provided at the respective intersections of the word lines WL and the bit line pairs BL. The word line driver drives a selected word line WL to a positive voltage VWL when data is written to the memory cells MC. The bit line booster drives a selected bit line pair BL to a negative voltage VBL corresponding to the voltage VWL when data is written to the memory cells MC. | 03-24-2011 |
| 20110075501 | Multi-Channel Semiconductor Integrated Circuit Devices for Controlling Direct Current Generators and Memory Systems Including the Same - Multi-channel semiconductor integrated circuit devices are provided including a plurality of memory devices that are independently accessible, each of the plurality of memory devices including at least one power generation unit and a control unit for controlling an operation of the at least one power generation unit, a detection unit for detecting an operation state of the plurality of memory devices, and a common control unit for commonly controlling an operation of the at least one power generation unit of the plurality of memory devices, according to the operation state of the plurality of memory devices detected by the detection unit. The control unit of each of the plurality of memory devices controls the operation of the at least one power generation unit of a corresponding one of the plurality of memory devices. | 03-31-2011 |
| 20110085399 | Method for Extending Word-Line Pulses - An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current. | 04-14-2011 |
| 20110085400 | SEMICONDUCTOR DEVICE - A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches. | 04-14-2011 |
| 20110090753 | POWER MANAGEMENT - An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power. | 04-21-2011 |
| 20110090754 | INTERNAL POWER GENERATING APPARATUS, MULTICHANNEL MEMORY INCLUDING THE SAME, AND PROCESSING SYSTEM EMPLOYING THE MULTICHANNEL MEMORY - An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states. | 04-21-2011 |
| 20110122720 | CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING SIMULTANEOUS SWITCHING OUTPUT NOISE, POWER NOISE, OR COMBINATIONS THEREOF - Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal. | 05-26-2011 |
| 20110141837 | Voltage regulation circuitry - Voltage regulation circuitry is provided comprising a pull-up p-type threshold device connecting a supply voltage node to an output voltage node, the pull-up p-type threshold device configured to be switched off in dependence on a control signal. A pull-down stack connects the output voltage node to a reference voltage node, the pull-down stack comprising a pull-down p-type threshold device and a pull-down n-type threshold device connected in series. An inverter is configured to receive an input from the output voltage node and is configured to generate a cut-off signal, wherein the pull-down n-type threshold device is configured to be switched on in dependence on the control signal and the pull-down p-type threshold device is configured to be switched off in dependence on the cut-off signal. | 06-16-2011 |
| 20110141838 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros. | 06-16-2011 |
| 20110149671 | Operation Method and Leakage Controller for a Memory and a Memory Applying the Same - An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step. | 06-23-2011 |
| 20110149672 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a circuit required to be in a data retaining state; a data retention characteristic evaluation circuit configured to measure the data retaining state of the circuit; a leakage current evaluation circuit configured to measure the leakage current in the circuit; a voltage control signal generation circuit configured to control a voltage supply circuit for the circuit; and a memory circuit configured to store measurement results of the leakage current evaluation circuit and the data retention characteristic evaluation circuit. The voltage control signal generation circuit sets, for the voltage supply circuit, a voltage with which the leakage current in the circuit is minimized, based on data stored in the memory circuit. | 06-23-2011 |
| 20110158027 | REGULATOR CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device includes a charge pump circuit for generating a pass pump voltage in response to a clock signal and a pump enable signal and a regulator circuit for maintaining the pass pump voltage in the same level as a program pass voltage during a program operation and discharging the program pass voltage during a verification operation so that the program pass voltage has the same level as a verification pass voltage. | 06-30-2011 |
| 20110170368 | CHARGE PUMP SYSTEM AND METHOD UTILIZING ADJUSTABLE OUTPUT CHARGE AND COMPILATION SYSTEM AND METHOD FOR USE BY THE CHARGE PUMP - Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a charge pump circuit. The method includes adjusting an output charge of the charge pump circuit by selecting a number of boost capacitors at least one of using a digital control word and by programming of a wiring level | 07-14-2011 |
| 20110182131 | SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT - A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented. | 07-28-2011 |
| 20110188334 | FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse. | 08-04-2011 |
| 20110199850 | MEMORY READOUT SCHEME USING SEPARATE SENSE AMPLIFIER VOLTAGE - A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump circuit is configured to provide a second voltage to the sense amplifier when a read operation is performed. | 08-18-2011 |
| 20110205827 | SEMICONDUCTOR INTEGRATED CIRCUIT - A system LSI ( | 08-25-2011 |
| 20110211412 | TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS - Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell. | 09-01-2011 |
| 20110216618 | VOLTAGE COMPENSATED TRACKING CIRCUIT IN SRAM - Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier enable (SE) signal in a memory. The tracking circuit receives an array supply voltage (VDDAR) and a periphery supply voltage (VDDPR). Further, the circuit includes a discharge control circuit, operatively coupled to the tracking circuit, for increasing delay in activating a first transistor of the tracking circuit when VDDAR is higher than VDDPR; and a contention circuit including an output coupled to the first transistor, for delaying a discharge path activation through the first transistor when VDDAR is lower than the VDDPR. | 09-08-2011 |
| 20110228622 | VOLTAGE REGULATOR BYPASS IN MEMORY DEVICE - A memory chip comprises an internal voltage regulator that is selectively enabled/disabled to regulate an external voltage used by the memory chip subunit. | 09-22-2011 |
| 20110228623 | POWER-UP CIRCUIT - A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value. The second internal supply voltage potential detector is configured to detect a second internal supply voltage that is internal to the memory device and to receive the first detection signal and an output voltage of the first internal supply voltage potential detector for generating a third detection signal indicating whether the voltage potentials of the external supply voltage and the first and second internal supply voltages reach the first, second, and third predetermined values respectively. The logic circuit is configured to receive the third detection signal and to generate a power-up signal. | 09-22-2011 |
| 20110235454 | High-voltage selecting circuit which can generate an output voltage without a voltage drop - A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time. | 09-29-2011 |
| 20110235455 | VOLTAGE REGULATORS, AMPLIFIERS, MEMORY DEVICES AND METHODS - Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit may allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided. | 09-29-2011 |
| 20110235456 | POWER SUPPLY CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A power supply control circuit includes a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals; and a plurality of power blocks configured to supply power to a plurality of memory banks of a plurality of chips based on the plurality of power supply enable signals. | 09-29-2011 |
| 20110235457 | SEMICONDCUTOR INTEGRATED CIRCUIT DEVICE - According to one embodiment, a semiconductor integrated circuit device is provided. The semiconductor integrated circuit device is provided with a plurality of booster circuits, a regulator and a plurality of switches. Each of the booster circuit receives an input voltage, boosts the input voltage, and generates a boosted voltage having a different value. The regulator is capable of generating a plurality of dropped voltages by dropping each boosted voltage from the booster circuits. The switches are connected between the booster circuits and the regulator. The switches provide the boosted voltages outputted from the booster circuits selectively to the regulator as a power-supply voltage. | 09-29-2011 |
| 20110267916 | VDD PRE-SET OF DIRECT SENSE DRAM - A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line. | 11-03-2011 |
| 20110273951 | MEMORY CIRCUIT AND METHOD FOR CONTROLLING MEMORY CIRCUIT - A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage. | 11-10-2011 |
| 20110273952 | SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented. | 11-10-2011 |
| 20110280094 | Boost Cell Supply Write Assist - A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit. | 11-17-2011 |
| 20110280095 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. | 11-17-2011 |
| 20110280096 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers. | 11-17-2011 |
| 20110286294 | METHOD OF FORMING A UNIQUE NUMBER - A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells. | 11-24-2011 |
| 20110305100 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers | 12-15-2011 |
| 20110310689 | POWER SOURCE AND POWER SOURCE CONTROL CIRCUIT - Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node are disclosed. An example power source includes an input, backup power source, and a backup power source control circuit. The input is configured to be coupled to a primary power source and further configured to couple the primary power source to the output when the input is coupled to the primary power source. The backup power source control circuit is configured to control a current path from the backup power source to the output based at least in part on a voltage applied to the input. | 12-22-2011 |
| 20110310690 | VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF - A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator. | 12-22-2011 |
| 20120002498 | NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM - Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized. | 01-05-2012 |
| 20120014201 | DUAL RAIL MEMORY - A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column. | 01-19-2012 |
| 20120033520 | MEMORY WITH LOW VOLTAGE MODE OPERATION - A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells. | 02-09-2012 |
| 20120033521 | Semiconductor apparatus and its control method - Semiconductor apparatus includes first power supply line and second power supply line, first sub power supply line, first switch circuit, first logic circuit and first control circuit. First switch circuit is disposed between first power supply line and first sub power supply line, and controlled based on first signal. First logic circuit is disposed between first sub power supply line and second power supply line and comprises first input node and second input node receiving second signal and third signal respectively, and output node. First logic circuit outputs an active voltage associated with a logical level of second signal to output node in active state, and outputs a standby voltage associated with a voltage of second power supply line to output node regardless of the logical level of second signal in non-active state. First control circuit generates third signal based on first signal and fourth signal independent of first signal, and letting first logic circuit transit from non-active state to active state by providing third signal to second input node of first logic circuit. | 02-09-2012 |
| 20120044779 | DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY - A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation. | 02-23-2012 |
| 20120063254 | Voltage Regulator for Memory - A voltage regulator includes a first transistor, a second transistor, a third transistor, a feedback unit, a comparison unit, a first control unit and a second control unit. The first transistor is controlled by the feedback unit and the comparison unit, for stabilizing the voltage of the output node. When the first control unit turns on the second transistor, the voltage of the output node rises. When the first control unit turns off the second transistor, it triggers the second control unit turning on the third transistor, so the first transistor is turned on completely. Therefore, when the third transistor is turned off, the first transistor can be controlled by the feedback unit and the comparison unit for stabilizing the voltage of the output node. | 03-15-2012 |
| 20120081987 | SUPPLY VOLTAGE DISTRIBUTION SYSTEM WITH REDUCED RESISTANCE FOR SEMICONDUCTOR DEVICES - A supply voltage distribution system for distributing a supply voltage through a semiconductor device, the supply voltage distribution system comprising:
| 04-05-2012 |
| 20120087196 | GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE - The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected. | 04-12-2012 |
| 20120087197 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex an output signal of the voltage sensing unit and provide a skew control signal; and an internal voltage regulation unit configured to provide an internal voltage by regulating an internal bias voltage in response to the skew control signal. | 04-12-2012 |
| 20120087198 | SEMICONDUCTOR MEMORY DEVICE WITH ADJUSTABLE SELECTED WORK LINE POTENTIAL UNDER LOW VOLTAGE CONDITION - A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage. | 04-12-2012 |
| 20120099392 | STORAGE DEVICE INCLUDING RESET CIRCUIT AND METHOD OF RESETTING THEREOF - A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and a reset circuit to discharge an enable terminal of the voltage regulator or the power terminal of the memory device according to a change of the external voltage. | 04-26-2012 |
| 20120106284 | MEMORY POWER SUPPLY CIRCUIT - A memory power supply circuit includes a memory module, a micro control unit (MCU), a phase switch circuit, and a multi-phase pulse-width modulation (PWM) controller. The MCU is operable to determine required current to be supplied to the memory module and output corresponding phase switch signals to the phase switch circuit. The PWM controller includes a number of phase pins connected to the phase switch circuit. The phase switch circuit controls enable states of the phase pins of the PWM controller according to the phase switch signals. | 05-03-2012 |
| 20120106285 | CIRCUITS AND METHODS FOR REDUCING MINIMUM SUPPLY FOR REGISTER FILE CELLS - A register file employing a shared supply structure to improve the minimum supply voltage. | 05-03-2012 |
| 20120113737 | ELECTRONIC DEVICE AND MEMORY DEVICE OF CURRENT COMPENSATION - An electronic device includes a functional unit and a current compensation unit. The functional unit operates based on a power supplied by an external host through power supply lines and generates a control signal based on an amount of power consumption of the functional unit. The current compensation unit compensates a change in a power supply current based on the control signal, where the power supply current is a current flowing through the power supply lines. | 05-10-2012 |
| 20120113738 | Memory Device Having Multiple Power Modes - A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command. | 05-10-2012 |
| 20120134228 | CHARGE PUMP CONTROL SCHEME FOR MEMORY WORD LINE - A memory includes a word line, a charge pump coupled to the word line, and a charge pump control circuit coupled to the charge pump. The charge pump control circuit is configured to turn on the charge pump if the word line voltage is lower than a first threshold voltage and turn off the charge pump if the word line voltage is higher than a second threshold voltage. | 05-31-2012 |
| 20120155207 | SEMICONDUCTOR DEVICE GENERATING INTERNAL VOLTAGE - Such a device is disclosed that includes an internal voltage generating circuit generating an internal voltage by lowering an external potential and supplying the generated internal voltage to a power supply line, a switch being connected between a grounding wire to which a ground voltage is supplied and the power supply line, and a one-shot signal generating unit controlling turning on and off of the switch, wherein the one-shot signal generating unit brings the switch into conduction synchronously with start of generating the internal voltage by the internal voltage generating circuit. | 06-21-2012 |
| 20120155208 | NEGATIVE HIGH VOLTAGE GENERATOR AND NON-VOLATILE MEMORY DEVICE INCLUDING NEGATIVE HIGH VOLTAGE GENERATOR - A negative high voltage generator includes a charge providing unit and a voltage conversion unit. The charge providing unit is configured to periodically output a predetermined amount of positive charges received from a supply voltage. The voltage conversion unit is configured to store the positive charges and to discharge the stored positive charges to a ground voltage to generate a negative high voltage having a magnitude larger than a magnitude of the supply voltage. | 06-21-2012 |
| 20120163112 | SEMICONDUCTOR STORAGE SYSTEM CAPABLE OF SUPPRESSING PEAK CURRENT - According to one embodiment, in a semiconductor storage system, the power supply wiring is connected to a first semiconductor storage device, and second semiconductor storage device as a common connection, and supplies power to the first and second semiconductor storage devices. A voltage detection circuit is provided in each of the first and second semiconductor storage devices. Each of the voltage detection circuits detects a power supply voltage of the power supply wiring. A control circuit is provided in each of the first and second semiconductor storage devices. When lowering of the power supply voltage is detected by a corresponding voltage detection circuit, each of the control circuits does not shift the operation of the first or second semiconductor storage device to the next operation until the power supply voltage is restored. | 06-28-2012 |
| 20120170397 | SENSOR NODE ENABLED TO MANAGE POWER INDIVIDUALLY - A sensor node is provided. The sensor node regulates the power supplied to memories of a memory unit individually and the power supplied to a transmitter and a receiver of an RF transceiver individually. Thus, the sensor node can minimize its power consumption. | 07-05-2012 |
| 20120176854 | STATE-MONITORING MEMORY ELEMENT - Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be disturbed in different locations on the IC for better coverage. | 07-12-2012 |
| 20120176855 | CARD AND HOST DEVICE - A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern. | 07-12-2012 |
| 20120182820 | LOCAL POWER DOMAINS FOR MEMORY SECTIONS OF AN ARRAY OF MEMORY - Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses. | 07-19-2012 |
| 20120206989 | SEMICONDUCTOR MEMORY DEVICES WITH A POWER SUPPLY - A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage level that is reinforced as compared with a voltage level of the driving voltage. The load driver drives a load based on the driving voltage and the driving signal. | 08-16-2012 |
| 20120213027 | METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY - A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's. | 08-23-2012 |
| 20120218849 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a memory cell array including a plurality of chips, a control circuit configured to control an internal operation of the memory cell array, a power circuit configured to supply power to the control circuit, and a mode setting circuit configured to output a flag signal for power supply control based on a mode register set command and data received through a data input/output pad, in response to a clock enable signal. | 08-30-2012 |
| 20120218850 | NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word line of the word lines and providing a first pass voltage to an unselected word line adjacent to the selected word line, sensing potential of the bit line by applying a second read voltage higher than the first read voltage to the selected word line and providing a second pass voltage lower than the first pass voltage to the unselected word line adjacent to the selected word line, and sensing potential of the bit line by applying a third read voltage higher than the second read voltage to the selected word line and providing a third pass voltage lower than the second pass voltage to the unselected word line adjacent to the selected word line. | 08-30-2012 |
| 20120230142 | TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS - Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell. | 09-13-2012 |
| 20120236672 | HIGH VOLTAGE GENERATING CIRCUIT AND METHOD OF OPERATING THE SAME - A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage pump circuit and a second clock signal driving the second high voltage pump circuit. The oscillator includes a first delay circuit configured to output the second clock signal by delaying the first clock signal by a first delay time. The first delay circuit is configured to adjust the first delay time according to a period of the first clock signal. | 09-20-2012 |
| 20120236673 | SEMICONDUCTOR DEVICE - Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate. | 09-20-2012 |
| 20120236674 | Circuit and Method for Operating a Circuit - A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section. | 09-20-2012 |
| 20120243362 | ADVANCED DETECTION OF MEMORY DEVICE REMOVAL, AND METHODS, DEVICES AND CONNECTORS - Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal. Alternatively, the connector may be configured to generate a signal that causes a host to terminate programming or erase operations prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position. | 09-27-2012 |
| 20120243363 | POWER LINE LAYOUT TECHNIQUES FOR INTEGRATED CIRCUITS HAVING MODULAR CELLS - An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block. | 09-27-2012 |
| 20120250443 | Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack - Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. | 10-04-2012 |
| 20120269022 | INTERNAL POWER SOURCE VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY AND METHOD FOR GENERATING INTERNAL POWER SOURCE VOLTAGE - An internal power source voltage generating circuit of a semiconductor memory and a corresponding method shorten an access delay upon transition of a data reading operation in an address period shorter than a prescribed minimum period to an operation in the prescribed minimum period. While a boosted voltage of an external power source voltage is supplied to the semiconductor memory as the internal power source voltage via an output line connected to one end of a condenser. A reference low potential is applied to the other end of the condenser and the external power source voltage is applied to the output line, thereby charging the condenser. If the internal power source voltage is lower than a threshold voltage, the internal power source voltage on the output line is boosted by applying the external power source voltage to the other end of the condenser. | 10-25-2012 |
| 20120281491 | DATA PROCESSING SYSTEM HAVING BROWN-OUT DETECTION CIRCUIT - A data processing system includes a brown-out detection circuit with a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal. | 11-08-2012 |
| 20120294105 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM COMPRISING THE SAME - According to an embodiment, a semiconductor device includes a power supply switch and a first regulator. One end of the power supply switch is connected to an input terminal. The other end of the power supply switch is connected to an output terminal. The first regulator includes a power supply terminal connected to the one end of the power supply switch, and a voltage output terminal connected to the other end of the power supply switch. The first regulator is configured to control a voltage of the voltage output terminal to approach a target voltage based on a voltage of the power supply terminal. The target voltage is switched to a first voltage or a second voltage. The first voltage is equal to or more than the voltage of the power supply terminal. The second voltage is lower than the voltage of the power supply terminal. | 11-22-2012 |
| 20120320699 | SEMICONDUCTOR DEVICE - A word driver drives a word line with a first power supply voltage and with a second power supply voltage which has a potential lower than the first power potential, respectively in a first time period and in a second time period following the first time period for activating the word line. | 12-20-2012 |
| 20120320700 | CURRENT LEAKAGE REDUCTION - This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell. | 12-20-2012 |
| 20120320701 | MULTI-CHANNEL MEMORY AND POWER SUPPLY-DRIVEN CHANNEL SELECTION - Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same. | 12-20-2012 |
| 20120327734 | SEMICONDUCTOR MEMORY, SYSTEM, AND METHOD OF OPERATING SEMICONDUCTOR MEMORY - A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of second signal lines in the memory cells, after the first selection unit starts operating; a first voltage generation unit generating a first power supply voltage supplied to the first selection unit; a second voltage generation unit generating a second power supply voltage supplied to the second selection unit, when a start-up signal is active; a switch short-circuiting first and second power supply lines, when a short-circuit signal is active; and a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal and the start-up signal after completion of access operations. | 12-27-2012 |
| 20130016578 | POWER SUPPLY SYSTEM FOR MEMORIESAANM WU; KANGAACI Shenzhen CityAACO CNAAGP WU; KANG Shenzhen City CNAANM TIAN; BOAACI Shenzhen CityAACO CNAAGP TIAN; BO Shenzhen City CN - A power supply system for memory modules includes a control unit and a voltage regulator. The control unit includes a basic input/output system (BIOS) and a control chip connected to the BIOS. The BIOS controls the control chip to output a control signal according to the number of the memory modules mounted in memory slots. The voltage regulator is connected to the control chip through first and second general purpose input/output (GPIO) buses. The voltage regulator receives the control signal from the control chip through the first and second GPIO buses and regulates power supply modes, to output different phase voltages to the memory modules mounted in the memory slots. | 01-17-2013 |
| 20130016579 | SEMICONDUCTOR DEVICE - A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units. | 01-17-2013 |
| 20130021865 | MEMORY MODULE AND POWER SUPPLY SYSTEM - A memory module includes a ground terminal, a power terminal, a voltage regulator down, and a storing unit. The power terminal and the ground terminal are connected to a power source that supplies a first direct voltage. The voltage regulator down is connected to the power terminal and configured for converting the first direct current voltage to a second direct current voltage. The storing unit is connected the voltage regulator down for storing data and reading or writing data when the storing unit receives the second direct current voltage. | 01-24-2013 |
| 20130028039 | POWER MANAGEMENT IN SEMICONDUCTOR MEMORY SYSTEM - A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device. | 01-31-2013 |
| 20130028040 | DUAL RAIL MEMORY - A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes. | 01-31-2013 |
| 20130033952 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a reference voltage generation unit configured to generate first and second reference voltages, wherein a level of the first reference voltage increases with decreasing internal temperature, and a level of the second reference voltage decreases with decreasing internal temperature; and a level control unit configured to control an internal voltage in response to the first and second reference voltages so as to decrease the absolute value of the internal voltage. | 02-07-2013 |
| 20130033953 | COMPUTER MOTHERBOARD AND VOLTAGE ADJUSTMENT CIRCUIT THEREOF - A voltage adjustment circuit includes a south bridge, a complex programmable logic device (CPLD), a power supply unit, a voltage conversion unit, and a resistance unit. The south bridge detects a type of a number of dynamic random access memories (DRAMs), and outputs a corresponding signal according to a detected result of the type of the DRAMs. The CPLD is connected to the south bridge to receive the signal, and outputs a corresponding control signal according to the signal. The voltage conversion unit is connected to the power supply unit and the DRAMs, and converts voltage output from the power supply unit into a stable voltage. The resistance unit is connected to the CPLD and the voltage conversion unit, and provides different resistance according to the control signal received from the CPLD, to adjust the voltage output from the voltage conversion unit to an operation voltage of the DRAMs. | 02-07-2013 |
| 20130064031 | Adaptive Read Wordline Voltage Boosting Apparatus and Method for Multi-Port SRAM - Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM. | 03-14-2013 |
| 20130107654 | SEMICONDUCTOR MEMORY APPARATUS, HIGH VOLTAGE GENERATION CIRCUIT, AND PROGRAM METHOD THEREOF | 05-02-2013 |
| 20130128683 | Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same - A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. | 05-23-2013 |
| 20130135954 | MEMORY CELL ARRAY LATCHUP PREVENTION - A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level. | 05-30-2013 |
| 20130135955 | MEMORY DEVICE INCLUDING A RETENTION VOLTAGE RESISTOR - A mechanism for providing retention mode voltage to a memory storage array includes a resistor coupled between a power supply and a power rail of the storage array. The power rail may distribute an operating current to the bit cells of the storage array. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device coupled between the power supply and the power rail, in parallel with the resistor, may convey operational current to the power rail from the power supply during operation in a normal mode. | 05-30-2013 |
| 20130141999 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits. | 06-06-2013 |
| 20130142000 | METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY - Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports. | 06-06-2013 |
| 20130148455 | FINE GRANULARITY POWER GATING - An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value. | 06-13-2013 |
| 20130148456 | VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION AND VOLTAGE REGULATING METHOD - Provided is a voltage supply circuit using a charge pump. The voltage supply circuit enhances charge pump output voltage fluctuation characteristics depending on load variation of a charge pump voltage generator (load regulation characteristics) when receiving an operation power supply voltage of the charge pump through a regulator. The voltage supply circuit is configured to feed back fluctuation of a charge pump output voltage to a charge pump voltage regulator. The fluctuation of the charge pump output voltage is compensated through fluctuation of an output voltage of the charge pump to active enhance the load regulation characteristics. | 06-13-2013 |
| 20130176806 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a first driving section configured to generate a pre-power-up signal by driving a first node to a first pull-up drivability or driving the first node to a first pull-down drivability in response to an internal voltage when not in an active mode, and a second driving section configured to generate the pre-power-up signal by driving the first node to a second pull-up drivability or driving the first node to a second pull-down drivability in response to the internal voltage in the active mode. The first pull-up drivability is larger than the second pull-up drivability, and the first pull-down drivability is smaller than the second pull-down drivability. | 07-11-2013 |
| 20130182523 | ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR - An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies. | 07-18-2013 |
| 20130194886 | PHYSICAL UNCLONABLE FUNCTION WITH IMPROVED START-UP BEHAVIOR - An electric physical unclonable function (PUF) ( | 08-01-2013 |
| 20130208555 | DEVICES HAVING BIAS TEMPERATURE INSTABILITY COMPENSATION - Methods are provided for operating a memory device. An exemplary method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current. An exemplary memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element to adjust the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element. | 08-15-2013 |
| 20130223174 | BOOSTING SUPPLY VOLTAGE - A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is caused to rise towards a first power supply voltage value, and when the first power supply line reaches a first predetermined voltage value, the first power supply is caused to rise above the first power supply voltage value; and 2) a second power supply line of the sense amplifier is caused to fall towards a second power supply voltage value, and when the second power supply line reaches a second predetermined voltage value, the second power supply line is caused to fall below the second power supply voltage value. | 08-29-2013 |
| 20130235688 | LOOK-UP TABLE CIRCUIT - One embodiment provides a look-up table circuit, including: 2 | 09-12-2013 |
| 20130242682 | MEMORY DEVICE POWER CONTROL - The apparatus described herein may comprise a first set of transistors, including a first transistor and a second transistor, and a second set of transistors, including a third transistor and a fourth transistor. Gates of the first and second transistors may be coupled to a first signal and a second signal, respectively, each indicating whether a corresponding one of a first supply voltage and a second supply voltage reaches a first threshold voltage or a second threshold voltage to power on a first circuit or a second circuit of a memory device. Gates of the third and fourth transistors may be coupled to a first inverted version of the first signal and a second inverted version of the second signal, respectively. An outcome signal of the second set of transistors may indicate a power-on state of the memory device responsive to power states of the first and second signals. | 09-19-2013 |
| 20130242683 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITORS FOR STABILIZING OPERATION VOLTAGE - Disclosed herein is a device that includes first and second memory cell arrays each including a plurality of memory cells, a first power supply line supplying a first voltage to the first memory cell array, a second power supply line supplying the first voltage to the second memory cell array, and a first capacitive element. The first capacitive element is electrically connected to the first power supply line and is electrically disconnected from the second power supply line when the first memory cell array is activated and the second memory cell array is deactivated. The first capacitive element is electrically connected to the second power supply line and is electrically disconnected from the first power supply line when the second memory cell array is activated and the first memory cell array is deactivated. | 09-19-2013 |
| 20130258796 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a stacked layer memory block and associated peripheral circuits in stacked layer arrangements. Booster circuits in a variety of stacked layer arrangements are described. The booster circuit possesses plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive the first clock signal on one end, and the other ends are each connected to one end of different rectifier cells. The first capacitor is composed of capacities between plural first conductive layers that are arrayed with a set pitch perpendicularly to the substrate. One of the either even numbered or odd numbered first conductive layers is supplied with a first clock signal. The other of the either even numbered or odd numbered first conductive layers that line perpendicularly to the substrate is, individually, connected to one end of different rectifier cells. | 10-03-2013 |
| 20130265840 | SEMICONDUCTOR DEVICE HAVING AUXILIARY POWER-SUPPLY WIRING - Disclosed herein is a semiconductor device that includes a signal wiring arranged on a first layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block and produce a free space above the first circuit block, the signal wiring being electrically connected to the first circuit block, a power-supply wiring arranged on a second layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block, the power-supply wiring supplying an operating voltage to the first circuit block and an auxiliary power-supply wiring being configured to enhance the operating voltage supplied by the power supply line, and the auxiliary power-supply wiring being formed in the free space produced by the arrangement of the signal wiring. | 10-10-2013 |
| 20130286761 | SWITCHING CIRCUIT - A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second transistor is turned on based on a second control signal delayed by a time delay from the first control signal. A second terminal of the first transistor is coupled with a second terminal of the second transistor. The second control signal is used to control a first input signal of a logic device. The logic device receives a second input signal inversed from the first control signal. An output signal of the logic device is used to control a first terminal of the second transistor. | 10-31-2013 |
| 20130308407 | CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DISTURBS IN SEMICONDUCTOR MEMORIES - A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level. | 11-21-2013 |
| 20130308408 | INPUT BUFFER - An input buffer includes a first buffer circuit to amplify a difference between a first input signal and a second input signal; a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal; and a detector to compare the common mode output signal with a reference output signal and to control the first and second buffer circuits according to the comparison result such that a level of the common mode output signal coincides with a level of the reference output signal. | 11-21-2013 |
| 20130308409 | INTEGRATED CIRCUIT DEVICE, POWER MANAGEMENT MODULE AND METHOD FOR PROVIDING POWER MANAGEMENT - An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant. | 11-21-2013 |
| 20130322197 | POWER MANAGEMENT IN AN ELECTRONIC SYSTEM THROUGH REDUCING ENERGY USAGE OF A BATTERY AND/OR CONTROLLING AN OUTPUT POWER OF AN AMPLIFIER THEREOF - A method includes forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array including N amplifier stages in parallel to each other, with N>1. The method also includes coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array, and controlling an output power of the power control circuit by switching one or more appropriate gate switches of the gate switch array to apply an input signal from the buffer stage to a corresponding one or more amplifier stages coupled to the one or more appropriate gate switches such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on. | 12-05-2013 |
| 20130336080 | TIMING-DRIFT CALIBRATION - The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device. | 12-19-2013 |
| 20130343143 | SEMICONDUCTOR DEVICE HAVING LINE SELF-BOOSTING SCHEME - A semiconductor device includes: a plurality of target lines to be driven; a plurality of target line drivers configured to drive the corresponding target lines in a logic level corresponding to a plurality of target line selection signals; a plurality of booster enable units configured to generate a booster enable signal by sensing whether a group of target lines that is obtained by grouping the target lines by a predetermined number is enabled or not; and a plurality of self-boosters configured to boost corresponding target lines by sensing levels of the corresponding target lines in response to the booster enable signal. | 12-26-2013 |
| 20140003179 | REDUCED-NOISE REFERENCE VOLTAGE PLATFORM FOR A VOLTAGE CONVERTER DEVICE | 01-02-2014 |
| 20140003180 | STORAGE DEVICE, CONNECTION DEVICE, AND STORAGE CONTROL METHOD | 01-02-2014 |
| 20140003181 | MEMORY CELL WITH IMPROVED WRITE MARGIN | 01-02-2014 |
| 20140016425 | VOLTAGE REGULATOR, VOLTAGE REGULATING SYSTEM, MEMORY CHIP, AND MEMORY DEVICE - A voltage regulator comprises a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from an amplifier in a first mode to generate a first current, and outputs the first current to the output terminal; and a second transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from the amplifier in a second mode to generate a second current different from the first current, and outputs the second current to the output terminal, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode. | 01-16-2014 |
| 20140029368 | METHOD AND APPARATUS FOR INCREASING YIELD - Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement. | 01-30-2014 |
| 20140036611 | VOLTAGE GENERATING SYSTEM AND MEMORY DEVICE USING THE SAME - A voltage generating system and a memory device using the same are disclosed. The voltage generating system includes an internal voltage regulator, configured to supply a current to pull an internal supply voltage to a regulated level and maintain at the regulated level; and a substrate-bias controlled selector, configured to receive a regulator power-up mode signal, a regulating mode signal and a substrate-bias voltage of a substrate, and control the internal voltage regulator such that when the substrate-bias voltage is smaller than a predetermined voltage, the internal voltage regulator powers up and operates normally by respectively taking the regulator power-up mode signal and the regulating mode signal into consideration, and when the substrate-bias voltage is larger than or equal to the predetermined voltage, the internal voltage regulator is disabled. The predetermined voltage is smaller than or equal to a forward voltage of a p-n junction formed with the substrate. | 02-06-2014 |
| 20140064010 | APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES - An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided. | 03-06-2014 |
| 20140071781 | VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY - A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array. | 03-13-2014 |
| 20140092700 | FINE GRANULARITY POWER GATING - Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an adjacent row in the word line group. A row on a boundary of a word line group has a power supply line shared by a row on a boundary of an adjacent word line group. All power supply lines in a word line group are at a full power voltage in response to one of the rows in the word line group being selected by a word line. Most power supply lines in an adjacent word line group are at a full power voltage. All power supply lines in other word line groups are at a power-gated voltage. | 04-03-2014 |
| 20140098624 | Supply Power Dependent Controllable Write Throughput for Memory Applications - Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput. | 04-10-2014 |
| 20140112088 | CONTROL CIRCUIT, MEMORY DEVICE AND VOLTAGE CONTROL METHOD THEREOF - A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal. | 04-24-2014 |
| 20140133256 | VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal. | 05-15-2014 |
| 20140140161 | NON-VOLATILE MEMORY ROBUST START-UP USING ANALOG-TO-DIGITAL CONVERTER - In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it. | 05-22-2014 |
| 20140146629 | VOLTAGE BATTERY - A circuit includes a voltage generating circuit and a voltage keeper circuit. The voltage generating circuit includes a first node. The voltage keeper circuit includes a second node and a third node. The first node is coupled with the second node. The voltage generating circuit is configured to generate a voltage value at the first node and the second node to maintain the third node at a particular third node voltage. | 05-29-2014 |
| 20140146630 | DATA TRANSFER ACROSS POWER DOMAINS - The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers. | 05-29-2014 |
| 20140153351 | MEMORY DEVICE POWER CONTROL - The apparatus described herein may comprise a first set of transistors, including a first transistor and a second transistor, and a second set of transistors, including a third transistor and a fourth transistor. Gates of the first and second transistors may be coupled to a first signal and a second signal, respectively, each indicating whether a corresponding one of a first supply voltage and a second supply voltage reaches a first threshold voltage or a second threshold voltage to power on a first circuit or a second circuit of a memory device. Gates of the third and fourth transistors may be coupled to a first inverted version of the first signal and a second inverted version of the second signal, respectively. An outcome signal of the second set of transistors may indicate a power-on state of the memory device responsive to power states of the first and second signals. | 06-05-2014 |
| 20140160874 | POWER MANAGEMENT IN SEMICONDUCTOR MEMORY SYSTEM - A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device. | 06-12-2014 |
| 20140169115 | AUXILIARY POWER DEVICE AND USER SYSTEM INCLUDING THE SAME - A user system is provided which includes a storage device and an auxiliary power device configured to supply a power to the storage device, wherein the auxiliary power device includes a first one direction device configured to supply a supply voltage from an external power supply to the storage device, a charging unit configured to be charged by the external power supply, a second one direction device configured to selectively supply an output voltage of the charging unit to the storage device, a voltage detector configured to detect a level of the output voltage of the charging unit and to output a first control signal to the storage device, and a switching unit connected between the charging unit and the second one direction device and configured to operate in response to a second control signal from the storage device. | 06-19-2014 |
| 20140169116 | CIRCUITRY AND METHODS MINIMIZING OUTPUT SWITCHING NOISE THROUGH SPLIT-LEVEL SIGNALING AND BUS DIVISION ENABLED BY A THIRD POWER SUPPLY - Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. | 06-19-2014 |
| 20140192607 | ADAPTIVE VOLTAGE INPUT TO A CHARGE PUMP - A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power profile of the memory device, which indicates a voltage level that provides good efficiency for the charge pump, and is within maximum levels for the memory device. The voltage can be higher than a nominal voltage indicated for the memory device in a specification. | 07-10-2014 |
| 20140198598 | SYSTEM AND METHOD OF PERFORMING POWER ON RESET FOR MEMORY ARRAY CIRCUITS - The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus. | 07-17-2014 |
| 20140204695 | METHOD AND APPARATUS FOR INCREASING YIELD - Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement. | 07-24-2014 |
| 20140233337 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device includes a memory cell array; and a high voltage generator arranged to generate a high voltage to be supplied to the memory cell array. The high voltage generator includes a pump unit block having a plurality of pump units supplied with an external voltage and at least one of the pumps is engaged in pumping the external voltage to a higher, output, voltage, at a steady clock rate. The number of pumps engaged in pumping is increased until a predetermined period has elapsed. The rate at which the number of pumps is increased depends upon the value of the external voltage. | 08-21-2014 |
| 20140241095 | Semiconductor System - To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced. | 08-28-2014 |
| 20140247681 | WIRING CONFIGURATION OF A BUS SYSTEM AND POWER WIRES IN A MEMORY CHIP - Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip. | 09-04-2014 |
| 20140254299 | ROBUST MEMORY START-UP USING CLOCK COUNTER - In accordance with at least one embodiment, a clock counter on a system (for example, a system-on-a-chip (SOC) or other system) is utilized to count a number of a clock edges of a memory clock within a predefined time based on a predetermined system clock frequency and, therefore, to determine whether the memory clock for a memory array (for example, a non-volatile memory (NVM) array or other memory array) is correct or not. The system is directed to wait until the count is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the system such that the application can react to it. | 09-11-2014 |
| 20140269136 | POWER SUPPLY CIRCUIT AND SEMICONDUCTOR DEVICE - An output transistor coupled between an input terminal where an input voltage is input and an output terminal where an output voltage is output; an error amplifier configured to generate a first error signal and a second error signal based on a voltage in accordance with the output voltage and a reference voltage, and to output the first error signal to a gate terminal of the output transistor; an anti-overshoot circuit coupled to the output terminal and controlled by the second error signal; an output transistor control part configured to add a control signal based on a first current in accordance with an AC component of the output voltage to the first error signal; and a sensitivity adjustment part configured to decrease the first current based on the second error signal when the output voltage is higher than a certain voltage. | 09-18-2014 |
| 20140269137 | CANARY BASED SRAM ADAPTIVE VOLTAGE SCALING (AVS) ARCHITECTURE AND CANARY CELLS FOR THE SAME - A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank. | 09-18-2014 |
| 20140347946 | VOLTAGE REGULATOR - The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises: | 11-27-2014 |
| 20140347947 | APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES - An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided. | 11-27-2014 |
| 20140369147 | POWER CONVERTER FOR A MEMORY MODULE - An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage. | 12-18-2014 |
| 20150016205 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a first input section into which a first input signal is inputted, a second input section into which a second input signal is inputted, an output generation circuit which is connected to the first and second input sections and generates an output signal based on the input signals, an output section which outputs the output signal, and a current source which is connected to connection nodes between the input sections and the output generation circuit. | 01-15-2015 |
| 20150023122 | METHOD AND APPARATUS FOR MEMORY POWER AND/OR AREA REDUCTION - A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V | 01-22-2015 |
| 20150029805 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner. | 01-29-2015 |
| 20150029806 | VOLTAGE CONTROL INTEGRATED CIRCUIT DEVICES - Voltage control in integrated circuits include a first voltage divider coupled to receive a reference voltage and having an output providing an adjusted reference voltage; an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback voltage, and an output; a voltage generation circuit responsive to the output of the operational amplifier and having an output providing an output voltage; and a second voltage divider coupled to receive the output voltage and having an output providing the feedback voltage. The first voltage divider is responsive to first control signals to adjust a voltage level of the adjusted reference voltage. The second voltage divider is responsive to second control signals to adjust a voltage level of the feedback voltage. | 01-29-2015 |
| 20150029807 | MEMORY DEVICE AND METHOD FOR PUTTING A MEMORY CELL INTO A STATE WITH A REDUCED LEAKAGE CURRENT CONSUMPTION - In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved. | 01-29-2015 |
| 20150036446 | DUAL SUPPLY MEMORY - According to one general aspect, an apparatus may include a first power supply configured to generate a first power signal having one of a plurality of voltages, and a second power supply configured to generate a second power signal that includes a voltage equal to or higher than a voltage of the first power signal. The apparatus may include a first electrical circuit configured to be powered by the first power supply. The apparatus may also include a power mode controller configured to: determine the voltage of the first power signal during the next power state, and generate a selector control signal based upon the voltage of the first power signal. The apparatus may also include a power supply selector configured to dynamically electrically couple a second electrical circuit with either the first power signal or the second power signal, based upon the selector control signal. | 02-05-2015 |
| 20150036447 | FLIP-FLOP WITH ZERO-DELAY BYPASS MUX - Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal. | 02-05-2015 |
| 20150063051 | LOW POWER PROTECTION CIRCUIT - The present invention provides the low power protection circuit including a first voltage detector, a pulse generating circuit, a SR latch, and an output logic operation circuit. The low power protection circuit is adapted for a dynamic random access memory (DRAM) with dual operating voltages. The first voltage detector generates a high-voltage pump enable signal by detecting a voltage level of the power-up signal. The pulse generating circuit generates a power-up pulse according to the power-up signal. The SR latch receives the power-up pulse, the high-voltage pump enable signal and an inverted power-up signal, and generates an output signal. The second voltage detector generates a low-voltage pump enable signal by detecting a voltage level of the output signal. The output logic operation circuit generates a pump enable signal according to the low-voltage pump enable signal and the high-voltage pump enable signal. | 03-05-2015 |
| 20150085596 | SEMICONDUCTOR DEVICES HAVING MULTI-CHANNEL REGIONS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The semiconductor device includes a first channel region suitable for including a first pad region and a first core region and receiving a first power signal through a first power line, a second channel region suitable for including a second pad region and a second core region and receiving the first power signal through a second power line, and a switch unit suitable for electrically disconnecting the second power line from a first power stabilization unit if a predetermined operation of the first channel region is performed and electrically disconnecting the first power line from the first power stabilization unit if the predetermined operation of the second channel region is performed. | 03-26-2015 |
| 20150098290 | METHODS CIRCUITS APPARATUSES AND SYSTEMS FOR PROVIDING CURRENT TO A NON-VOLATILE MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICES PRODUCED ACCORDINGLY - Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage. | 04-09-2015 |
| 20150103611 | METHOD FOR DRIVING ARITHMETIC PROCESSING UNIT - In a memory cell including an inverter, a capacitor is provided. When the memory cell is not accessed, data stored in the memory cell is copied to the capacitor and then power supply to the inverter is stopped. When the memory cell needs to be accessed, the data is returned from the capacitor to the inverter. In this manner, power consumption when the memory cell is not accessed is reduced. Furthermore, in a memory device including a plurality of such memory cells, backup of the first memory cell and backup of the second memory cell are performed at different timings. Recovery of the first memory cell and recovery of the second memory cell are also performed at different timings. Consequently, power required for backup or recovery can be distributed. Other embodiments may be described and claimed. | 04-16-2015 |
| 20150109873 | REGULATED POWER GATING FOR GROWABLE MEMORY - A circuit for an integrated circuit power gating system includes a header device connected to a bank of a segmented memory array. The circuit is structured and arranged to: apply a ground input to a gate of the header device to activate the bank, and apply a regulated voltage to the gate of the header device to deactivate the bank. The circuit also includes a precharge circuit that charges the gate of the header device to a precharge voltage that is greater than ground and less than the regulated voltage | 04-23-2015 |
| 20150124546 | VOLTAGE REGULATOR AND APPARATUS FOR CONTROLLING BIAS CURRENT - A voltage regulator includes: a comparator configured to compare a feedback voltage with a reference voltage to output an enable signal and operate based on a bias current; a pass transistor turned on according to the enable signal and configured to output an external power voltage as an output voltage; a voltage distribution circuit configured to distribute and output the output voltage to an input terminal of the comparator; and a bias current control unit configured to control an amount of the bias current supplied to the comparator based on the output voltage. | 05-07-2015 |
| 20150124547 | SEMICONDUCTOR DEVICE - An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of the transistor is connected to a bit line controlling circuit connected to a battery. The minimum potential of the bit line is set higher than that of a word line. When power from an external power supply is interrupted, the bit line is cut off by the transistor, ensuring prevention of outflow of charge in the bit line. The potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor, resulting in an absolute off-state; thus, data can be retained. Other embodiments are disclosed. | 05-07-2015 |
| 20150124548 | SWITCHING CIRCUIT - A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor. | 05-07-2015 |
| 20150318026 | Integrated Circuit Device Body Bias Circuits and Methods - A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well. | 11-05-2015 |
| 20150323951 | VOLTAGE PROVIDING CIRCUIT - A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage. | 11-12-2015 |
| 20150338863 | DEVICE HAVING INTERNAL VOLTAGE GENERATING CIRCUIT - A device includes an amplifying circuit having first and second input terminals and an output terminal, a ground terminal, a variable resistance circuit, and a resistance selecting circuit coupled in series to the variable resistance circuit between the output terminal and the ground terminal. The resistance selecting circuit includes a first node coupled to the second input terminal, a plurality of resistors coupled in series to each other and a plurality of gate circuits each coupled between the first node and one end of a corresponding one of the resistors. | 11-26-2015 |
| 20150348599 | PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY - The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information. | 12-03-2015 |
| 20150380065 | DEEP SLEEP WAKEUP OF MULTI-BANK MEMORY - A deep sleep wakeup signal is received at a first memory bank. A first gated memory array supply voltage is increased in response to the receiving the deep sleep wakeup signal at the first memory bank. The first memory array supply voltage is applied to a first memory array. The deep sleep wakeup signal is forwarded to a second memory bank in response to determining the first gated memory array supply voltage has reached a specified voltage. | 12-31-2015 |
| 20160005441 | CHARGE PUMP SYSTEM AND ASSOCIATED CONTROL METHOD FOR MEMORY CELL ARRAY - A charge pump system includes a logic circuit, a signal processing circuit, a charge pump circuit, a switching circuit, a first controllable discharge path, and a second controllable discharge path. The logic circuit receives a program enabling signal and generates a first control signal. The signal processing circuit receives a pump enabling signal, and generates a second control signal and a third control signal. The charge pump circuit receives the third control signal and generates an output signal. The switching circuit has a control terminal receiving the third control signal, a first terminal connected with the output terminal of the charge pump circuit, and a second terminal connected with a reservoir capacitor. The first controllable discharge path receives the first control signal, and the second controllable discharge path receives the second control signal. | 01-07-2016 |
| 20160012866 | SEMICONDUCTOR MEMORY APPARATUS | 01-14-2016 |
| 20160012867 | SYSTEM AND METHOD FOR AUTOMATIC DETECTION OF POWER UP FOR A DUAL-RAIL CIRCUIT | 01-14-2016 |
| 20160043639 | SEMICONDUCTOR DEVICE - A semiconductor device includes a voltage hold circuit that raises a second boosted voltage with rise of an output voltage of a booster circuit that generates a first boosted voltage and then maintains the second boosted voltage at a point when the output voltage reaches a hold voltage level after that, and a first switch that short-circuits a first output terminal through which the first boosted voltage is output and a second output terminal through which the second boosted voltage is output until the output voltage reaches the hold voltage level. | 02-11-2016 |
| 20160049177 | MEMORY SYSTEM, STORAGE SYSTEM - According to one embodiment, a memory system includes a power supply circuit. The power supply circuit includes a first capacitor circuit which applies a voltage to a nonvolatile memory and a memory controller, and a second capacitor circuit which adds a further voltage to the voltage applied by the first capacitor circuit, when the voltage applied by the first capacitor circuit is less than a set value. | 02-18-2016 |
| 20160064042 | SELECTING A VOLTAGE SENSE LINE THAT MAXIMIZES MEMORY MARGIN - A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair. | 03-03-2016 |
| 20160064043 | SELECTING A VOLTAGE SENSE LINE THAT MAXIMIZES MEMORY MARGIN - A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes sequentially passing a voltage signal from each of the voltage sense line pairs to the voltage feedback line, and, for each voltage sense line pair, calculating a memory margin of the memory system based on memory operation while regulating voltage to the memory system responsive to the voltage signal from the voltage sense line pair. Still further, the method includes identifying the voltage sense line pair that provides the greatest memory margin, and then regulating voltage to the memory system responsive to the identified voltage sense line pair. | 03-03-2016 |
| 20160071565 | Memory Circuits and a Method for Forming a Memory Circuit - A memory circuit includes a memory element which includes a first electrode layer including lithium. The memory element further includes a second electrode layer and a solid-state electrolyte layer arranged between the first electrode layer and the second electrode layer. The memory circuit also includes a memory access circuit configured to determine a memory state of the memory element. | 03-10-2016 |
| 20160099028 | INTEGRATED CIRCUIT WITH INDEPENDENT PROGRAMMABILITY - An integrated circuit includes circuitry performing memory operations. The power from only one of a first power lead and a second power lead is sufficient for the circuitry to operate. A package encasing the integrated circuit. Leads on the package electrically couple power and data from an exterior of the package to the integrated circuit encased by the package, including the first power lead, the second power lead, and a ground lead. An isolation circuit electrically couples the circuitry to the first power lead but not the second lead at a first time, and electrically couples the circuitry to the second power lead but not the first power lead at a second time. | 04-07-2016 |
| 20160111134 | POWER PATH CONTROLLER OF A SYSTEM-ON-CHIP - A power path controller included in a system-on-chip (SoC) is provided. The power path controller is coupled to a first power source and a second power source. The power path controller includes a first switch located between the first power source and a memory core included in the SoC, a second switch located between the second power source and the memory core, a comparator configured to compare a first power supply voltage supplied from the first power source with a second power supply voltage supplied from the second power source, and a switch controller configured to selectively activate the first switch or the second switch according to a comparison result of the comparator. | 04-21-2016 |
| 20160125923 | MULTI-CHANNEL MEMORY SYSTEM USING ASYMMETRIC CHANNEL FREQUENCY SCALING AND RELATED POWER MANAGEMENT METHOD - A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency. | 05-05-2016 |
| 20160133302 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device may include a power-on reset signal generation unit suitable for receiving a power supply voltage, and generating a power-on reset signal that changes based on the power supply voltage, and a discharging signal generation unit suitable for generating a discharging signal for discharging a word line to be activated earlier than an activation timing of the power-on reset signal when the power supply voltage decreases. | 05-12-2016 |
| 20160134276 | SWITCH CIRCUIT FOR VOLTAGE - A switch circuit for voltage includes a power supply module, a platform controller hub (PCH), a basic input-output system (BIOS), and a regulation module. An output pin of the power supply module is coupled to a memory to supply power for the memory. When a type of the memory is changed, an output signal of the PCH is controlled by the BIOS, and the regulation module switches the resistors coupled to a feedback pin of the power supply module, for changing voltage signals output from the power supply module. | 05-12-2016 |
| 20160141003 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array disposed on the semiconductor substrate, a capacitor and a control circuit. The memory cell array includes a plurality of memory cells. The control circuit supplies a voltage to the memory cell array. The memory cell array includes a first conductive body disposed in a first region on the semiconductor substrate. The first conductive body extends in a first direction intersecting with a surface of the substrate. The capacitor includes first and second electrodes disposed in a second region different from the first region on the semiconductor substrate. The electrodes each include a second conductive body extending in the first direction. The first conductive body and the second conductive body include an identical material. | 05-19-2016 |
| 20160141005 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DRIVING THE SAME - Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, Each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal. | 05-19-2016 |
| 20160141007 | METHOD FOR CONTROLLING AN INTERNAL SUPPLY VOLTAGE BASED ON A CLOCK FREQUENCY OF AN EXTERNAL CLOCK SIGNAL AND A LOOK-UP TABLE - A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal. | 05-19-2016 |
| 20160141015 | MEMORY DEVICE INCLUDING POWER-UP CONTROL CIRCUIT, AND MEMORY SYSTEM HAVING THE SAME - A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level. | 05-19-2016 |
| 20160161962 | POWER DELIVERY TO THREE-DIMENSIONAL CHIPS - The present disclosure includes a three dimensional (3D) integrated device comprising a first die having a first supply line and a second die having a second supply line, a power header, and voltage selection logic. The power header is connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic is connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line. | 06-09-2016 |
| 20160161968 | SEMICONDUCTOR APPARATUS INCLUDING MULTICHIP PACKAGE - A semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master region. The slave region is configured to have a first threshold voltage smaller than an operation voltage and the master region is configured to have a second threshold voltage greater than the operation voltage. | 06-09-2016 |
| 20160180892 | SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP | 06-23-2016 |
| 20160180893 | POWER MANAGEMENT | 06-23-2016 |
| 20160203845 | POWER SOURCE FOR MEMORY CIRCUITRY | 07-14-2016 |
| 20160203846 | POWER SOURCE FOR MEMORY CIRCUITRY | 07-14-2016 |
| 20160254033 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM | 09-01-2016 |
| 20180025756 | ELECTRONIC DEVICE AND CONTROL METHOD WITH INSTRUCTION UNITS BASED ON A NUMBER OF POWER SUPPLY OFF OPERATIONS | 01-25-2018 |
| 20220137698 | Low Power State Implementation in a Power Management Circuit - A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint. | 05-05-2022 |
