| Entries |
| Document | Title | Date |
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| 20080212391 | LOW POWER MULTI-CHIP SEMICONDUCTOR MEMORY DEVICE AND CHIP ENABLE METHOD THEREOF - A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals. | 09-04-2008 |
| 20080219080 | Memory Device with Reduced Standby Power Consumption and Method for Operating Same - Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the memory cells; (b) comparing said actual value with a predetermined minimal value of the bit integrity parameter which takes into account possible variations in cell properties as a result of process variations; and (c) adjusting the standby voltage towards a more optimal value based on the result of the comparison in such a way that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value. The circuitry for measuring the bit integrity parameter preferably comprises a plurality of replica test cells which are added to the memory matrix. | 09-11-2008 |
| 20080225621 | STATIC RANDOM ACCESS MEMORY SYSTEM AND CONTROL METHOD FOR STATIC RANDOM ACCESS MEMORY SYSTEM - A static random access memory system used within a microprocessor includes a static random access memory array including a plurality of static random access memories, a storage unit configured to store a context ID used in the execution of a program or a process in association with an access pattern of the plurality of static random access memories in the execution of the program or the process, a search unit configured to, every time context switching occurs, search the storage unit for an access pattern that is associated with a context ID corresponding to a context ID of a program or a process to be executed after the context switching; and a power control unit configured to cause a static random access memory to be readable and writable on the basis of the access pattern of the plurality of static random access memories found by the search unit. | 09-18-2008 |
| 20080232185 | Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures - A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 09-25-2008 |
| 20080239857 | INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT - A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits | 10-02-2008 |
| 20080239858 | INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS - A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits. | 10-02-2008 |
| 20080247257 | MEMORY DATA INVERSION ARCHITECTURE FOR MINIMIZING POWER CONSUMPTION - A method for conserving power in a device is disclosed. The method generally includes the steps of (A) storing a plurality of data items in a plurality of bit cells in the device such that a majority of the bit cells holding the data items have a first logic state, wherein reading one of the bit cells having the first logic state consumes less power than reading one of the bit cells having a second logic state; (B) generating a polarity signal by analyzing the data items, the polarity signal indicating that the data items are stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition; and (C) driving at least one of the data items onto an external interface of the device in the normal condition during a read operation based on the polarity signal. | 10-09-2008 |
| 20080247258 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced. | 10-09-2008 |
| 20080253214 | Method and apparatus for incorporating DDR SDRAM into portable devices - A portable electronic device is provided which comprises (a) a memory device ( | 10-16-2008 |
| 20080253215 | Semiconductor memory circuit - The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized. | 10-16-2008 |
| 20080266998 | VOLTAGE BOOSTER AND MEMORY STRUCTURE USING THE SAME - A voltage booster and a memory structure using the same are provided. When a data storage unit in the memory structure is in normal operation, all voltage pumps in the voltage booster are turned on for boosting a supply voltage. However, when the data storage unit is in standby state, in the voltage booster, some voltage pumps are turned on while other voltage pumps are turned off, for boosting the supply voltage. Accordingly, the standby current and power consumption are reduced and the pump efficiency is improved. | 10-30-2008 |
| 20080279031 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for generating a second power supply voltage supplied to the second buffer in accordance with the operational timing of the second buffer. | 11-13-2008 |
| 20080298157 | MULTI-DIE PACKAGED DEVICE - A packaged multi die device includes at least one memory die. The one or more of the memory dice includes a memory function circuit configured to program or read data, a logic circuit configured to control the program operation and the read operation of the memory function circuit in accordance with an inputted operation command, and a power supplying circuit configured to provide a power corresponding to an operation mode to the memory function circuit, and apply an extra power to the logic circuit. | 12-04-2008 |
| 20090003114 | Apparatus and Method for Reducing Power Consumption Using Selective Power Gating - A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. An apparatus for reducing power consumption of a transistor-based circuit, the apparatus being connected to the transistor-based circuit, and is adapted to receive a low power mode indication, wherein the apparatus includes: means for determining whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and means for power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination. | 01-01-2009 |
| 20090003115 | POWER-GATING MEDIA DECODERS TO REDUCE POWER CONSUMPTION - Embodiments of a system that reduces power consumption by power-gating media decoders are described. During operation of the system, a decoder circuit receives encoded audio data and outputs corresponding decoded audio data to a memory, which is electrically coupled to the decoder circuit. Moreover, control logic, which is electrically coupled to the memory and the decoder circuit, provides commands to the memory and the decoder circuit that selectively disable at least a portion of the memory based on an amount of decoded audio data in the memory. | 01-01-2009 |
| 20090016140 | DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY - A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit. | 01-15-2009 |
| 20090016141 | Methods and Arrangements for Enhancing Power Management Systems in Integrated Circuits - Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit. | 01-15-2009 |
| 20090016142 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 01-15-2009 |
| 20090022004 | Charge recycling method and driving circuit and low power memory using the same - A driving circuit includes a first switch, a first driver and a second driver. The first switch has a first terminal coupled to a first voltage. The first driver includes a second switch and a third switch. The second switch has a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to a first capacitor. The third switch has a first terminal coupled to the second terminal of the second switch, and a second terminal coupled to a second voltage. The second driver includes a fourth switch and a fifth switch. The fourth switch has a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to a second capacitor. The fifth switch has a first terminal coupled to the second terminal of the fourth switch, and a second terminal coupled to the second voltage. | 01-22-2009 |
| 20090040858 | SRAM Device with a Power Saving Module Controlled by Word Line Signals - An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit. | 02-12-2009 |
| 20090091998 | POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY - A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated. | 04-09-2009 |
| 20090091999 | LEAKAGE OPTIMIZED MEMORY - A method of power optimization in a memory is disclosed. The method generally includes the steps of (A) dividing a plurality of bit cells in a design of the memory into (i) a plurality of first rows storing programmed data and (ii) at least one second row storing only padding data, (B) adjusting the design such that a second power consumption in each of the second rows is lower than a first power consumption in each of the first rows and (C) generating a file defining the design as adjusted. | 04-09-2009 |
| 20090103386 | SELECTIVELY-POWERED MEMORIES - Embodiments provide methods, apparatuses and systems including a plurality of memory cells configured to store bit values while being powered at a power-saving voltage lower than a normal-operation voltage during operation of a host apparatus, and power circuitry coupled to the plurality of memory cells. The power circuitry is configured to selectively power a first subset of the plurality of memory cells at the normal-operation voltage during operation of the host apparatus while concurrently powering a second subset of the plurality of memory cells at the power-saving voltage. The first and second subsets being different subsets of the memory cells. | 04-23-2009 |
| 20090129193 | ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES - An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device. | 05-21-2009 |
| 20090147612 | SYSTEM FOR CONTROLLING MEMORY POWER CONSUMPTION IN INTEGRATED DEVICES - A method for reducing power consumption in integrated devices is provided. The method comprising: locating a plurality of unused blocks of memory and a plurality of used blocks of memory in a memory device tlhrough a tracking mechanism; performing a refresh operation on the plurality of used blocks of memory at a constant frequency and suppressing the refresh operation on the plurality of unused blocks of memory through a memory controller; and suppressing error correction codes or parity errors on at least one of the plurality of unused blocks of memory when the at least one of the plurality of unused blocks of memory is accessed through the memory controller. | 06-11-2009 |
| 20090154281 | SEMICONDUCTOR DEVICE WITH REDUCED STANDBY FAILURES - A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode. | 06-18-2009 |
| 20090245008 | SYSTEM AND METHOD FOR PROVIDING VOLTAGE POWER GATING - A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state. | 10-01-2009 |
| 20090268542 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state. | 10-29-2009 |
| 20090285046 | METHOD TO REDUCE LEAKAGE OF A SRAM-ARRAY - A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode. | 11-19-2009 |
| 20090323452 | Dual Mode Memory System for Reducing Power Requirements During Memory Backup Transition - A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time. | 12-31-2009 |
| 20090323453 | Dynamic Power Saving Memory Architecture - A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and configured to control each of the word lines. The memory also includes multiplexers coupled to each of the interface ports. The multiplexers are configured to cause the selection of one of the sub-arrays based upon an address of a memory cell received at one or more of the interface ports. | 12-31-2009 |
| 20100002532 | ULTRA-LOW POWER HYBRID SUB-THRESHOLD CIRCUITS - The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. | 01-07-2010 |
| 20100046312 | Dynamic and Non-Volatile Random Access Memories with an Increased Stability of the MOS Memory Cells - In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices. | 02-25-2010 |
| 20100103760 | Memory Power Management Systems and Methods - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 04-29-2010 |
| 20100142306 | SEMICONDUCTOR MEMORY, SEMICONDUCTOR DEVICE, AND SYSTEM - A semiconductor memory includes: a voltage supply circuit which supplies a first voltage to a word line when an internal circuit is in a standby state, and supplies a second voltage higher than the first voltage to the word line when the internal circuit is in an active state; and a control circuit changes a drive capacity of the voltage supply circuit when changing from the standby state to the active state and the second voltage is supplied to the word line. | 06-10-2010 |
| 20100188922 | SEMICONDUCTOR STORAGE DEVICE AND ELECTRIC APPARATUS - A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros. | 07-29-2010 |
| 20100208539 | VOLTAGE REGULATOR FOR MEMORY - A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell. | 08-19-2010 |
| 20100246307 | INTERNAL POWER SUPPLY CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY - An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined period, when a mode changes from a normal operation mode where power is always supplied from the internal power supply circuit to the internal circuit to a standby mode where consumption power is further suppressed as compared with consumption power in the normal operation mode, and a permission signal output unit that outputs the permission signal synchronized with the periodic signal to the internal power supply circuit, when a mode signal indicating any mode of the normal operation mode and the standby mode and the periodic signal are input and the input mode signal indicates the standby mode. | 09-30-2010 |
| 20100290305 | Systems and Methods for Dynamic Power Savings in Electronic Memory Operation - Reduction of line delay is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control the bit line length for address selection. The latch repeaters are, in one embodiment, allowed to remain in their operated/non-operated state at the completion of a memory read/write cycle. This then avoids successive enabling pulses when the same segment is accessed on successive cycles. | 11-18-2010 |
| 20100302893 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER THAT CONTROLS THE SAME, AND INFORMATION PROCESSING SYSTEM - To include a power-down control circuit that suspends an operation of a predetermined internal circuit in response to a power-down command, and an external terminal to which a selection signal is input from outside simultaneously with issuance of a power-down command. The power-down control circuit suspends an operation of a DLL circuit when the selection signal is at a low level, and continues an operation of the DLL circuit when the selection signal is at a high level. According to the present invention, by using the selection signal input simultaneously with a power-down command, mode selection can be made on-the-fly. | 12-02-2010 |
| 20100322027 | MEMORY USING MULTIPLE SUPPLY VOLTAGES - A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is decoupled from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift. If the power supply node drifts to a second voltage, a power supply source is coupled to the power supply node. This is useful in reducing power in the circuit that produces the first voltage. | 12-23-2010 |
| 20110058439 | Circuits, Architectures, Apparatuses, Systems, Algorithms, and Methods for Memory with Multiple Power Supplies and/or Multiple Low Power Modes - Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail. | 03-10-2011 |
| 20110216619 | MEMORY POWER MANAGEMENT SYSTEMS AND METHODS - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 09-08-2011 |
| 20110222362 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state. | 09-15-2011 |
| 20110261639 | Semiconductor memory circuit - The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized. | 10-27-2011 |
| 20110292753 | MEMORY LEAKAGE AND DATA RETENTION CONTROL - A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is coupled to the virtual ground and the gate of the NMOS transistor is coupled to the current source. | 12-01-2011 |
| 20120002499 | Power control of an integrated circuit memory - An integrated circuit memory | 01-05-2012 |
| 20120008449 | LOW POWER STATIC RANDOM ACCESS MEMORY - A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices. | 01-12-2012 |
| 20120069693 | DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR - A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. | 03-22-2012 |
| 20120075948 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 03-29-2012 |
| 20120087199 | WAKE-UP CONTROL CIRCUIT FOR POWER-GATED IC - Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a lower impedance than the second switch. When a wake up signal is received, the second switch may be turned on first and the first switch may be turned on after the virtual power supply reaches a predetermined voltage level. | 04-12-2012 |
| 20120243364 | METHOD AND SYSTEM FOR DYNAMIC POWER MANAGEMENT OF MEMORIES - A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature. | 09-27-2012 |
| 20120307584 | MEMORY POWER SUPPLY CIRCUIT - A memory power supply circuit is used for providing power to a first memory module received in a first memory slot and a second memory module received in a second memory slot, and comprises a logic circuit and a switching power supply. The logic circuit comprises a first input terminal electrically connected to the first memory slot, a second input terminal electrically connected to the second memory slot, and a first signal terminal. The switching power supply comprises a first power terminal, a second power terminal, and a second signal terminal electrically connected to the first signal terminal. When the first memory slot and the second memory slot receive the first memory slot and the second memory module, the switching power supply turns on the first power terminal and the second power terminal; otherwise, the switching power supply turns off the first power terminal or the second power terminal. | 12-06-2012 |
| 20120314522 | CONTROLLING CLOCK INPUT BUFFERS - An integrated circuit may have a clock input pin coupled to a buffer ( | 12-13-2012 |
| 20130010563 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER-SAVING FEATURE - A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state. | 01-10-2013 |
| 20130064032 | SEMICONDUCTOR STORAGE DEVICE AND ELECTRONIC APPARATUS - A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros. | 03-14-2013 |
| 20130094318 | Energy Efficient Processor Having Heterogeneous Cache - A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells. | 04-18-2013 |
| 20130128684 | REDUCED LEAKAGE BANKED WORDLINE HEADER - A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication. | 05-23-2013 |
| 20130170310 | ULTRA LOW POWER MEMORY CELL WITH A SUPPLY FEEDBACK LOOP CONFIGURED FOR MINIMAL LEAKAGE OPERATION - A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether. | 07-04-2013 |
| 20130188436 | INTEGRATED CIRCUIT WITH ADAPTIVE POWER STATE MANAGEMENT - Methods and apparatuses that relate to an integrated circuit (IC) with adaptive power state management are described. The IC can be coupled with, and can control the operation of, a memory device. The IC and the memory device can be operated in multiple operational states, wherein each operational state may represent a tradeoff point between performance and power consumption. The IC may be capable of: ( | 07-25-2013 |
| 20130215701 | APPARATUSES AND METHODS FOR PROVIDING WORD LINE VOLTAGES - Apparatuses and methods of providing word line voltages are disclosed. An example apparatus includes a voltage driver and a word line driver. The voltage driver is configured to provide a word line voltage, wherein the word line voltage is a pumped supply voltage responsive to an active mode and the word line voltage is a non-zero voltage less than the pumped supply voltage during a standby mode. The word line driver is coupled to the voltage driver and is configured to drive a respective word line to the word line voltage during the active and standby modes. | 08-22-2013 |
| 20130235689 | SEMICONDUCTOR DEVICE - To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch. | 09-12-2013 |
| 20130301372 | MEMORY DEVICE, MEMORY SYSTEM, AND POWER MANAGEMENT METHOD - A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address. | 11-14-2013 |
| 20130315020 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 11-28-2013 |
| 20130322198 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 12-05-2013 |
| 20140036612 | BTI-Independent Source Biasing of Memory Arrays - A memory device having an array of memory cells and BTI-independent bias circuitry for controlling the bias voltage level of a source node of the array. The bias circuitry has an n-type transistor and a p-type transistor connected in parallel between ground and the source node. The bias circuitry also has circuitry for controlling the n-type and p-type transistors such that the memory device can be selectively configured in any of an active mode (where the source node is driven towards ground such that the array can be accessed), a low-leakage-current light sleep mode (where the source node is driven towards an intermediate, data-retention voltage level such that the array cannot be accessed but will retain data), and an even-lower-leakage-current shutdown mode (where the source node is driven towards the power supply voltage level such that the array cannot be accessed and cannot retain data). | 02-06-2014 |
| 20140071782 | Circuits, Architectures, Apparatuses, Systems, Algorithms, and Methods for Memory with Multiple Power Supplies and/or Multiple Low Power Modes - Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail. | 03-13-2014 |
| 20140078850 | SEMICONDUCTOR DEVICE AND MEMORY CONTROL METHOD - An access detection section detects access to an access object circuit and outputs a signal which restricts switching the access object circuit from a first operation state to a second operation state (low power consumption operation state) in which power consumption is lower than power consumption in the first operation state (normal operation state) until no-access period which lasts from last access to next access reaches a first period. An operation control section controls operation of the access object circuit according to the output of the access detection section. | 03-20-2014 |
| 20140086000 | POWER CONSUMPTION CONTROL - The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases. | 03-27-2014 |
| 20140119146 | Clock Gated Storage Array - A storage array and a method of operating the same are disclosed. A storage array includes a number of clocked storage circuits arranged in rows and columns. The storage array is subdivided into a number of grids each including a subset of clocked storage circuits and also includes a number of clock gating circuits, each of which is coupled to provide a clock signal to the clocked storage circuits of a corresponding subset. During an access of the storage array (i.e. a read or a write), one of the clock gating circuits is configured to provide the clock signal to the clocked storage circuits of its correspondingly coupled subset. The remaining clock gating circuits are configured to inhibit the clock signal from being provided to the flop circuits of their respectively coupled subsets. | 05-01-2014 |
| 20140119147 | SEGMENTED MEMORY HAVING POWER-SAVING MODE - A memory array is divided into multiple segments, each segment having one or more rows of bitcells. Each segment has control circuitry that controls whether the segment is in an active mode or a power-saving, sleep mode. The control circuitry ensures that a segment transitions from sleep mode to active mode before a row of the segment is accessed by driving a corresponding wordline high. The control circuitry also ensures that, at the end of a row access, the wordline is driven low before the corresponding segment is transitioned from active mode to sleep mode. | 05-01-2014 |
| 20140177374 | DRIVER OF SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A driver of a semiconductor memory device and driving method thereof is disclosed, which relates to a technology for reducing consumption of a leakage current not required for a driver circuit of a semiconductor memory device. The driver of the semiconductor memory device includes a drive controller configured to selectively provide a first voltage and a second voltage, that have different levels in response to a power-down signal, to a first node; an input driver configured to selectively output a voltage received from the first node in response to a decoding signal; and an output driver configured to be driven in response to an output voltage of the input driver. | 06-26-2014 |
| 20140192608 | CONTROLLING METHOD OF CONNECTOR, CONNECTOR, AND MEMORY STORAGE DEVICE - A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced. | 07-10-2014 |
| 20140241096 | STORAGE DEVICE - A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token. | 08-28-2014 |
| 20140269138 | SEMICONDUCTOR MEMORY DEVICE FOR REDUCING STANDBY CURRENT - A semiconductor memory device includes a standby voltage providing unit. The standby voltage providing unit is configured to receive an external voltage, primarily clamp and secondarily clamp a predetermined voltage, and provide the predetermined voltage as an internal voltage, during a standby mode. | 09-18-2014 |
| 20140307517 | SEMICONDUCTOR DEVICE INCLUDING POWER-ON RESET CIRCUIT AND OPERATING METHOD THEREOF - A semiconductor device includes a power-on reset circuit configured to receive a power voltage and generate a power-on reset signal varying with a voltage level of the power voltage, an internal circuit configured to be initialized and operated in response to the power-on reset signal and generate a hold signal based on an operation mode of the internal circuit, and a reset protection circuit configured to deactivate the power-on reset circuit in response to the hold signal and provide a replacement signal for replacing the power-on reset signal to the internal circuit when the power-on reset circuit is deactivated. | 10-16-2014 |
| 20140313843 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREFOR - A semiconductor integrated circuit includes a plurality of first non-volatile registers including a retention circuit that retains volatile data and one or more non-volatile elements capable of retaining non-volatile data, and a second non-volatile register that retains a load enable bit that decides in which one of the plurality of first non-volatile registers data is loaded. The semiconductor integrated circuit also includes a non-volatile register control circuit that, when supply power is delivered from outside, loads to the retention circuit data retained by the non-volatile element(s) contained in the first non-volatile register specified by the load enable bit loaded from the second non-volatile register (FIG. | 10-23-2014 |
| 20140321227 | FREQUENCY POWER MANAGER - A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode. | 10-30-2014 |
| 20140340977 | LOW POWER TRANSIENT VOLTAGE COLLAPSE APPARATUS AND METHOD FOR A MEMORY CELL - Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node. | 11-20-2014 |
| 20140362655 | SEMICONDUCTOR INTEGRATED CIRCUIT AND INFORMATION PROCESSING APPARATUS - According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a second terminal and the third terminal. The level shifter adjusts a voltage level between a first terminal and a second terminal. The switch circuit includes a first switch selectively connecting the third terminal of the regulator to a first potential, a second switch selectively connecting the third terminal of the regulator to the first terminal of the level shifter, and a third switch selectively connecting the third terminal of the regulator to a second potential. | 12-11-2014 |
| 20150009772 | MEMORY HAVING POWER SAVING MODE - A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode. | 01-08-2015 |
| 20150029808 | POWER FAIL PROTECTION AND RECOVERY USING LOW POWER STATES IN A DATA STORAGE DEVICE/SYSTEM - Systems and methods for early warnings of power loss in solid state storage drives are disclosed. Early warnings of power loss can be used to power the drive to force the drive into a low power states before the energy in backup power sources, such as backup capacitors, is used. The low power states can allow for the reduction of power use by the drive which can provide cost savings and reduction in the risk that the drive will be rendered reconfigurable by a power failure event. | 01-29-2015 |
| 20150098291 | POWER CONSUMPTION CONTROL - The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases. | 04-09-2015 |
| 20150117132 | SEMICONDUCTOR MEMORY DEVICE AND DATA STORAGE DEVICE INCLUDING THE SAME - A semiconductor memory device includes a memory cell array, a voltage generator suitable for generating voltages used for controlling the memory cell array in response to a power-saving signal, and a control logic suitable for providing a power-saving signal to the voltage generator, based on a chip select signal. The control logic includes a delay block suitable for delaying the chip select signal and generating the power-saving signal based on the delayed chip select signal. | 04-30-2015 |
| 20150131396 | SEMICONDUCTOR MEMORY DEVICE WITH SWITCHES FOR SUSPENDING POWER SUPPLY - A method of making a semiconductor integrated circuit includes forming switches configured to suspend, on a way-specific basis, power supply to ways allocated to one or more RAM macros. | 05-14-2015 |
| 20150138905 | Low Leakage State Retention Synchronizer - Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit, and an output, wherein the second memory unit operates on a second power supply which is always on; and a control logic coupled to the first and second memory units, the control logic to provide one or more control signals to each of the first and second memory units. | 05-21-2015 |
| 20150364175 | VOLUME SELECT FOR AFFECTING A STATE OF A NON-SELECTED MEMORY VOLUME - Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can include selecting the targeted memory volume of the memory volumes and putting at least a portion of a non-selected memory volume of the memory volumes in a particular state based, at least in part, on a previous state of the non-selected memory volume and/or a portion of an address associated with the select command. | 12-17-2015 |
| 20160019936 | ULTRA LOW POWER ARCHITECTURE TO SUPPORT ALWAYS ON PATH TO MEMORY - An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power. | 01-21-2016 |
| 20160086638 | CIRCUITS, ARCHITECTURES, APPARATUSES, SYSTEMS, ALGORITHMS, AND METHODS FOR MEMORY WITH MULTIPLE POWER SUPPLIES AND/OR MULTIPLE LOW POWER MODES - Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail. | 03-24-2016 |
| 20160148653 | METHOD AND APPARATUS FOR USING A PRE-CLOCK ENABLE COMMAND FOR POWER MANAGEMENT MODES - Provided are a method and apparatus for using a pre-clock enable (pre-CKE) command for power management modes. A host memory controller sends a pre-CKE command to a memory module over a bus indicating at least one power management operation to perform. The host memory controller further asserts a clock enable (CKE) signal to the memory module over the bus after sending the pre-CKE command to cause a memory module controller to execute the indicated at least one power management operation in response to the CKE signal. | 05-26-2016 |
| 20160196854 | SEMICONDUCTOR DEVICE | 07-07-2016 |
| 20160202713 | CIRCUIT DRIVING METHOD AND DEVICE | 07-14-2016 |
| 20170236561 | MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL | 08-17-2017 |
