| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365180000 | Four layer devices | 12 |
| 20080239803 | MEMORY CELLS, MEMORY DEVICES AND INTEGRATED CIRCUITS INCORPORATING THE SAME - A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor. | 10-02-2008 |
| 20090086536 | Semiconductor device - A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another. | 04-02-2009 |
| 20090086537 | Semiconductor device - A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and the first terminal of the thyristor element, respectively, and a control section including a load current element whose load current flows, upon reading out operation, to the second terminal side of the thyristor element and configured to carry out access control to the memory cell. | 04-02-2009 |
| 20090213648 | Integrated Circuit Comprising a Thyristor and Method of Controlling a Memory Cell Comprising a Thyristor - An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal. | 08-27-2009 |
| 20100002502 | MEMORY DEVICE AND METHOD OF REFRESHING - A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor. | 01-07-2010 |
| 20130314986 | Thyristors - Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors. | 11-28-2013 |
| 20140003140 | THYRISTOR MEMORY AND METHODS OF OPERATION | 01-02-2014 |
| 20140340962 | THYRISTOR MEMORY AND METHODS OF OPERATION - Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed. | 11-20-2014 |
| 20160078917 | Thyristors, Methods of Programming Thyristors, and Methods of Forming Thyristors - Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors. | 03-17-2016 |
| 20160093356 | Methods of Reading and Writing Data in a Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array. | 03-31-2016 |
| 20160093357 | Methods of Retaining and Refreshing Data in a Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein. | 03-31-2016 |
| 20160093358 | Power Reduction in Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays. | 03-31-2016 |
