| Entries |
| Document | Title | Date |
|---|
| 20080225502 | Alternating micro-vias and throughboard vias to create PCB routing channels in BGA interconnect grid - A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board. | 09-18-2008 |
| 20080266825 | ELECTRONIC COMPONENT PACKAGE, ELECTRONIC COMPONENT MOUNTED APPARATUS, METHOD OF INSPECTING BONDING PORTION THEREIN, AND CIRCUIT BOARD - An electronic component package includes: an insulating carrier substrate; a connection wiring that is provided on one side of the carrier substrate; an IC chip that is connected to the connection wiring; an external connection land that is disposed on the other side of the carrier substrate and is connected to the connection wiring via a wiring in the carrier substrate; and a solder ball that is disposed on the external connection land. A region of the external connection land that can be bonded to the solder ball has an outer shape that includes at least one arc portion and at least one straight portion. With this configuration, it is possible to provide an electronic component mounted apparatus in which bonding failure of the external connection land and the circuit board-side land with the solder ball can be reduced, and the bonding state can be easily inspected, and a method of inspecting a bonding portion therein. | 10-30-2008 |
| 20080291650 | Arrangement Having an Electric Motor and a Main Printed Circuit Board, and an Assembly Method - A device provided with an electric motor ( | 11-27-2008 |
| 20080298033 | POWER SUPPLY PLATFORM AND ELECTRONIC COMPONENT - An electric power supply platform ( | 12-04-2008 |
| 20090002964 | Multilayer wiring element having pin interface - A method of forming contacts for an interconnection element, includes (a) joining a conductive element to an interconnection element having multiple wiring layers, (b) patterning the conductive element to form conductive pins, and (c) electrically interconnecting the conductive pins with conductive features of the interconnection element. A multiple wiring layer interconnection element having an exposed pin interface, includes an interconnection element having multiple wiring layers separated by at least one dielectric layer, the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element, a plurality of conductive pins protruding in a direction away from the first face, and metal features electrically interconnecting the conductive features with the conductive pins. | 01-01-2009 |
| 20090027865 | Surface Mount Electrical Component - A surface mount electrical component comprising a first soldering interface having a fist soldering interface total solder path length of sufficient length such that a first melted solder fillet substantially disposed along the first soldering interface total solder path length produces an first upward moment greater than a first downward moment produced by the weight of the surface mount electrical component about the first soldering interface, and a second soldering interface comprising a second soldering interface total solder path length such that a surface tension produced by a second melted solder fillet substantially disposed along the second soldering interface total solder path length produces a second upward moment greater than a second downward moment produced by the weight of the surface mount electrical component about the second soldering interface is disclosed. | 01-29-2009 |
| 20090034218 | PRINTED CIRCUIT BOARD ASSEMBLY - A printed circuit board assembly ( | 02-05-2009 |
| 20090040739 | LSI PACKAGE WITH INTERFACE MODULE AND INTERFACE MODULE - An LSI package includes an interface module having first and second surfaces and including a wiring board having a first through hole, a driver selectively provided on the second surface, a transmission line connected to the driver, and a first terminal formed on the second surface and connected to the driver, an interposer having a third surface facing the second surface and a fourth surface, and including a signal processor and a second terminal provided on the third surface, a third terminal provided on the fourth surface and a second through hole, the third surface facing the second surface except a region where the driver portion is provided. The interposer is arranged so that the first through hole matches with the second through hole, and a movable guide pin is inserted into the first and second through holes to position the interface module and the interposer. | 02-12-2009 |
| 20090080169 | Method for forming BGA package with increased standoff height - A method of forming a Ball Grid Array (BGA) package having an increased standoff height after solder reflow is described. A substrate containing a plurality of first solder bond pads and a component containing a plurality of second solder bond pads are arranged in parallel spaced relationship to form an arrangement, each first and second bond pad being in contact with a solder ball therebetween. Solder balls are formed of a core, which remains solid at solder reflow temperatures, encapsulated with a reflowable solder layer. First standoff height of the arrangement is largely determined by the diameter of the solder ball. Upon heating to solder reflow temperatures, the solder coalesces between the core and the bond pads. Upon cooling of the arrangement, the second standoff height of the BGA package is greater than the first standoff height of the arrangement. | 03-26-2009 |
| 20090080170 | Electronic carrier board - An electronic carrier board includes a plurality of round pads and a plurality of solder layers formed on the round pads respectively. The design of the round pads ensures the solder layers covering the pads completely, and neighboring sides of the two solder layers are lower than opposite sides, such that electronic element can be stably fixed on the two solder layers to prevent the tombstone of the electronic element. | 03-26-2009 |
| 20090129038 | CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a simplified structure of a circuit device in which a power element generating a large amount of heat is incorporated. The circuit device according to the present invention includes: a circuit board whose surface is covered with an insulating layer; a conductive pattern formed on the surface of the insulating layer; a circuit element electrically connected to the conductive pattern; and a lead connected to a pad formed of the conductive pattern. Furthermore, a power element is fixed to the top surface of a land portion formed of a part of the lead. Accordingly, the land portion serves as a heat sink, thereby contributing to heat dissipation. | 05-21-2009 |
| 20090135569 | ELECTRONIC COMPONENT WITH WIRE BONDS IN LOW MODULUS FILL ENCAPSULANT - An electronic component that has a support structure with a plurality of electrical conductors, a series of wire bonds, each of the wire bonds extending from one of the electrical conductors respectively, each of the wire bonds having an end section contacting the electrical conductor and an intermediate section contiguous with the end section, a bead of dam encapsulant encapsulating the electrical conductors and the end section of each of the wire bonds, and a bead of fill encapsulant contacting the bead of dam encapsulant and encapsulating the intermediate portion of each of the wire bonds. The dam encapsulant has a higher modulus of elasticity than the fill encapsulant. | 05-28-2009 |
| 20090154126 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A wiring board includes a first bonding wiring array that is formed by extending conductor wirings, and that extends from an external side of a semiconductor element region and is bonded individually to a first element electrode array of a semiconductor element, and a second bonding wiring array that extends from the external side of the semiconductor element region and is bonded individually to a second element electrode array of the semiconductor element. A pitch of the individual conductor wirings constituting the first bonding wiring array varies continuously so as to be wider than a pitch of the first element electrode array on the external side of the semiconductor element region and narrower than that of the first element electrode array at a front end on a center side of the semiconductor element, and a pitch of the individual conductor wirings constituting the second bonding wiring array varies continuously so as to be narrower than a pitch of the second element electrode array on the external side of the semiconductor element region and wider than that of the second element electrode array at a front end on the center side of the semiconductor element. In bare chip mounting by flip chip or ILB such as COF, the displacement between the semiconductor element and the electrode caused by a dimensional change of the wiring board can be alleviated. | 06-18-2009 |
| 20090168381 | PRINTED WIRING BOARD UNIT AND METHOD OF MAKING THE SAME - An electrically-conductive pin is inserted into a through hole penetrating through a substrate between a first surface and a second surface defined at the reverse side of the first surface so that the electrically-conductive pin stands upright from the first surface of the substrate. An electronic component is then mounted on the tip end of the electrically-conductive pin standing upright from the first surface. The electrically-conductive pin is inserted into the through hole before an electronic component is mounted on the tip end of the electrically-conductive pin. It is thus extremely easy to insert the electrically-conductive pin into the through hole. As compared with the case where the electrically-conductive pins are first bonded to an electronic component, an operator is released from a troublesome operation of inserting the electrically-conductive pin. The electronic component can be mounted in an efficient manner. | 07-02-2009 |
| 20090257209 | Semiconductor package and associated methods - A semiconductor package and associated methods, the semiconductor package including a substrate including a socket, and connection terminals including a solder ball and a supporting portion extending from the solder ball into the socket. | 10-15-2009 |
| 20100027228 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes wiring boards each having an insulating board, conductor circuits and through-holes, the insulating board having top and bottom surfaces, the conductor circuits formed on the top and bottom surfaces, the through holes penetrating the insulating board and electrically connecting the conductor circuits of the top and bottom surfaces; conductor posts each having flange, head and leg portions, the flange portion having first and second surfaces and having an external diameter larger than that of the through-hole, the head portion protruding from the first surface, the leg portion protruding from the second surface; and electronic components each having an electrode formed on one or more surfaces and connected to the leg portion. The head portion is inserted until the first surface of the flange portion comes into contact with the bottom surface of the wiring board and electrically connected at an inner wall of the through-hole. | 02-04-2010 |
| 20100053922 | MICROPACKAGING METHOD AND DEVICES - A method of micro-packaging a component wherein at least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of the substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. A micro-packaged electronic or micromechanic device, including a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing is also disclosed. An electronic or micromechanic component is attached to the electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box. | 03-04-2010 |
| 20100067207 | SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMADATE HIGH SPEED CIRCUITRY GROUND ISOLATION - Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package. | 03-18-2010 |
| 20100091472 | SEMICONDUCTOR PACKAGE - Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities. | 04-15-2010 |
| 20100118503 | Electric drive with a circuit board - An electric drive ( | 05-13-2010 |
| 20100149770 | Semiconductor stack package - The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips. | 06-17-2010 |
| 20100157556 | Surface mounting lug terminal and method for mounting the same - A surface mounting lug terminal formed of a metallic plate having terminal leads and positioning projections can readily be positioned on a printed board with high precision by fitting the positioning projections into positioning cutouts formed in the printed board. The terminal leads of the surface mounting lug terminal can easily be soldered to land patterns on the printed board to secure the surface mounting lug terminal onto the printed board irrespective of the number of terminal leads. The surface mounting lug terminal can be reduced in size, thus to contribute miniaturization of electronic circuits. | 06-24-2010 |
| 20100188829 | ANISOTROPIC CONDUCTIVE FILM, METHOD FOR PRODUCING THE SAME, AND JOINED STRUCTURE USING THE SAME - An anisotropic conductive film, containing a resin film; and conductive particles aligned into a monolayer within the resin film adjacent to or on one plane of the resin film with respect to a thickness direction of the resin film, wherein a distance between the one plane of the resin film and a center of the conductive particle is 9 μm or less based on 10-point average. | 07-29-2010 |
| 20100214751 | CHIP COMPONENT MOUNTED WIRING BOARD - A wiring board to be used with being mounted on a packaging board includes a chip component surface-mounted on a surface facing the packaging board. The chip component includes terminal electrodes at both end portions of the component body thereof. Each of the terminal electrodes is provided in a form in which a plated film (Sn) formed on the surface of the terminal electrode is separated into two portions, one portion being on the wiring board side, and another portion being on the packaging board side. In one aspect, each of the terminal electrodes of the chip component is separated into a portion on the wiring board side and a portion on the packaging board side, and the plated film (Sn) is formed on a surface of each of the separated portions of each of the terminal electrodes. | 08-26-2010 |
| 20100226109 | ELECTRONIC SUBSTRATE, MANUFACTURING METHOD FOR ELECTRONIC SUBSTRATE, AND ELECTRONIC DEVICE - An electronic substrate includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed. | 09-09-2010 |
| 20100302748 | CERAMIC SUBSTRATE PART AND ELECTRONIC PART COMPRISING IT - A ceramic substrate part comprising on its upper surface pluralities of external electrodes comprising wire-bonding electrodes, each of which comprises a primer layer based on Ag or Cu, a Ni-based lower layer, an intermediate layer based on a Pd—P alloy containing 0.4-5% by mass of P, and a Au-based upper layer formed in this order on a ceramic substrate, the upper layer containing Pd after heated by soldering, and having a Au concentration of 80 atomic % or more based on the total concentration (100 atomic %) of Au and Pd. | 12-02-2010 |
| 20110110059 | APPARATUS AND METHODS FOR THERMAL MANAGEMENT OF ELECTRONIC DEVICES - An apparatus is disclosed that may include a printed circuit board (PCB) and an electronics package may be disposed about the first surface of the PCB. The PCB may include a metal layer and a core, and, in some aspects, may include multiple cores interposed between multiple metal layers, and in some embodiments a backplane may be disposed along the core. The metal layer may be disposed on a core first surface. The metal layer may comprise metal or other conductive material suitable to define traces, which may be circuit paths for electronic components affixed to the PCB. In some aspects, the core may be electrically non-conducting, and may be thermally insulating, and, accordingly, inhibit the transfer of heat from the electronics package through the PCB. However, pins may be configured to pass through the PCB including the core from the core first surface to the core second surface to conduct heat generated by the electronics package away for dispersion. In some embodiments, the pins may pass into the backplane. A pad may be disposed between the electronic package and the core in some embodiments, the pins passing into the pad. | 05-12-2011 |
| 20110188218 | LAYOUT SCHEMES AND APPARATUS FOR MULTI-PHASE POWER SWITCH-MODE VOLTAGE REGULATOR - A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern. | 08-04-2011 |
| 20110286189 | METHOD OF FABRICATING WIRING BOARD AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer. | 11-24-2011 |
| 20110317386 | CONNECTING STRUCTURE, CIRCUIT DEVICE AND ELECTRONIC APPARATUS - To provide a connecting structure which can effectively suppress the generation of a crack and an exfoliation of a terminal. The connecting structure includes a frame | 12-29-2011 |
| 20120020040 | Package-to-package stacking by using interposer with traces, and or standoffs and solder balls - The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contact pads disposed on a top and/or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack. | 01-26-2012 |
| 20120020041 | DEVICE AND MANUFACTURING METHOD OF THE SAME - A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board. | 01-26-2012 |
| 20120026705 | INTERPOSER LEAD - An interposer lead provides a connection between an integrated circuit and a circuit board. The interposer lead includes a first leg for interfacing with the circuit board. The interposer lead also includes a second leg disposed generally parallel to the first leg for interfacing with an IC electrical lead extending from the integrated circuit. A connecting portion operatively connects the first leg and the second leg. The interposer lead further includes a lip extending non-parallel from the second leg for limiting movement of the IC electrical lead on the second leg. | 02-02-2012 |
| 20120063106 | RF LAYERED MODULE USING THREE DIMENSIONAL VERTICAL WIRING AND DISPOSING METHOD THEREOF - Provided is a structure and disposing method of a radio frequency (RF) layered module using three dimensional (3D) vertical wiring. A first wafer in the RF layered module having the 3D vertical wiring may include a first RF device and at least one first via- hole. A second wafer may include a second RF device and at least one second via-hole disposed at a location corresponding to the at least one first via-hole. A vertical wiring may connect the at least one first via-hole and the at least one second via-hole. The vertical wiring may be configured to be connected to an external device through a bottom surface of the at least one first via-hole or a top surface of the at least one second via-hole. | 03-15-2012 |
| 20120127681 | SOLDERING CONNECTING PIN, SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MOUNTING SEMICONDUCTOR CHIP USING THE SAME - Disclosed herein are a soldering connecting pin, a semiconductor package substrate and a method of mounting a semiconductor chip using the same. A semiconductor chip is mounted on the printed circuit board using the soldering connecting pin inserted into a through-hole of the printed circuit board, thereby preventing deformation of the semiconductor package substrate and fatigue failure due to external shocks. | 05-24-2012 |
| 20120293972 | Integrated Voltage Regulator Method with Embedded Passive Device(s) - A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias. | 11-22-2012 |
| 20120327623 | PRINTED CIRCUIT BOARD AND LAYOUT METHOD THEREOF - A printed circuit board includes first and second layout layers, first and second components, and a pair of connecting portions. The first layout layer includes a pair of first conducting portions connected to a control chip. The second layout layer includes pairs of second to fourth conducting portions. The connecting portions connect the first and third conducting portions together. When an electronic device is connected to the second conducting portions, and the first and second components are connected to the third and fourth conducting portions to form a first route, signals generated by the control chip are transmitted to the electronic device through the first route. When the electronic device is connected to the fourth conducting portions, and the first and second components are connected to the second and third conducting portions to form a second route, the signals are transmitted to the electronic device through the second route. | 12-27-2012 |
| 20130021766 | Electronic Component - An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap. | 01-24-2013 |
| 20130063918 | LOW CTE INTERPOSER - An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”). | 03-14-2013 |
| 20130128485 | METHOD FOR ENHANCING RELIABILITY OF WELDING SPOT OF CHIP, PRINTED CIRCUIT BOARD AND ELECTRONIC DEVICE - The present invention relates to processing of PCBA, and provides a method for enhancing reliability of a welding spot of a chip, a printed circuit board and an electronic device. The method for enhancing reliability of the welding spot of the chip includes: dipping an epoxy flux on a weld leg of a chip or coating, with epoxy flux, a bonding pad corresponding to the weld leg of the chip, and mounting the chip to the bonding pad; and performing reflow processing on the bonding pad mounted with the chip, and finishing curing the epoxy flux. By applying the present invention, an Underfill process is not required, thereby reducing the cost of the device and improving the manufacturing efficiency. | 05-23-2013 |
| 20130155636 | DUMMY THROUGH-SILICON VIA CAPACITOR - An integrated circuit device includes dummy through-silicon vias (TSVs) that can be connected to one or more voltage references, thereby increasing a capacitance associated with the integrated circuit device, such as a decoupling capacitance. In addition, the dummy TSVs can be distributed based on the distribution of active TSVs in the device, thus increasing the stability and performance of the TSV manufacturing process. | 06-20-2013 |
| 20130265731 | CIRCUIT BOARD SYSTEM - A circuit board system includes a first circuit board ( | 10-10-2013 |
| 20130286617 | CIRCUIT DEVICE - A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. A lead ( | 10-31-2013 |
| 20130286618 | CIRCUIT DEVICE - A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. The hybrid integrated circuit device ( | 10-31-2013 |
| 20140092573 | CONTACT PROTECTION FOR INTEGRATED CIRCUIT DEVICE LOADING - In one embodiment, a load frame and an integrated circuit device are aligned, with a base frame carried on a substrate, along a first alignment axis defined by a first alignment post extending from the base frame to the load frame, in a direction transverse to the substrate, and a first biasing device carried on the base frame is actuated to engage and bias the load frame toward the base frame aligned with the load frame, and to bias the integrated circuit toward the substrate. A latch latches the load and base frames together, aligned with and biased towards each other with the integrated circuit device and the substrate aligned with, and biased toward each other. Other aspects and features are also described. | 04-03-2014 |
| 20140133120 | SUBSTRATE WITH BUILT-IN ELECTRONIC COMPONENT - In a first conductive layer and a third conductive layer that are respectively closest to a core layer having a storage portion that penetrates therethrough, four first penetrating holes and four first penetrating holes are formed so as to overlap part of an opening edge of the storage portion that is projected onto the first conductive layer and the third conductive layer, respectively. | 05-15-2014 |
| 20140192499 | SEMICONDUCTOR DEVICE AND PRINTED CIRCUIT BOARD - Provided is a compact semiconductor device having high joint reliability of multiple first ball electrodes arrayed on one surface of a first interposer. On a surface ( | 07-10-2014 |
| 20140211440 | CABINET FOR THIN DISPLAY DEVICE AND THIN DISPLAY DEVICE - Provided is technology that stably fixes a plurality of harnesses all at once, without using a wire holder. A line-shaping section | 07-31-2014 |
| 20140240940 | ELECTRONIC COMPONENT CONNECTION STRUCTURE - A connection structure for an electronic component, which is set on two lead frames spaced apart from each other. The electronic component is connected to the two lead frames by a conductive joining member. The connection structure includes two electrodes arranged on at least portions of a lower surface of the electronic component. The two electrodes respectively face the two lead frames. A receiving surface is included in each of the two lead frames immediately below the corresponding electrode. The receiving surface extends from a supporting portion supporting the electronic component toward the other one of the lead frames and away from the electronic component. The conductive joining member is located between the receiving surface of each of the two lead frames and the corresponding one of the electrodes. | 08-28-2014 |
| 20140240941 | ELECTRONIC PART AND ELECTRONIC CONTROL UNIT - A main body of an electronic part has multiple electrodes, to which multiple terminals are connected. The terminals include a normal terminal and a fuse terminal, each of which extends from lands formed in a printed board so as to hold the main body at a position above and separated from a board surface of the printed board. The fuse terminal has a cut-off portion having a smaller width than other portions of the fuse terminal, so that the cut-off portion is melted down when excess current flows in the fuse terminal. The normal terminal holds the main body at the position above and separated from the board surface even in a case of melt-down of the cut-off portion. | 08-28-2014 |
| 20140240942 | ELECTRONIC PART AND ELECTRONIC CONTROL UNIT - A main body of an electronic part is formed in a rectangular pillared shape having a first and a second axial end surface. A first electrode is formed on the first axial end surface electrically and mechanically connected to a first wiring pattern formed on a board surface of a printed board. A second electrode is formed on the second axial end surface, to which one end of a fuse terminal is electrically connected. The other end of the fuse terminal is connected to a second wiring pattern of the printed board or a wiring member which is formed as an independent member from the printed board. A cut-off portion is formed in a connecting portion of the fuse terminal. | 08-28-2014 |
| 20140240943 | SOLDER IN CAVITY INTERCONNECTION TECHNOLOGY - An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball. | 08-28-2014 |
| 20140247574 | PRINTED CIRCUIT BOARD - A printed circuit board includes a printed circuit board, a semiconductor device mounted on the printed circuit board, a capacitor element mounted on the printed circuit board | 09-04-2014 |
| 20140254120 | DEVICE PACKAGING STRUCTURE AND DEVICE PACKAGING METHOD - Provided is a device packaging structure including: an interposer substrate including a substrate, and a plurality of through-hole interconnections formed inside a plurality of through-holes passing through the substrate from a first main surface toward a second main surface, the first main surface being one main surface of the substrate, the second main surface being the other main surface thereof; a first device which includes a plurality of electrodes and is arranged so that these electrodes face the first main surface; and a second device which includes a plurality of electrodes of which an arrangement is different from an arrangement of each of the electrodes of the first device, and is arranged so that these electrodes face the second main surface. | 09-11-2014 |
| 20140307406 | CERAMIC MULTILAYER WIRING SUBSTRATE AND MODULE INCLUDING THE SAME - A module includes a multilayer body including laminated ceramic green sheets that have been fired, multiple mounting terminals arranged to mount a component thereon, the mounting terminals each including an end surface that is exposed at a main surface of the multilayer body, and multiple via conductors disposed inside the multilayer body so as to correspond to the mounting terminals at positions overlapped by the corresponding mounting terminals when viewed in a plan view. The lengths of the via conductors are adjusted so that predetermined points on the mounting terminals are positioned on the same plane. | 10-16-2014 |
| 20150016081 | ELECTRONIC DEVICE WITH INTEGRATED CIRCUIT CHIP PROVIDED WITH AN EXTERNAL ELECTRICAL CONNECTION NETWORK - An electronic device may include a substrate, and an integrated circuit over the substrate. The substrate may be provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links may include an impedance-compensating inductor. | 01-15-2015 |
| 20150022988 | LID BODY PORTION AND ELECTRONIC DEVICE PACKAGE USING THE LID BODY PORTION AND ELECTRONIC DEVICE - To provide a lid body portion with an improved mounting ratio of an electronic device component, an electronic device package and an electronic device including the same. There is provided a lid body portion including a concave portion in which a space portion is formed by a bottom portion and a side plate portion and a flange portion extending from an outer edge portion in an opening portion of the concave portion to the outside, in which a side-plate inner surface as a surface facing the space portion of the concave portion in the side plate portion inclines to the outside of the space portion. | 01-22-2015 |
| 20150049449 | DISPLAY DEVICE - A display device includes: a substrate; electrode terminals for external connection; an insulating film on the respective electrode terminals, the insulating film provided with openings which expose part of the respective electrode terminals, the insulating film covering the other portion of the respective electrode terminals; surface conductive films which are disposed so as to correspond to the respective openings, and are connected to part of the respective electrode terminals; and a circuit board disposed so as to oppose the substrate, the circuit board including circuit electrode terminals which are connected to the surface conductive films through a conductive bonding member so as to oppose the respective openings, the surface conductive films extending from an inside of an opening corresponding thereto to a surface of an insulating film corresponding thereto, peripheral edges of the respective surface conductive films being positioned beyond a peripheral edge of a circuit electrode terminal corresponding thereto. | 02-19-2015 |
| 20150092377 | DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH IN-TRENCH PACKAGE SURFACE CONDUCTORS AND METHODS OF THEIR FABRICATION - Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench. | 04-02-2015 |
| 20150109749 | CIRCUIT BOARD ASSEMBLY, WIRE FIXING DEVICE AND WIRE FIXING METHOD - A circuit board assembly includes a printed circuit board, at least one wire, at least one wire fixing device, and a plurality of electronic components. A wire fixing method includes following steps. Firstly, the wire fixing device is inserted into a conductive hole of the printed circuit board. Then, the wire fixing device is fixed on the printed circuit board via a soldering material. Then, a conducting terminal of the wire is introduced into an accommodation space of the wire fixing device through the first opening of the wire fixing device. Then, at least one concave structure is formed in an external surface of a first conducting part of the wire fixing device by a jig. Consequently, the conducting terminal of the wire is fixed on the wire fixing device, and the wire is electrically connected with the printed circuit board through the wire fixing device. | 04-23-2015 |
| 20150116969 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - An electronic device of the present invention includes an insulating base substrate in which a plurality of through electrodes are formed; an electronic element which is electrically connected to the through electrodes and is mounted on one surface of the base substrate; a lid which accommodates the electronic element and is bonded to the one surface of the base substrate; and an external electrode which covers a region ranging from an end face of the through electrode, which is exposed by the other surface of the base substrate, to the other surface in a vicinity of the end face. The external electrode includes a conductive film which covers a region ranging from the end face to the other surface in the vicinity of the end face, a first electrolytic plating film which is formed on a surface of the conductive film by an electrolytic plating method, and a second electrolytic plating film which is formed on a surface of the first electrolytic plating film by an electrolytic plating method. The second electrolytic plating film is formed of tin or a tin alloy. | 04-30-2015 |
| 20150124422 | ELECTRONIC DEVICE MOUNTING BOARD AND ELECTRONIC APPARATUS - There are provided an electronic device mounting board and an electronic apparatus that can be made lower in profile. An electronic device mounting board includes an insulating substrate having an opening in which an electronic device is disposed so as to lie over the opening as seen in a transparent plan view, and a reinforcement portion disposed on a surface or in an interior of the insulating substrate so as to lie around the opening of the insulating substrate as seen in a transparent plan view. | 05-07-2015 |
| 20150360934 | Microelectromechanical system and method for manufacturing a microelectromechanical system - A microelectromechanical system includes a microelectromechanical element and a substrate, in which an element surface of the element and a substrate surface of the substrate is integrally joined with the aid of an eutectic alloy at at least one joint. Also described is a method for manufacturing a microelectromechanical system. | 12-17-2015 |
| 20160021737 | ELECTRIC DEVICE MODULE AND METHOD OF MANUFACTURING THE SAME - An electronic device module includes a board including one or more external connection electrodes and plating lines extending from the external connection electrodes by a predetermined distance; one or more electronic devices mounted on the board; a molded part sealing the electronic devices; and a plurality of connective conductors extending from the external connection electrodes and penetrating through the molded part to be disposed within the molded part. | 01-21-2016 |
| 20160037649 | MULTILAYERED TRANSIENT LIQUID PHASE BONDING - A bonding structure includes a first layer of first alloy component disposed on a substrate and a first layer of a second alloy component disposed on the first alloy component. The second alloy component has a lower melting temperature than the first alloy component. A second layer of the first alloy component is disposed on the first layer of the second alloy component and a second layer of the second alloy component is disposed on the second layer of the first alloy component. | 02-04-2016 |
| 20160071789 | MOLDED INTERPOSER FOR PACKAGED SEMICONDUCTOR DEVICE - A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers. | 03-10-2016 |
| 20160073496 | FAN-OUT WAFER LEVEL PACKAGES HAVING PREFORMED EMBEDDED GROUND PLANE CONNECTIONS AND METHODS FOR THE FABRICATION THEREOF - Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections. | 03-10-2016 |
| 20160099192 | DUAL-SIDED RADIO-FREQUENCY PACKAGE HAVING BALL GRID ARRAY - Dual-sided radio-frequency package having ball grid array. In some embodiments, a packaged radio-frequency (RF) device may include a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side. The packaged RF device also includes a shielded package implemented on the first side of the packaging substrate, the shielded package including an RF circuit, the shielded package configured to provide RF shielding for at least a portion of the RF circuit. The packaged RF device further includes a ball-grid array (BGA) implemented on the second side of the packaging substrate, the BGA defining a mounting volume on the second side of the packaging substrate and a component implemented within the mounting volume. | 04-07-2016 |
| 20160143139 | ELECTRONIC COMPONENT DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electronic component device includes a first insulating layer, a wiring layer, a second insulating layer, a wiring component, and first and second electronic components. The first insulating layer includes a mounting region on an upper surface thereof. The wiring layer is formed on the first insulating layer except the mounting region. The second insulating layer is formed on the first insulating layer, is formed with an opening in the mounting region, and is formed with first and second connection holes on the wiring layer. The wiring component is mounted in the mounting region and in the opening and includes first and second connecting portions. The first electronic component is connected to the first connecting portion and is connected to the wiring layer in the first connection hole. The second electronic component is connected to the second connecting portion and is connected to the wiring layer in second connection hole. | 05-19-2016 |
| 20190150268 | SEMICONDUCTOR DEVICE | 05-16-2019 |
