| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 361306200 | For decoupling type capacitor | 13 |
| 20080239622 | WIRING STRUCTURE OF LAMINATED CAPACITORS - The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer. | 10-02-2008 |
| 20080291601 | Integrated Capacitor Arrangement for Ultrahigh Capacitance Values - The present invention relates to an electronic device ( | 11-27-2008 |
| 20080304203 | HIGH CAPACITANCE DENSITY VERTICAL NATURAL CAPACITORS - Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent. | 12-11-2008 |
| 20090059469 | MULTILAYER CHIP CAPACITOR, CIRCUIT BOARD APPARATUS HAVING THE CAPACITOR, AND CIRCUIT BOARD - Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit. | 03-05-2009 |
| 20090207552 | Decoupling capacitors - A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor, said decoupling capacitor comprising an NFET transistor and a PFET transistor, said PFET transistor being substantially formed in said n-type portion and said NFET transistor being substantially formed in said p-type portion, a boundary between said n-type portion and said p-type portion being substantially straight, said transistors being arranged such that a source and drain of said PFET transistor are connected to a high voltage rail and a source and drain of said NFET transistor are connected to a low voltage rail. | 08-20-2009 |
| 20090244807 | MULTILAYER CHIP CAPACITOR, MOTHERBOARD APPARATUS HAVING THE SAME, AND POWER DISTRIBUTION NETWORK - There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged in a laminated direction; and first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first capacitor unit includes first and second inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing a corresponding one of dielectric layers, the second capacitor unit includes third and fourth inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing another corresponding one of the dielectric layers, the first and second capacitor units are electrically insulated from each other, and the first capacitor unit operates in a first frequency range and the second capacitor unit operates in a second frequency range lower than the first frequency range. | 10-01-2009 |
| 20090290282 | MODULAR CHIP STACK AND PACKAGING TECHNOLOGY WITH VOLTAGE SEGMENTATION, REGULATION, INTEGRATED DECOUPLING CAPACITANCE AND COOLING STRUCTURE AND PROCESS - An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component. | 11-26-2009 |
| 20090290283 | Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance. | 11-26-2009 |
| 20100046139 | DECOUPLE CAPACITOR FORMING CIRCUIT, INTEGRATED CIRCUIT UTILIZING THE DECOUPLE CAPACITOR FORMING CIRCUIT AND RELATED METHOD - A method for forming a decouple capacitor of an integrated circuit, the integrated circuit including a core circuit and a plurality of I/O circuits coupled to the core circuit, includes cutting part of a plurality of lines in at least one specific circuit of the I/O circuits to form decouple capacitors of the integrated circuit. | 02-25-2010 |
| 20110149467 | Capacitor Module, Power Converter, Vehicle-Mounted Electrical-Mechanical System - A capacitor module in which the structure of a connecting portion is highly resistant against vibration and has a low inductance. The capacitor module includes a plurality of capacitors and a laminate made up of a first wide conductor and a second wide conductor joined in a layered form with an insulation sheet interposed between the first and second wide conductors. The laminate comprises a first flat portion including the plurality of capacitors which are supported thereon and electrically connected thereto, a second flat portion continuously extending from the first flat portion while being bent, and connecting portions formed at ends of the first flat portion and the second flat portion and electrically connected to the exterior. | 06-23-2011 |
| 20110242725 | CAPACITOR ARRANGEMENT AND METHOD FOR PRODUCING A CAPACITOR ARRANGEMENT - The present invention relates to a capacitor arrangement having a capacitor and a first terminal plate and a second terminal plate. The capacitor has a first contact face and a second contact face arranged opposite one another. The terminal plates are each connected to one of the contact faces and have protrusions on one end suitable for engaging in recesses in a power rail. | 10-06-2011 |
| 20110304949 | CAPACITIVE-STEMMED CAPACITOR - A capacitor having a stem that is designed to be inserted into a single, large-diameter via hole drilled in a printed circuit board is provided, wherein the stem may have conductive rings for making the positive and negative connections to the printed circuit board power distribution planes. Inside the capacitive stem, current, or at least a portion thereof, may be carried to the main body of the capacitor through low-inductance plates that are interleaved to maximize their own mutual inductance and, therefore, minimize the connection inductance. Alternatively, the capacitor may include a coaxial stem that forms a coaxial transmission line with the anode and cathode terminals forming the inner and outer conductors. | 12-15-2011 |
| 20130120903 | DECOUPLING DEVICE AND FABRICATING METHOD THEREOF - A decoupling device including a lead frame, multiple capacitor units, a protective layer and a packaging element is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions disposed at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor units are connected in parallel and disposed on the lead frame. Each capacitor unit has a cathode portion and an opposite anode portion. The cathode portion is electrically connected with the cathode terminal portion. The anode portion is electrically connected with the anode terminal portion. The protective layer wraps at least one of the anode portion and the cathode portion of the capacitor unit. The packaging element covers the lead frame, the capacitor units and the protective layer. The packaging element exposes a bottom surface of the lead frame. | 05-16-2013 |
