Class / Patent application number | Description | Number of patent applications / Date published |
341161000 | Acting sequentially | 56 |
20080198058 | PIPELINED CONVERTER - The invention relates to an apparatus comprising a pipelined converter, such as a pipelined ADC. The pipelined converter has a first set of stages and a second set of stages. A clocking circuit is configured to generate a plurality of clocking signals for the pipelined converter. The plurality of clocking signals comprise a first clocking signal at a first voltage level that is provided to the first set of stages and a second clocking signal at a second voltage level that is provided to the second set of stages. | 08-21-2008 |
20080218396 | Charge-domain pipelined charge-redistribution analog-to-digital converter - A single-ended charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially identical to the charge input to said stage. | 09-11-2008 |
20080266163 | Analog-to-Digital Converter with Reduced Metastable Errors - In an analog-to-digital converter, an analog-to-digital conversion stage comprising a comparator and an analog residual signal generator. The comparator is operable to compare an analog input signal or a sample of the analog input signal with a threshold to generate a bit signal. The analog residual signal generator is operable to generate an analog residual signal from signals comprising the sample of the analog input signal and the bit signal. The analog residual signal generator comprises a summing element, a selective inverter and an amplifier in series. The summing element is operable to sum a signal input to it with a reference signal. The selective inverter precedes the summing element, and is operable in response to a first state of the bit signal to pass a signal input to it, and is operable in response to a second state of the bit signal to invert the signal input to it. | 10-30-2008 |
20090002215 | Sample and Hold Circuit for a Current Mode Pipelined Analog-to-Digital Converter - A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit. | 01-01-2009 |
20090040088 | A/d Converter and A/D Conversion Method - In an A/D converter provided with an A/D converter circuit | 02-12-2009 |
20090040089 | A-TO-D CONVERTER - A successive approximation type A-to-D converter includes a cyclic D-to-A converter ( | 02-12-2009 |
20090073021 | CASCADE COMPARATOR AND CONTROL METHOD THEREOF - A cascade comparator and a control method thereof are provided. By applying multi-phase clock signals to a plurality of comparators when the plurality of comparators are cascaded together so that each comparator is regenerated before the preceding comparator is reset, a hold switch does not need to be provided between the comparators. Therefore, it is possible to reduce the size and parasitic components of a circuit, operate the circuit at a high speed, remove a glitch caused by any hold switch, and accordingly improve system linearity. | 03-19-2009 |
20090128389 | Multi-bit Per Stage Pipelined Analog to Digital Converters - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches. | 05-21-2009 |
20090140904 | INCREASING THE DYNAMIC RANGE OF PULSE WIDTH MODULATION IN ANALOG TO DIGITAL CONVERTERS - This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range. | 06-04-2009 |
20090189798 | ENCODER FOR A PIPELINED ANALOG-TO-DIGITAL CONVERTER - In a pipelined analog-to-digital (AD) converter, if logically incongruent signals S | 07-30-2009 |
20090195433 | MULTISTAGE AMPLIFIER AND A METHOD OF SETTLING THE MULTISTAGE AMPLIFIER - A method of settling an amplifier and a multistage amplifier are provided. To settle an amplifier, a plurality of clock signals are, respectively, applied to preset switches, each of which is placed between amplifiers connected in cascade, to open the preset switches sequentially, thereby settling the amplifiers in order. | 08-06-2009 |
20090201189 | FLASH A/D CONVERTER - A flash analog-to-digital converter comprising a resistive reference ladder, a set of comparators for comparing the analog input signal with the reference voltages of the ladder to provide a digital code representing a coarse quantization of the input signal, a set of switches connected to the reference ladder and controlled by said digital code to provide an analog representation of the coarse quantization of the input signal, means to derive from said analog representation of the coarse quantization and from the input signal one or more residue signals and a fine analog-to-digital converter stage to generate a digital code representing a fine quantization of the one or more residue signals. For minimizing the number of switches required, each selector for one residue signal selects voltages of one half of the ladder at two values of the coarse quantization and the output signals of the two selectors for that residue signal are reversed by a crossover switch when the coarse quantization passes its center value. | 08-13-2009 |
20090243907 | Analog-to-digital converter - A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers. | 10-01-2009 |
20090289827 | FRONT-END SAMPLING TECHNIQUE FOR ANALOG-TO-DIGITAL CONVERTERS - Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals. | 11-26-2009 |
20090309778 | SUCCESSIVE APPROXIMATION TYPE ANALOG/DIGITAL CONVERTER AND OPERATION METHOD OF SUCCESSIVE APPROXIMATION TYPE ANALOG/DIGITAL CONVERTER - In a successive approximation-type A/D converter, an S/H circuit samples and holds an analog input voltage. A D/A converter section receives current digital data corresponding to a current search voltage range, and outputs a plurality of comparison voltages based on the current digital data. A comparator section performs parallel comparison in which the held analog input voltage is compared with each of the plurality of comparison voltages. A successive approximation register section outputs digital data for a next search voltage range within the current search voltage range as the current digital data to the digital-to-analog converter section based on a result of the parallel comparison using the current search voltage range. A timing control circuit generates a switching signal from the parallel comparison to a redundant comparison such that the redundant comparison is performed. | 12-17-2009 |
20100019946 | Amplifier networks with controlled common-mode level and converter systems for use therewith - Effective control of the common-mode level of amplifiers is obtained through control structures (both closed-loop and open-loop structures) which are directed to various amplifier functions such as the reduction of amplifier loading, accurate sensing of common-mode levels, mitigation of headroom restraints, and proper transistor biasing. This common-mode control is especially useful in multiplying analog-to-digital converters (MDACs) of signal processing systems. | 01-28-2010 |
20100060503 | SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, METHOD OF CONTROLLING SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS - A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N-n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed. | 03-11-2010 |
20100066583 | MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TODIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD USING THE SAME - A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC. | 03-18-2010 |
20100156691 | Unified architecture for folding ADC - A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array ( | 06-24-2010 |
20100164778 | CIRCUIT WITH A SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence. | 07-01-2010 |
20100164779 | CHARGE-DOMAIN PIPELINED CHARGE-REDISTRIBUTION ANALOG-TO-DIGITAL CONVERTER - A charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially similar to the charge input to said stage. | 07-01-2010 |
20100207801 | A/D CONVERSION CIRCUIT AND A/D CONVERSION METHOD - An A/D (analog-to-digital) conversion circuit includes an input signal selecting circuit configured to output voltage signals of different signal levels in response to control signals in an adjustment mode before A/D conversion of an analog signal in a practical mode; an A/D converter configured to perform A/D conversion on the voltage signals in response to an adjustment sampling clock signal in the adjustment mode to output adjustment conversion values; and a sampling timing adjusting circuit configured to delay a reference sampling clock signal based on a delay value selected in response to a selection signal in the adjustment mode to output the adjustment sampling clock signal to the A/D converter. An operation circuit is configured to set the adjustment mode, output the control signals to the input signal selecting circuit, and the selection signal to the sampling timing adjusting circuit, such that the adjustment conversion values are obtained at each of different delay values, determine an optimal parameter from parameters corresponding to the obtained adjustment conversion values, and set the practical mode to output the selection signal corresponding to the optimal parameter to the sampling timing adjusting circuit. | 08-19-2010 |
20100289684 | ANALOG-DIGITAL CONVERTER CIRCUIT AND ANALOG-DIGITAL CONVERSION METHOD - Provided is an analog-digital converter circuit including: a comparison unit that sequentially compares an analog input voltage with reference voltages, which sequentially vary, and outputs a comparison result as a digital value; a standard voltage generation unit that generates a standard voltage for correcting the reference voltages; a storage unit that stores a comparison result of the standard voltage obtained by the comparison unit; and a reference voltage generation unit that generates the reference voltages based on the comparison result of the standard voltage. | 11-18-2010 |
20110043400 | SUCCESSIVE APPROXIMATION TYPE AD CONVERTER AND TEST METHOD THEREOF - A successive approximation type analog-to-digital (AD) converter includes: a converting and comparing section configured to compare an input analog signal and an analog signal as an analog conversion result of a digital data; and a successive approximation section configured to change the digital data based on the comparison result by the converting and comparing section. The converting and comparing section includes: a DA (digital-to-analog) section configured to perform an analog conversion on the digital data of a predetermined number of bits in an ordinary mode, and on the digital data of bits smaller than the predetermined number of bits in a test mode. | 02-24-2011 |
20110068966 | Asynchronous Sigma Delta Analog to Digital Converter Using a Time to Digital Converter - This disclosure relates to analog to digital conversion using irregular sampling. A method may include combining an analog signal with a feedback signal into a combined signal, filtering the combined signal using a digital noise shaping filter into a combined noise shaped signal, modulating the combined noise shaped signal into a modulated signal, generating samples of the modulated signal, and reconstructing as a digital signal the analog signal from the samples of the modulated signal. | 03-24-2011 |
20110148684 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code. | 06-23-2011 |
20110298645 | Shared Operational Transconductance Amplifier Pipelined ADC Incorporating a Sample/Hold Amplifier and Multiple MDAC Stages - A single operational transconductance pipelined ADC incorporating a sample/hold amplifier and multiple MDAC stages. An input signal is sampled on input signal sampling capacitors, and then coupled around an operational transconductance amplifier (OTA) so that the output of the OTA is equal to the sampled voltage. There is no net charge transfer in this operation, so the noise and power dissipation normally associated with an input sample and hold circuitry (SHA) in a pipelined ADC is substantially eliminated. A pipelined ADC using a shared OTA for sample/hold and two MDACs is disclosed. | 12-08-2011 |
20120026027 | A/D CONVERTER USING ISOLATION SWITCHES - In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated. | 02-02-2012 |
20120068871 | AD CONVERTER-EQUIPPED TEMPERATURE SENSOR CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - In an AD converter-equipped temperature sensor circuit, at start of operation, a successive approximation type AD converter converts an analog voltage having temperature dependence received from a voltage generation circuit, to determine all bits of the converted digital signal. Thereafter, a power control circuit detects only a change in the outputs of comparators into which reference voltages upwardly and downwardly adjacent to the potential of the analog voltage are input, and shuts off power supply to any comparator other than the above comparators. Thus, in sensing of a steady, slow-changing signal like the analog voltage having temperature dependence using the AD converter, power consumption is reduced and the signal processing time is shortened without degrading the resolution of the AD converter. | 03-22-2012 |
20120092203 | Analog to digital converter and signal processing system - Disclosed herein is an analog to digital converter including an analog to digital conversion stage of at least one stage adapted to produce digital data of a value corresponding to a relationship to two analog signals inputted thereto and output two analog residual signals. The analog to digital conversion stage includes a signal production section, a comparison section, a first outputting section, a second outputting section, and a changeover section. The comparison section outputs first digital data when a first comparison result that the voltage value of the first analog signal is lower than the voltage value of the second analog signal is obtained whereas the comparison section outputs second digital data when a second comparison result that the voltage value of the first analog signal is higher than the voltage value of the second analog signal is obtained. | 04-19-2012 |
20120105264 | ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique. | 05-03-2012 |
20120146829 | SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER CIRCUIT - Techniques are generally described herein for analog to digital conversion. Some example ADC converters include a unit capacitor array coupled to a reference voltage, where the capacitor array includes multiple capacitors coupled to one another via multiple switches under control of a control block. A comparator, having a first input and a second input, is configured to receive a controlled voltage generated from the unit capacitor array and compare an analog voltage to the controlled voltage. The control block is configured to selectively open or close the switches, receive a comparison result from the comparator, and generate a digital output based On the comparison result. The control block is configured to control the switch timing of the unit capacitor array for reset, pre-charge, charge redistribution, and comparison phases, where a passive charge redistribution method may be utilized. | 06-14-2012 |
20120268302 | ANALOG-DIGITAL CONVERTER AND SIGNAL PROCESSING SYSTEM - An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set. | 10-25-2012 |
20130038483 | ANALOG-TO-DIGITAL CONVERTERS AND PIPELINE ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter is provided. The analog-to-digital converter includes a sampling-voltage providing circuit, a first comparison circuit, a second comparison circuit, and an encoder circuit. The sampling-voltage providing circuit provides a group of first comparison voltages and a group of second comparison voltages. The first comparison circuit performs a first comparison operation to an analog-signal input quantity according to the group of first comparison voltages to generate a first comparison digital quantity. The second comparison circuit selects second comparison voltages among the group of second comparison voltages according to the first comparison digital quantity and performs a second comparison operation to the analog-signal input quantity according to the selected second comparison voltages to generate a second comparison digital quantity. The encoder circuit encodes the first comparison digital quantity and the second comparison digital quantity and generates a digital quantity corresponding to the analog-signal input quantity. | 02-14-2013 |
20130099953 | SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTOR AND RELATED CONTROLLING METHOD - A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC. | 04-25-2013 |
20130162457 | Methods and Systems for Compressed Sensing Analog to Digital Conversion - Disclosed herein are example methods, systems, and devices for compressed sensing analog to digital conversion. In an example embodiment, a multiplication circuit is configured to multiply an input signal with a measurement signal to produce a multiplied signal, where the measurement signal includes data from a column of a measurement matrix. The measurement matrix may be generated by a linear feedback shift register (LFSR)-based measurement-matrix generator. An integration circuit may be coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal. An analog to digital converter (ADC) circuit may be coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal. Among other benefits of the disclosure herein, a column-wise multiplication of the input signal with the measurement signal enables an efficient compressed-sensing analog-to-digital conversion architecture. | 06-27-2013 |
20130335250 | HYBRID SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits. | 12-19-2013 |
20140022105 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE - A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns. | 01-23-2014 |
20140055295 | METHODS AND APPARATUS FOR CALIBRATING STAGES IN PIPELINE ANALOG-TO-DIGITAL CONVERTERS - A calibration control circuit is provided for calibrating a stage in a pipeline analog-to-digital converter (ADC). The stage includes an analog-to-digital subconverter (ADSC) and a multiplying digital-to-analog converter (MDAC). The calibration control circuit includes circuitry coupled to comparators in the ADSC to force the comparators to output a predetermined digital output signal set by a calibration control signal when the ADC is in a calibration mode to thereby control reference switches in an analog multiplexer (AMUX) to selectively apply reference voltages to capacitors in the MDAC to obtain a predetermined stage residue signal. | 02-27-2014 |
20140070975 | SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR - According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator. | 03-13-2014 |
20140118176 | METHODS AND APPARATUS FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - Methods and apparatus for a successive approximation register analog to digital converter are provided. In an example, provided is a method for digitally representing an analog input signal. A bit of the digital output signal is generated by altering a test voltage by an amount comparable to a weight afforded to the bit, comparing the altered test voltage with the analog input signal to create a comparison output, switching a two-to-one multiplexer to select the comparison output instead of a preceding shift-successive approximation register block output, storing the comparison output in a flip-flop, inhibiting clocking of the flip-flop, and outputting the comparison output from the flip-flop as the bit of the digital output signal. | 05-01-2014 |
20140145868 | ANALOG-DIGITAL CONVERTER AND ANALOG-DIGITAL CONVERSION METHOD - According to the present invention, a successive approximation type analog-digital converter includes: a comparator outputting a result of comparing an analog signal and a reference voltage; a register storing a digital value corresponding to the result of comparison and outputting a digital signal; a detection unit detecting whether the comparator is in a stable state or not for each bit; and a bit determination unit storing, if the comparator is not stable, as a bit value of a bit which is one bit lower-order than a corresponding detection bit, a value obtained by inverting a final determined bit value of the detection bit in the register instead of the comparison result of the comparator. | 05-29-2014 |
20140176358 | METHOD OF PRODUCING LOW-POWER SWITCHED-CAPACITOR AMPLIFIER, CIRCUIT AND A PIPELINE ANALOG-TO-DIGITAL CONVERTER INCLUDING THE SAME - A switched-capacitor amplifier comprises an operational amplifier (op-amp), a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a plurality of switches connected to these capacitors. The first capacitor equals the third capacitor, the second capacitor equals the fourth capacitor, and the first capacitor is asymmetric to the second capacitor, the third capacitor is asymmetric to the fourth capacitor. A ratio of the first capacitor and the second capacitor is a function of a simulated parasitic capacitance of the switched-capacitor amplifier, a simulated DC gain of the operational amplifier, and a target gain of the switched-capacitor circuit. | 06-26-2014 |
20140184435 | Successive Approximation Register Analog-to-Digital Converter with Multiple Capacitive Sampling Circuits and Method - A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase. | 07-03-2014 |
20140184436 | APPARATUS AND METHODS FOR CONVERTING ANALOG SIGNAL TO N-BIT DIGITAL DATA - An apparatus includes a sample holding circuit, a comparator, a digital-to-analog converter, a clock generator, a successive approximation logic circuit, and a background calibration circuit. The apparatus converts an analog signal into digital data based on an asynchronous clock signal. The clock signal follows the number of clocks in a converting operation section through a background calibration scheme. | 07-03-2014 |
20140240158 | AD CONVERTER AND AD CONVERSION METHOD - An A/D converter includes a plurality of AD converting sections that sequentially operate at predetermined intervals. The AD converting section has an ADC that converts an analog signal into a digital signal and outputs the digital signal, a memory that stores, as a specific polarity value, the polarity of a signal obtained by the ADC digitizing an analog signal at a reference voltage, an analog polarity converting circuit that inverts the polarity of the analog signal based on the specific polarity value and a set polarity value, which is previously set, and a digital polarity converting circuit that inverts the polarity of the digital signal based on the specific polarity value and the set polarity value. | 08-28-2014 |
20150042501 | CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER - A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. | 02-12-2015 |
20150061912 | ANALOG-TO-DIGITAL CONVERTER AND CONTROL CIRCUIT WITH A LOW QUIESCENT CURRENT AT LOW LOAD - A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator. | 03-05-2015 |
20150070203 | MIXED-SIGNAL CIRCUITRY - Mixed-signal circuitry, comprising: an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; and a controller, wherein: at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; and the controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication. | 03-12-2015 |
20150091746 | Successive Approximation Register Analog-to-Digital Converter With Single-Ended Measurement - A circuit may include a comparator having a first input, a second input, and an output. The circuit further may further include a successive approximation register (SAR) circuit coupled to the output of the comparator, the first input, and the second input. The SAR circuit may be configured to program one or more capacitors to selectively bias the first input to provide a single-ended measurement of a voltage at the second input. | 04-02-2015 |
20150102952 | COMPARATOR AND ANALOG-TO-DIGITAL CONVERTER - Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback. | 04-16-2015 |
20160020778 | METHOD AND DEVICE FOR USE IN ANALOG-TO-DIGITAL CONVERSION - Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed. | 01-21-2016 |
20160094239 | SEMICONDUCTOR DEVICE - A semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits. | 03-31-2016 |
20160204789 | MULTICHANNEL ANALOG-TO-DIGITAL CONVERTER | 07-14-2016 |
20160254821 | Successive Approximation Register-based Analog-to-Digital Converter with Increased Time Frame for Digital-to-Analog Capacitor Settling | 09-01-2016 |
20220140837 | ADC SLICER RECONFIGURATION FOR DIFFERENT CHANNEL INSERTION LOSS - A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver. | 05-05-2022 |