| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327437000 | Complementary metal-oxide semiconductor (CMOS) | 49 |
| 20080204114 | TRANSMISSION GATE SWITCH, SYSTEM USING THE SAME, AND DATA INPUT/OUTPUT METHOD THEREOF - A transmission gate switch includes a switching unit to conduct a switching operation between first and second nodes in response to a switching signal, and an isolation unit to prevent the switching unit from being turned on by a negative swing of the first or second node while the switching unit is being turned off. | 08-28-2008 |
| 20080211569 | Higher voltage switch based on a standard process - A higher voltage switching circuit based on a standard process limits the lowest applied voltage to an intermediate voltage between the higher voltage and ground, instead of ground. In this way, the maximum electric field across the gate dielectric is greatly reduced. In additional the use of p-type triple well also reduces junction breakdown in some embodiments. This concept is also valid in the case where the high voltage is negative, in which case the intermediate voltage is also negative. | 09-04-2008 |
| 20090134933 | OUTPUT DRIVER AND METHOD OF OPERATION THEREOF - The method of the present invention for switching an output driver of the type comprising an n-mos transistor and a p-mos transistor configured in a push-pull arrangement operates by directly monitoring the level of the output signal OUT. The method comprises slowly switching off the input to the initially designated active transistor; monitoring the variation in output voltage level in response thereto; and when a desired change in output level is detected the switching the initially designated output transistor on completely and fast. Using this method the parasitic currents in the diodes are much smaller in time and amplitude. | 05-28-2009 |
| 20090289693 | BI-DIRECTIONAL BUFFER AND METHOD FOR BI-DIRECTIONAL BUFFERING THAT REDUCE GLITCHES DUE TO FEEDBACK - A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal. | 11-26-2009 |
| 20090309647 | High voltage tolerant pass-gate assembly for an integrated circuit - A high-voltage tolerant pass-gate assembly ( | 12-17-2009 |
| 20100090747 | HIGH-FREQUENCY SWITCH CIRCUIT - A high frequency switch circuit according to the present invention includes a control-voltage-generating circuit. The control-voltage-generating circuit includes a depletion type field-effect transistor, an external-control-signal-input terminal, an internal-control-voltage-output terminal, and a power-receiving terminal of the control-voltage-generating circuit. The field-effect transistor has a grounded gate, a source connected to the external-control-signal-input terminal, and a drain connected to the power-receiving terminal. The internal-control-voltage-output terminal is connected to an electrical connection path between the drain of the field-effect transistor and the power-receiving terminal. | 04-15-2010 |
| 20100148851 | LOW VOLTAGE ANALOG CMOS SWITCH - A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit. | 06-17-2010 |
| 20100164600 | NOVEL CHARGE PUMP - A charge pump circuit includes a first voltage supply circuit configured to provide a first supply voltage in response to a first and second input signals. A first capacitor is coupled to the first voltage supply circuit. A first switch circuit is configured to provide a second supply voltage to a second terminal of the first capacitor in response to a first control signal. A second switch circuit is coupled to the second terminal of the first capacitor. A second capacitor is coupled to the second switch circuit. The second switch circuit is configured to cause charge transfer from the first capacitor to the second capacitor in response to a second control signal. The charge pump also includes an output terminal coupled to the second capacitor to provide an output voltage, the output voltage being higher than the first supply voltage, the output voltage being also higher than the second supply voltage. | 07-01-2010 |
| 20100214006 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - There is provided a circuit whose output is free from high impedance to improve wrong transmission and waveform overshoot, realizing a semiconductor integrated circuit device in which plural channels is integrated with transmitter circuit as unit channel, in the transmitter circuit used in a medical ultrasound system and drives a transducer by voltage pulses having plural positive and negative electric potentials including ground potential. The transmitter circuit includes a conventional pulse generating circuit supplied with positive and negative voltage largest in absolute value, a P-channel analog switching pulse generating circuit supplied with positive voltage being the second largest therein, an N-channel analog switching pulse generating circuit supplied with negative voltage being the second largest, and an N-channel analog switching ground level damping circuit supplied with ground potential. The circuits are connected to output terminal. Switch control signals drive ultrasound transducers by turning on and off the circuits. | 08-26-2010 |
| 20100219878 | SEMICONDUCTOR SWITCH CIRCUIT - A semiconductor switch circuit is provided that enables current consumption to be reduced even in a conduction state. A semiconductor switch circuit | 09-02-2010 |
| 20100244930 | SEMICONDUCTOR DEVICE FOR OUTPUT OF PULSE WAVEFORMS - A semiconductor device has multiple high-side field-effect transistors and multiple low-side field-effect transistors connected to a single output terminal to generate an output signal. A driver circuit outputs driving signals that turn the field-effect transistors on and off. The driving signal for the field-effect transistors on each side is conducted by a salicided gate line with salicide block areas that produce successive delays, causing the field-effect transistors to turn on sequentially. Alternatively, the transistors have different threshold voltages, or the driving signals for different transistors are output from drivers with different driving abilities, again causing the transistors to turn on sequentially. The output signal therefore rises and falls gradually, reducing electromagnetic interference. | 09-30-2010 |
| 20100277220 | SELF BIASED GATE CONTROLLED SWITCH - Conventional current sharing circuits, which can be used in drivers for liquid crystal displays (LCDs), for example, often use bipolar transistors. However, bipolar transistors are not available in many CMOS processes. Thus, a current sharing circuit is provided here that employs CMOS transistors. In particular, the circuit provided here uses a current mirror and pass circuit to assist in providing this current sharing function. | 11-04-2010 |
| 20100308891 | CASCODE SWITCHING CIRCUIT - A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages. | 12-09-2010 |
| 20110080206 | SYSTEM AND METHOD FOR NEGATIVE VOLTAGE PROTECTION - An electronic system is disclosed, which includes a connector unit to communicate data with a host system, an electronic circuit to store the data, and a switch to convey the data to and from the electronic circuit via the connector unit. The switch includes a negative voltage protection unit coupled to the connector unit, and a transistor switch coupled to the negative voltage protection unit, the connector unit, and the electronic circuit. The negative voltage protection unit forces the transistor switch off if a negative voltage is detected. | 04-07-2011 |
| 20110140764 | CMOS SWITCH FOR USE IN RADIO FREQUENCY SWITCHING AND ISOLATION ENHANCEMENT METHOD - Provided is a CMOS switch for use in RF switching having improved isolation properties. The CMOS switch includes a serial switching unit having first and second CMOS switches, a switching isolation unit for allowing an unselected output terminal of two output terminals to be electrically isolated from a common input terminal when the serial switching unit operates and an isolation enhancement unit. The isolation enhancement unit is connected in parallel to the first and the second CMOS switches between the two output terminals forming a parallel resonance circuit together with a parasitic capacitor of the serial switching unit. The CMOS switch for use in RF switching according to the present invention has a simple circuit structure and excellent operating properties at the MF or higher band. Also, the CMOS switch having high isolation properties is realized. | 06-16-2011 |
| 20110148507 | SWITCH-BODY NMOS-PMOS SWITCH WITH COMPLEMENTARY CLOCKED SWITCH-BODY NMOS-PMOS DUMMIES - A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs. | 06-23-2011 |
| 20110193615 | TRANSMISSION GATE AND SEMICONDUCTOR DEVICE - Provided is a transmission gate capable of adapting to various input voltages to attain high S/N characteristics. The transmission gate includes: a PMOS transistor ( | 08-11-2011 |
| 20110234298 | REFERENCE VOLTAGE CIRCUIT - Provided is a reference voltage circuit having a soft start function, which is small in circuit size and is capable of providing a continuous voltage. The reference voltage circuit includes a reference voltage section and a soft start circuit. The reference voltage section includes a depletion mode MOS transistor and a first enhancement mode MOS transistor. The soft start circuit includes: a second enhancement mode MOS transistor having a gate connected to a gate and a drain of the first enhancement mode MOS transistor, and a drain connected to an output terminal of the reference voltage circuit; a MOS switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode MOS transistor; and a constant current source and a capacitor connected in series between a power supply and a ground. | 09-29-2011 |
| 20110298526 | APPARATUS AND METHOD FOR DISABLING WELL BIAS - Apparatuses and methods for disabling well bias are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well. The gate is formed adjacent the well between the source and drain, and the source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a well bias control block for biasing the well voltage of the first switch and a disable circuit for disabling the well bias control block so as to prevent the well bias control block from biasing the well. The well bias control block can bias the well voltage of the first switch to at least two voltage levels. | 12-08-2011 |
| 20110316610 | TRANSMISSION GATE CIRCUITRY FOR HIGH VOLTAGE TERMINAL - A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area. | 12-29-2011 |
| 20120013390 | DISPLAYPORT SWITCH - In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the switch activates the auxiliary channel, which can result in errors. Here, a switch is employed that uses precharge circuits to precharge these capacitors. Thus, errors due to charging of these capacitors can be reduced. | 01-19-2012 |
| 20120013391 | ADAPTIVE BOOTSTRAP CIRCUIT FOR CONTROLLING CMOS SWITCH(ES) - An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type. | 01-19-2012 |
| 20120044012 | REFERENCE VOLTAGE GENERATOR CIRCUIT AND IMAGE PROCESSING APPARATUS - A reference current generating circuit includes a generator that generates a reference voltage, a bias generator includes plural transistors of a different conductive types from each other and generates a first bias voltage and a second bias voltage, respectively, a first output transistor and a second output transistor of a different conductive type that outputs a current corresponds to a reference current when the first bias voltage or the second bias voltage is supplied thereto, an input-output unit that one terminal connected between the first output transistor and the second output terminal and the other terminal connected to a load, and supplies current from the first output transistor to the load or from the load to the second output transistor, and a switch that turns on/off the first and the second output transistors based on the output voltage of the input-output unit. | 02-23-2012 |
| 20120081172 | High Voltage Switch Suitable for Use in Flash Memory - A high voltage switch is presented that, rather than relying upon a charge pump to boost the voltage applied to the switches gate in order to compensate for the switch's threshold voltage, a combination of high voltage devices to eliminate the threshold voltage from the switch. This will save on the needed circuit area and reduce the current and, consequently, power consumption. In the exemplary embodiment, the switch circuit passes an input voltage from an input node to an output node in response to an enable signal. The switch includes a level shifter connected to the input node and is connected to receive the enable signal to provide the input voltage as output when the enable signal is asserted. The circuit also includes a first depletion type NMOS transistor that is connected between the input node and a first intermediate node and having a gate connected to receive the output of the level shifter, and a PMOS transistor that is connected between the first intermediate node and the output node and having a gate connected to receive an inverted form of the enable signal. | 04-05-2012 |
| 20120206188 | SYSTEMS AND METHODS FOR DYNAMIC MOSFET BODY BIASING FOR LOW POWER, FAST RESPONSE VLSI APPLICATIONS - Systems and methods in accordance with embodiments of the invention are disclosed that include MOSFET transistor operation by adjusting V | 08-16-2012 |
| 20120274387 | RF Switching System, Module, and Methods with Improved High Frequency Performance - Embodiments of radio frequency switching systems, modules, and methods with improved high frequency performance are described generally herein where the switching module may include a first switch module coupled in series to a second switch module, and a third switch module coupled between the first and the second module and ground. A controllable element of the second module may have a lower off capacitance than a controllable element of the first module. Other embodiments may be described and claimed. | 11-01-2012 |
| 20120299637 | SWITCH CIRCUITS - A switch can be implemented by a switch circuit, which can include a pair of NMOS transistors connected in series as pass-through transistors to transmit an input signal at an input terminal to produce an output signal at output terminal in response to an active state of a switching signal, and a pair of PMOS transistors connected in series as pass-through transistors to transmit the input signal at the input terminal to produce the output signal at output terminal in response to the active state of the switching signal. The switch circuit can also include a switch network connecting, in response to the active state of the switching signal, sources to bodies of the pairs of NMOS and PMOS transistors, and connecting, in response to an inactive state of the switching signal, the bodies of the pair of NMOS transistors to a first reference voltage, the bodies of the pair of PMOS transistors to a second reference voltage, and the sources of the pairs of NMOS and PMOS transistors to a third reference voltage. A capacitance-to-voltage converter can include one or more of the switch circuits. | 11-29-2012 |
| 20130009693 | PIPELINE POWER GATING FOR GATES WITH MULTIPLE DESTINATIONS - A first and second plurality of gates are coupled respectively between first and second source storage elements and first and second destination storage elements. The first and second plurality of gates are slept to reduce leakage current in the plurality of gates under certain conditions by turning off respective one or more transistors between the first and second plurality of gates and power supplies. A third plurality of gates are maintained in a reduced leakage current state (sleep state) or regular state (wake state) based on conditions associated with the source and destination elements for the first and second plurality of gates. | 01-10-2013 |
| 20130027114 | High Side Switch - A semiconductor chip includes at least one power semiconductor switch configured to activate and deactivate current conduction from a first supply terminal, which is connected to a first supply line that provides an unstabilized first supply voltage, to the at least one output terminal in accordance with a respective control signal. In operation, the unstabilized first supply voltage is monitored and an under-voltage is signaled when the unstabilized first supply voltage falls below a first threshold value. The first supply terminal is short circuited with a third terminal when the an under-voltage is signaled. | 01-31-2013 |
| 20130033302 | INPUT SWITCHES IN SAMPLING CIRCUITS - A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase. | 02-07-2013 |
| 20130127520 | TRACKING CIRCUIT - A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage. | 05-23-2013 |
| 20130147541 | CIRCUIT FOR CLEARING DATA STORED IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR - An exemplary circuit for clearing data stored in a complementary metal-oxide-semiconductor (CMOS) includes a power circuit and a button circuit. The power circuit supplies power for the CMOS. The button circuit is configured to clear data stored in the CMOS, and includes a switch and an electronic switch element. A first terminal of the switch is grounded, and a second terminal of the switch is coupled to a first terminal of the electronic switch element. A second terminal of the electronic switch element is grounded. A third terminal of the electronic switch element is coupled to the CMOS. When the switch is closed, the second terminal of the electronic switch element is connected to the third terminal of the electronic switch element, and the data stored in the CMOS is cleared. | 06-13-2013 |
| 20130314147 | SEMICONDUCTOR PROCESSING DEVICE AND SEMICONDUCTOR PROCESSING SYSTEM - A semiconductor processing device ( | 11-28-2013 |
| 20130321063 | MOS SWITCH - This document discusses, among other things, a switch circuit including a switch having a low-impedance state configured to couple a first node to a second node and a high-impedance state configured to isolate the first node from the second node. The switch circuit can include an arbiter circuit configured to receive a source voltage and an input signal, to provide, at an output, the higher voltage of the source voltage and the input signal, and to isolate the input signal form ground when the input signal has a lower voltage than the source voltage. | 12-05-2013 |
| 20140043093 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - Direct-path current is reduced in a semiconductor device including CMOS circuits. One embodiment of the present invention is a method for driving a semiconductor device that includes a first CMOS circuit between power supply lines, a first transistor between the power supply lines, a second CMOS circuit between the power supply lines, and a second transistor between an output terminal of the first CMOS circuit and an input terminal of the second CMOS circuit. The first transistor and the second transistor each have lower off-state current than a transistor included in the first CMOS circuit. In a period during which the voltage of a first signal input to the first CMOS circuit is changed, a second signal is input to the first transistor and the second transistor to turn off the first transistor and the second transistor. | 02-13-2014 |
| 20140043094 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor having a p-channel type, a second transistor having an n-channel type, and a third transistor with low off-state current between a high potential power supply line and a low potential power supply line, and a source terminal and a drain terminal of the third transistor are connected so that the third transistor is connected in series with the first transistor and the second transistor between the high potential power supply line and the low potential power supply line, and the third transistor is turned off when both the first transistor and the second transistor are in conducting states. | 02-13-2014 |
| 20140084988 | SWITCH ARCHITECTURE AT LOW SUPPLY VOLTAGES - A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage. | 03-27-2014 |
| 20140159799 | MULTIPLEX DRIVING CIRCUIT - A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals. | 06-12-2014 |
| 20140176227 | DATA CONTROL CIRCUIT - A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit. | 06-26-2014 |
| 20140197879 | METHOD AND APPARATUS FOR REDUCING CROWBAR CURRENT - Techniques for reducing crowbar current are disclosed. In one embodiment, a circuit for reducing crowbar current comprises an inverter having an input and an output, a first switch coupled between the inverter and a first power supply rail, and a second switch coupled between the inverter and a second power supply rail. The circuit also comprises a feedback circuit coupled to the output of the inverter, wherein the feedback circuit is configured to turn off the first switch when the output of the inverter is in a low output state, and to turn off the second switch when the output of the inverter is in a high output state. | 07-17-2014 |
| 20140333367 | METAL-OXIDE-SEMICONDUCTOR (MOS) VOLTAGE DIVIDER WITH DYNAMIC IMPEDANCE CONTROL - Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path. | 11-13-2014 |
| 20140361825 | SWITCH CIRCUIT - Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from GND to VDD to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding PMOS transistors to NMOS transistors constituting the switch circuit and controlling gates of the PMOS transistors by a voltage of the input terminal, the transmission or interruption of the voltage of from GND to VDD can be reliably controlled. | 12-11-2014 |
| 20150070077 | SIGNAL DISTRIBUTION CIRCUITRY - Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines. | 03-12-2015 |
| 20150137873 | Fet Array Bypass Module - A bypass module including a plurality of P-Channel MOSFETs connected in parallel to form a P-Channel MOSFET array, a plurality of N-Channel MOSFETs connected in parallel to form a N-Channel MOSFET array, and a control module to control switching of the P-Channel MOSFET array and the N-Channel MOSFET array is disclosed. A battery or load management device used to switch higher current and low voltages is disclosed. A battery bypass and bypass method for charge, discharge, and charge limiting control for various types of batteries is disclosed. | 05-21-2015 |
| 20150318853 | Gate Boosting Transmission Gate - A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold. | 11-05-2015 |
| 20160036428 | Fine-Grained Power Gating in FPGA Interconnects - Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation. | 02-04-2016 |
| 20160056816 | SWITCHING CIRCUIT - A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The switching circuit further includes a gate voltage generating circuit configured to switch voltage applied to the gate of the PLDMOS between a first voltage and a second voltage, wherein the first voltage is substantially the same as an input voltage from the converting circuit, and wherein a difference between the first voltage and the second voltage is lower than the gate-source breakdown voltage of the PLDMOS. | 02-25-2016 |
| 20160134280 | Bidirectional Integrated CMOS Switch - A bidirectional integrated CMOS switch is provided which is capable of switching voltages beyond the range of the supply and ground potentials. The switch is composed of NMOS and PMOS transistors as the switch conductor path, a diode bridge, and control circuitry to turn the switch on and off by means of low voltage logic, regardless of the voltages on the switch terminals. The device and method of the invention enables the switching of high voltage loads operating at arbitrary or floating voltages relative to the low voltage power supply and ground, and provides on/off control of the switch with ordinary low voltage logic levels. The invention provides bidirectional switching without conducting through the parasitic body diodes of the CMOS devices. | 05-12-2016 |
| 20160164497 | MINIMIZATION OF BIAS TEMPERATURE INSTABILITY (BTI) DEGRADATION IN CIRCUITS - A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state. | 06-09-2016 |
