| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327380000 | Preventing quick rise gating current (i.e., di/dt) | 8 |
| 20130207713 | Coincident Tracking Turn-On For Mixed Voltage Logic - A method for dealing with high inrush current when voltage is applied to mixed voltage logic integrated circuits is disclosed. A depletion N-Channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or junction Field Effect Transistor (JFET) is added to a linear voltage regulator in mixed voltage logic integrated circuits. The Field Effect Transistor (FET) is utilized to allow the core voltage to come up with Input/Output voltage prior to turn-on of linear voltage regulator. Turn-on state of FET allows the core voltage to rise with Input/Output voltage until the FET threshold is reached across the gate. When threshold is reached, the FET turns off to allow linear voltage regulator turn on and take over supply power. | 08-15-2013 |
| 20130222043 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the device, a pair of transistors includes first and second transistors connected in parallel between a power-supply-line and a power-supply or between a ground-line and a ground-potential. A third transistor is connected between the power-supply-line and the power-supply or between the ground-line and the ground-potential. First to third nodes are gate nodes of the first to third transistors. A first buffer outputs a first control-signal for controlling the first transistor. A second buffer is connected between the first node and the second and third nodes to receive the first control-signal and transmit a second control-signal for controlling the second and third transistors to the second and third nodes in parallel. When power-supplying starts, the second control signal drives the second and third transistors to the conductive-state after the first control-signal controls the first transistor to be driven in an intermediate-state between the conductive-state and a shutoff-state. | 08-29-2013 |
| 20140015591 | GATE PROTECTED SEMICONDUCTOR DEVICES - Providing gate protection to a group III-semiconductor device by delivering gate overdrive immunity is described herein. The gate protection can be achieved by embedding a gate-voltage-controlling second transistor to the gate electrode of a first transistor. In other words, a first gate electrode of the first semiconductor device is in series with a second source electrode of the second semiconductor device, and a second gate electrode of the second semiconductor device is connected to the second source electrode and the first gate electrode. | 01-16-2014 |
| 20140022001 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level. | 01-23-2014 |
| 20140132331 | Wide Common Mode Range Transmission Gate - A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal. | 05-15-2014 |
| 20140354345 | SWITCH CONTROL CIRCUIT, SWITCHING POWER SUPPLY, AND ELECTRONIC APPARATUS - A switch control circuit that includes a control unit configured to generate a control signal; a switch driving unit configured to drive a switch element based on the control signal; and a slew rate adjusting unit configured to control the switch driving unit to change a slew rate of the switch element periodically in a predetermined change pattern. | 12-04-2014 |
| 20150341028 | GATE DRIVE UNIT AND METHOD FOR CONTROLLING A GATE DRIVE UNIT - A gate drive unit includes a charging device, a switch, and a timing module. The charging device is conductively coupled with an electrical energy source and a power switch between the electric energy source and the charging device. The switch closes to transfer electrical energy from the energy source to the charging device. The timing module is configured to close the switch to direct the electrical energy from the electrical energy source to the charging device for a designated charging time period in order to charge the charging device with the electrical energy while the power switch is in an OFF state. The timing module opens the switch to cause the electrical energy stored in the charging device to be transferred out of the charging device in the form of a trigger current that is conducted to a gate terminal of the power switch to activate the power switch to an ON state from the OFF state. | 11-26-2015 |
| 20160028392 | SOLID STATE POWER CONTROLLER - A solid state power controller including: a plurality of pairs of FETs connected in parallel, each pair comprising a first, forward-facing FET and a second, backward-facing FET connected by their respective sources; gate drive means for switching said FETs on and off; and means for isolating the sources of the backwards-facing FETs of the plurality of pairs of FETs from each other and operating the backwards-facing FETs in 3 | 01-28-2016 |
